intel_idle: Add ->enter_freeze callbacks
Add an ->enter_freeze callback routine, intel_idle_freeze(), to the intel_idle driver and point the ->enter_freeze callback pointers of all of the driver's state objects to it. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
This commit is contained in:
Rafael J. Wysocki
Rafael J. Wysocki
Родитель
124cf9117c
Коммит
5fe2e52720
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@ -97,6 +97,8 @@ static const struct idle_cpu *icpu;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static void intel_idle_freeze(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static int intel_idle_cpu_init(int cpu);
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static struct cpuidle_state *cpuidle_state_table;
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@ -131,28 +133,32 @@ static struct cpuidle_state nehalem_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 3,
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.target_residency = 6,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-NHM",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-NHM",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-NHM",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 800,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -164,35 +170,40 @@ static struct cpuidle_state snb_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-SNB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-SNB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 211,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-SNB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 104,
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.target_residency = 345,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-SNB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 109,
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.target_residency = 345,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -204,42 +215,48 @@ static struct cpuidle_state byt_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-BYT",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 15,
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.target_residency = 30,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6N-BYT",
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.desc = "MWAIT 0x58",
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.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 40,
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.target_residency = 275,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6S-BYT",
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.desc = "MWAIT 0x52",
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.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.target_residency = 560,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-BYT",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 1200,
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.target_residency = 1500,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7S-BYT",
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.desc = "MWAIT 0x64",
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.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 10000,
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.target_residency = 20000,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -251,35 +268,40 @@ static struct cpuidle_state ivb_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 156,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 300,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-IVB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 87,
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.target_residency = 300,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -291,28 +313,32 @@ static struct cpuidle_state ivt_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVT",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 80,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 156,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVT",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 82,
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.target_residency = 300,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -324,28 +350,32 @@ static struct cpuidle_state ivt_cstates_4s[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVT-4S",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 250,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT-4S",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 300,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVT-4S",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 84,
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.target_residency = 400,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -357,28 +387,32 @@ static struct cpuidle_state ivt_cstates_8s[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVT-8S",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 500,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT-8S",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 600,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVT-8S",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 88,
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.target_residency = 700,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -390,56 +424,64 @@ static struct cpuidle_state hsw_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-HSW",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-HSW",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 33,
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.target_residency = 100,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-HSW",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 133,
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.target_residency = 400,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7s-HSW",
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.desc = "MWAIT 0x32",
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.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 166,
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.target_residency = 500,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C8-HSW",
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.desc = "MWAIT 0x40",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 300,
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.target_residency = 900,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C9-HSW",
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.desc = "MWAIT 0x50",
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.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 600,
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.target_residency = 1800,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C10-HSW",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 2600,
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.target_residency = 7700,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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@ -450,56 +492,64 @@ static struct cpuidle_state bdw_cstates[] = {
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.flags = MWAIT2flg(0x00),
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-BDW",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-BDW",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 40,
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.target_residency = 100,
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.enter = &intel_idle },
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-BDW",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 133,
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.target_residency = 400,
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.enter = &intel_idle },
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.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C7s-BDW",
|
||||
.desc = "MWAIT 0x32",
|
||||
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 166,
|
||||
.target_residency = 500,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C8-BDW",
|
||||
.desc = "MWAIT 0x40",
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 300,
|
||||
.target_residency = 900,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C9-BDW",
|
||||
.desc = "MWAIT 0x50",
|
||||
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 600,
|
||||
.target_residency = 1800,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C10-BDW",
|
||||
.desc = "MWAIT 0x60",
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 2600,
|
||||
.target_residency = 7700,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.enter = NULL }
|
||||
};
|
||||
|
|
@ -511,28 +561,32 @@ static struct cpuidle_state atom_cstates[] = {
|
|||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C2-ATM",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10),
|
||||
.exit_latency = 20,
|
||||
.target_residency = 80,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C4-ATM",
|
||||
.desc = "MWAIT 0x30",
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 100,
|
||||
.target_residency = 400,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C6-ATM",
|
||||
.desc = "MWAIT 0x52",
|
||||
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 140,
|
||||
.target_residency = 560,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.enter = NULL }
|
||||
};
|
||||
|
|
@ -543,14 +597,16 @@ static struct cpuidle_state avn_cstates[] = {
|
|||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C6-AVN",
|
||||
.desc = "MWAIT 0x51",
|
||||
.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 15,
|
||||
.target_residency = 45,
|
||||
.enter = &intel_idle },
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.enter = NULL }
|
||||
};
|
||||
|
|
@ -592,6 +648,21 @@ static int intel_idle(struct cpuidle_device *dev,
|
|||
return index;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
|
||||
* @dev: cpuidle_device
|
||||
* @drv: cpuidle driver
|
||||
* @index: state index
|
||||
*/
|
||||
static void intel_idle_freeze(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index)
|
||||
{
|
||||
unsigned long ecx = 1; /* break on interrupt flag */
|
||||
unsigned long eax = flg2MWAIT(drv->states[index].flags);
|
||||
|
||||
mwait_idle_with_hints(eax, ecx);
|
||||
}
|
||||
|
||||
static void __setup_broadcast_timer(void *arg)
|
||||
{
|
||||
unsigned long reason = (unsigned long)arg;
|
||||
|
|
|
|||
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