Merge branch 'x86-x2apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-x2apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, x2apic: Simplify apic init in SMP and UP builds x86, intr-remap: Remove IRTE setup duplicate code x86, intr-remap: Set redirection hint in the IRTE
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5fe8321b88
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@ -3,4 +3,31 @@
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#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
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#ifdef CONFIG_INTR_REMAP
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static inline void prepare_irte(struct irte *irte, int vector,
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unsigned int dest)
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{
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memset(irte, 0, sizeof(*irte));
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irte->present = 1;
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irte->dst_mode = apic->irq_dest_mode;
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/*
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* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
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* actual level or edge trigger will be setup in the IO-APIC
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* RTE. This will help simplify level triggered irq migration.
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* For more details, see the comments (in io_apic.c) explainig IO-APIC
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* irq migration in the presence of interrupt-remapping.
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*/
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irte->trigger_mode = 0;
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irte->dlvry_mode = apic->irq_delivery_mode;
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irte->vector = vector;
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irte->dest_id = IRTE_DEST(dest);
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irte->redir_hint = 1;
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}
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#else
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static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
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{
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}
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#endif
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#endif /* _ASM_X86_IRQ_REMAPPING_H */
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@ -1665,10 +1665,7 @@ int __init APIC_init_uniprocessor(void)
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}
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#endif
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#ifndef CONFIG_SMP
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enable_IR_x2apic();
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default_setup_apic_routing();
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#endif
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verify_local_APIC();
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connect_bsp_APIC();
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@ -1382,21 +1382,7 @@ int setup_ioapic_entry(int apic_id, int irq,
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if (index < 0)
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panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
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memset(&irte, 0, sizeof(irte));
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irte.present = 1;
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irte.dst_mode = apic->irq_dest_mode;
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/*
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* Trigger mode in the IRTE will always be edge, and the
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* actual level or edge trigger will be setup in the IO-APIC
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* RTE. This will help simplify level triggered irq migration.
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* For more details, see the comments above explainig IO-APIC
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* irq migration in the presence of interrupt-remapping.
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*/
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irte.trigger_mode = 0;
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irte.dlvry_mode = apic->irq_delivery_mode;
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irte.vector = vector;
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irte.dest_id = IRTE_DEST(destination);
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prepare_irte(&irte, vector, destination);
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/* Set source-id of interrupt request */
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set_ioapic_sid(&irte, apic_id);
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@ -3340,14 +3326,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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ir_index = map_irq_to_irte_handle(irq, &sub_handle);
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BUG_ON(ir_index == -1);
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memset (&irte, 0, sizeof(irte));
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irte.present = 1;
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irte.dst_mode = apic->irq_dest_mode;
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irte.trigger_mode = 0; /* edge */
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irte.dlvry_mode = apic->irq_delivery_mode;
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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prepare_irte(&irte, cfg->vector, dest);
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/* Set source-id of interrupt request */
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if (pdev)
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@ -54,6 +54,9 @@ static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
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*/
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void __init default_setup_apic_routing(void)
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{
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enable_IR_x2apic();
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#ifdef CONFIG_X86_X2APIC
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if (x2apic_mode
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#ifdef CONFIG_X86_UV
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@ -1120,8 +1120,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
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}
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set_cpu_sibling_map(0);
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enable_IR_x2apic();
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default_setup_apic_routing();
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if (smp_sanity_check(max_cpus) < 0) {
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printk(KERN_INFO "SMP disabled\n");
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@ -1129,6 +1127,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
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goto out;
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}
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default_setup_apic_routing();
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preempt_disable();
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if (read_apic_id() != boot_cpu_physical_apicid) {
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panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
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