pinctrl: sunxi: Add external interrupts support
The port controller IP found in the Allwinner A10 and A13 can use few of the pins it manage as an interrupt source, called external interrupts in the datasheet. The number of these external interrupts are SoCs specific, but the current upper limit is 32. In order to work, the external interrupts' pins have to be muxed to a specific function to generate an interrupt. This patch adds the irqchip and the needed logic to use the PIO controller as an interrupt controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Maxime Ripard
Linus Walleij
Родитель
814d4f2e15
Коммит
60242db1a7
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@ -13,10 +13,12 @@
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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@ -1796,6 +1798,26 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
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return pin;
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}
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static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
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struct sunxi_desc_function *desc;
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if (offset > chip->ngpio)
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return -ENXIO;
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desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
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if (!desc)
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return -EINVAL;
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pctl->irq_array[desc->irqnum] = offset;
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dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
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chip->label, offset + chip->base, desc->irqnum);
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return irq_find_mapping(pctl->domain, desc->irqnum);
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}
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static struct gpio_chip sunxi_pinctrl_gpio_chip = {
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.owner = THIS_MODULE,
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.request = sunxi_pinctrl_gpio_request,
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@ -1805,10 +1827,118 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip = {
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.get = sunxi_pinctrl_gpio_get,
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.set = sunxi_pinctrl_gpio_set,
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.of_xlate = sunxi_pinctrl_gpio_of_xlate,
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.to_irq = sunxi_pinctrl_gpio_to_irq,
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.of_gpio_n_cells = 3,
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.can_sleep = 0,
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};
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static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
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unsigned int type)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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u32 reg = sunxi_irq_cfg_reg(d->hwirq);
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u8 index = sunxi_irq_cfg_offset(d->hwirq);
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u8 mode;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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mode = IRQ_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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mode = IRQ_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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mode = IRQ_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mode = IRQ_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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mode = IRQ_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
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return 0;
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}
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static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
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u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
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u32 status_reg = sunxi_irq_status_reg(d->hwirq);
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u8 status_idx = sunxi_irq_status_offset(d->hwirq);
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u32 val;
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/* Mask the IRQ */
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val = readl(pctl->membase + ctrl_reg);
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writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
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/* Clear the IRQ */
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writel(1 << status_idx, pctl->membase + status_reg);
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}
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static void sunxi_pinctrl_irq_mask(struct irq_data *d)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
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u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
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u32 val;
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/* Mask the IRQ */
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val = readl(pctl->membase + reg);
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writel(val & ~(1 << idx), pctl->membase + reg);
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}
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static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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struct sunxi_desc_function *func;
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u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
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u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
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u32 val;
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func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
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pctl->irq_array[d->hwirq],
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"irq");
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/* Change muxing to INT mode */
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sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
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/* Unmask the IRQ */
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val = readl(pctl->membase + reg);
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writel(val | (1 << idx), pctl->membase + reg);
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}
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static struct irq_chip sunxi_pinctrl_irq_chip = {
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.irq_mask = sunxi_pinctrl_irq_mask,
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.irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
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.irq_unmask = sunxi_pinctrl_irq_unmask,
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.irq_set_type = sunxi_pinctrl_irq_set_type,
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};
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static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
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const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
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/* Clear all interrupts */
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writel(reg, pctl->membase + IRQ_STATUS_REG);
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if (reg) {
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int irqoffset;
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for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
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int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
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generic_handle_irq(pin_irq);
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}
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}
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}
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static struct of_device_id sunxi_pinctrl_match[] = {
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{ .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
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{ .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
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@ -2005,6 +2135,31 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
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clk_prepare_enable(clk);
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pctl->irq = irq_of_parse_and_map(node, 0);
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if (!pctl->irq) {
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ret = -EINVAL;
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goto gpiochip_error;
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}
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pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
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&irq_domain_simple_ops, NULL);
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if (!pctl->domain) {
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dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
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ret = -ENOMEM;
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goto gpiochip_error;
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}
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for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
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int irqno = irq_create_mapping(pctl->domain, i);
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irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
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handle_simple_irq);
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irq_set_chip_data(irqno, pctl);
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};
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irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
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irq_set_handler_data(pctl->irq, pctl);
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dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
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return 0;
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@ -344,9 +344,31 @@
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#define PULL_PINS_BITS 2
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#define PULL_PINS_MASK 0x03
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#define SUNXI_IRQ_NUMBER 32
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#define IRQ_CFG_REG 0x200
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#define IRQ_CFG_IRQ_PER_REG 8
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#define IRQ_CFG_IRQ_BITS 4
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#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
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#define IRQ_CTRL_REG 0x210
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#define IRQ_CTRL_IRQ_PER_REG 32
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#define IRQ_CTRL_IRQ_BITS 1
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#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
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#define IRQ_STATUS_REG 0x214
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#define IRQ_STATUS_IRQ_PER_REG 32
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#define IRQ_STATUS_IRQ_BITS 1
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#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
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#define IRQ_EDGE_RISING 0x00
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#define IRQ_EDGE_FALLING 0x01
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#define IRQ_LEVEL_HIGH 0x02
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#define IRQ_LEVEL_LOW 0x03
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#define IRQ_EDGE_BOTH 0x04
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struct sunxi_desc_function {
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const char *name;
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u8 muxval;
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u8 irqnum;
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};
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struct sunxi_desc_pin {
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@ -378,10 +400,13 @@ struct sunxi_pinctrl {
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struct gpio_chip *chip;
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struct sunxi_pinctrl_desc *desc;
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struct device *dev;
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struct irq_domain *domain;
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struct sunxi_pinctrl_function *functions;
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unsigned nfunctions;
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struct sunxi_pinctrl_group *groups;
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unsigned ngroups;
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int irq;
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int irq_array[SUNXI_IRQ_NUMBER];
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struct pinctrl_dev *pctl_dev;
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};
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@ -398,6 +423,13 @@ struct sunxi_pinctrl {
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.muxval = _val, \
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}
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#define SUNXI_FUNCTION_IRQ(_val, _irq) \
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{ \
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.name = "irq", \
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.muxval = _val, \
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.irqnum = _irq, \
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}
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/*
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* The sunXi PIO registers are organized as is:
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* 0x00 - 0x0c Muxing values.
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@ -475,4 +507,40 @@ static inline u32 sunxi_pull_offset(u16 pin)
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return pin_num * PULL_PINS_BITS;
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}
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static inline u32 sunxi_irq_cfg_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
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return reg + IRQ_CFG_REG;
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}
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static inline u32 sunxi_irq_cfg_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
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return irq_num * IRQ_CFG_IRQ_BITS;
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}
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static inline u32 sunxi_irq_ctrl_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
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return reg + IRQ_CTRL_REG;
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}
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static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
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return irq_num * IRQ_CTRL_IRQ_BITS;
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}
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static inline u32 sunxi_irq_status_reg(u16 irq)
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{
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u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
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return reg + IRQ_STATUS_REG;
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}
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static inline u32 sunxi_irq_status_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
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return irq_num * IRQ_STATUS_IRQ_BITS;
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}
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#endif /* __PINCTRL_SUNXI_H */
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