drm/etnaviv: add further minor features and varyings count
Export further minor feature bitmasks and the varyings count from the GPU specifications registers to userspace. Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
This commit is contained in:
Russell King
Lucas Stach
Родитель
472f79dcf2
Коммит
602eb48966
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@ -72,6 +72,14 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
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*value = gpu->identity.minor_features3;
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break;
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case ETNAVIV_PARAM_GPU_FEATURES_5:
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*value = gpu->identity.minor_features4;
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break;
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case ETNAVIV_PARAM_GPU_FEATURES_6:
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*value = gpu->identity.minor_features5;
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break;
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case ETNAVIV_PARAM_GPU_STREAM_COUNT:
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*value = gpu->identity.stream_count;
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break;
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@ -112,6 +120,10 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
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*value = gpu->identity.num_constants;
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break;
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case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
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*value = gpu->identity.varyings_count;
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break;
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default:
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DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
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return -EINVAL;
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@ -131,10 +143,13 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
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{
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if (gpu->identity.minor_features0 &
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chipMinorFeatures0_MORE_MINOR_FEATURES) {
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u32 specs[2];
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u32 specs[4];
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unsigned int streams;
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specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
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specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
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specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
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specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
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gpu->identity.stream_count = etnaviv_field(specs[0],
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VIVS_HI_CHIP_SPECS_STREAM_COUNT);
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@ -158,6 +173,15 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
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VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
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gpu->identity.num_constants = etnaviv_field(specs[1],
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VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
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gpu->identity.varyings_count = etnaviv_field(specs[2],
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VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
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/* This overrides the value from older register if non-zero */
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streams = etnaviv_field(specs[3],
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VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
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if (streams)
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gpu->identity.stream_count = streams;
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}
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/* Fill in the stream count if not specified */
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@ -239,6 +263,30 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
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if (gpu->identity.num_constants == 0)
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gpu->identity.num_constants = 168;
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if (gpu->identity.varyings_count == 0) {
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if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
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gpu->identity.varyings_count = 12;
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else
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gpu->identity.varyings_count = 8;
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}
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/*
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* For some cores, two varyings are consumed for position, so the
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* maximum varying count needs to be reduced by one.
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*/
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if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
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etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
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etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
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etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
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etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
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etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
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etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
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etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
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etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
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etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
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etnaviv_is_model_rev(gpu, GC880, 0x5106))
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gpu->identity.varyings_count -= 1;
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}
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static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
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@ -305,6 +353,8 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
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gpu->identity.minor_features1 = 0;
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gpu->identity.minor_features2 = 0;
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gpu->identity.minor_features3 = 0;
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gpu->identity.minor_features4 = 0;
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gpu->identity.minor_features5 = 0;
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} else
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gpu->identity.minor_features0 =
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gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
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@ -317,6 +367,10 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
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gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
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gpu->identity.minor_features3 =
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gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
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gpu->identity.minor_features4 =
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gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
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gpu->identity.minor_features5 =
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gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
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}
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/* GC600 idle register reports zero bits where modules aren't present */
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@ -645,6 +699,10 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
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gpu->identity.minor_features2);
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seq_printf(m, "\t minor_features3: 0x%08x\n",
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gpu->identity.minor_features3);
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seq_printf(m, "\t minor_features4: 0x%08x\n",
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gpu->identity.minor_features4);
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seq_printf(m, "\t minor_features5: 0x%08x\n",
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gpu->identity.minor_features5);
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seq_puts(m, "\tspecs\n");
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seq_printf(m, "\t stream_count: %d\n",
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@ -667,6 +725,8 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
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gpu->identity.instruction_count);
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seq_printf(m, "\t num_constants: %d\n",
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gpu->identity.num_constants);
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seq_printf(m, "\t varyings_count: %d\n",
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gpu->identity.varyings_count);
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seq_printf(m, "\taxi: 0x%08x\n", axi);
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seq_printf(m, "\tidle: 0x%08x\n", idle);
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@ -46,6 +46,12 @@ struct etnaviv_chip_identity {
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/* Supported minor feature 3 fields. */
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u32 minor_features3;
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/* Supported minor feature 4 fields. */
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u32 minor_features4;
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/* Supported minor feature 5 fields. */
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u32 minor_features5;
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/* Number of streams supported. */
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u32 stream_count;
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@ -75,6 +81,9 @@ struct etnaviv_chip_identity {
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/* Buffer size */
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u32 buffer_size;
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/* Number of varyings */
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u8 varyings_count;
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};
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struct etnaviv_event {
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@ -48,6 +48,8 @@ struct drm_etnaviv_timespec {
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#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
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#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
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#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
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#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
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#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
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#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
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#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
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@ -59,6 +61,7 @@ struct drm_etnaviv_timespec {
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#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
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#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
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#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
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#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
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#define ETNA_MAX_PIPES 4
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