e1000e: 82579 do not gate auto config of PHY by hardware during nominal use
For non-managed versions of 82579, set the bit that prevents the hardware from automatically configuring the PHY after resets only when the driver performs a reset, clear the bit after resets. This is so the hardware can configure the PHY automatically when the part is reset in a manner that is not controlled by the driver (e.g. in a virtual environment via PCI FLR) otherwise the PHY will be mis-configured causing issues such as failing to link at 1000Mbps. For managed versions of 82579, keep the previous behavior since the manageability firmware will handle the PHY configuration. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -243,6 +243,7 @@ static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
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static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
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static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
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static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
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{
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@ -278,7 +279,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
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static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 ctrl;
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u32 ctrl, fwsm;
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s32 ret_val = 0;
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phy->addr = 1;
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@ -300,7 +301,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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* disabled, then toggle the LANPHYPC Value bit to force
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* the interconnect to PCIe mode.
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*/
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if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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fwsm = er32(FWSM);
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if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
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ctrl = er32(CTRL);
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ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
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ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
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@ -309,6 +311,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
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ew32(CTRL, ctrl);
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msleep(50);
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/*
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* Gate automatic PHY configuration by hardware on
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* non-managed 82579
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*/
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if (hw->mac.type == e1000_pch2lan)
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e1000_gate_hw_phy_config_ich8lan(hw, true);
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}
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/*
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@ -321,6 +330,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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if (ret_val)
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goto out;
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/* Ungate automatic PHY configuration on non-managed 82579 */
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if ((hw->mac.type == e1000_pch2lan) &&
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!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
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msleep(10);
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e1000_gate_hw_phy_config_ich8lan(hw, false);
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}
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phy->id = e1000_phy_unknown;
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ret_val = e1000e_get_phy_id(hw);
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if (ret_val)
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@ -567,13 +583,10 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
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if (mac->type == e1000_ich8lan)
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e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
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/* Disable PHY configuration by hardware, config by software */
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if (mac->type == e1000_pch2lan) {
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u32 extcnf_ctrl = er32(EXTCNF_CTRL);
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extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
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ew32(EXTCNF_CTRL, extcnf_ctrl);
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}
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/* Gate automatic PHY configuration by hardware on managed 82579 */
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if ((mac->type == e1000_pch2lan) &&
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(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
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e1000_gate_hw_phy_config_ich8lan(hw, true);
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return 0;
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}
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@ -1620,6 +1633,32 @@ out:
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return ret_val;
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}
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/**
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* e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
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* @hw: pointer to the HW structure
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* @gate: boolean set to true to gate, false to ungate
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*
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* Gate/ungate the automatic PHY configuration via hardware; perform
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* the configuration via software instead.
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**/
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static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
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{
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u32 extcnf_ctrl;
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if (hw->mac.type != e1000_pch2lan)
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return;
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extcnf_ctrl = er32(EXTCNF_CTRL);
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if (gate)
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extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
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else
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extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
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ew32(EXTCNF_CTRL, extcnf_ctrl);
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return;
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}
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/**
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* e1000_lan_init_done_ich8lan - Check for PHY config completion
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* @hw: pointer to the HW structure
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@ -1695,6 +1734,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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/* Configure the LCD with the OEM bits in NVM */
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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/* Ungate automatic PHY configuration on non-managed 82579 */
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if ((hw->mac.type == e1000_pch2lan) &&
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!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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msleep(10);
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e1000_gate_hw_phy_config_ich8lan(hw, false);
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}
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out:
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return ret_val;
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}
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@ -1711,6 +1757,11 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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/* Gate automatic PHY configuration by hardware on non-managed 82579 */
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if ((hw->mac.type == e1000_pch2lan) &&
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!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
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e1000_gate_hw_phy_config_ich8lan(hw, true);
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ret_val = e1000e_phy_hw_reset_generic(hw);
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if (ret_val)
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goto out;
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@ -2975,6 +3026,14 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
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* external PHY is reset.
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*/
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ctrl |= E1000_CTRL_PHY_RST;
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/*
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* Gate automatic PHY configuration by hardware on
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* non-managed 82579
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*/
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if ((hw->mac.type == e1000_pch2lan) &&
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!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
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e1000_gate_hw_phy_config_ich8lan(hw, true);
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}
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ret_val = e1000_acquire_swflag_ich8lan(hw);
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e_dbg("Issuing a global reset to ich8lan\n");
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