drm/radeon/kms: add some missing regs to evergreen gpu init
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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09d7e785f7
Коммит
60a4a3e0ce
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@ -1260,6 +1260,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(VGT_GS_VERTEX_REUSE, 16);
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WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
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WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
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WREG32(VGT_OUT_DEALLOC_CNTL, 16);
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WREG32(CB_PERF_CTR0_SEL_0, 0);
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WREG32(CB_PERF_CTR0_SEL_1, 0);
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WREG32(CB_PERF_CTR1_SEL_0, 0);
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@ -1269,6 +1272,26 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(CB_PERF_CTR3_SEL_0, 0);
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WREG32(CB_PERF_CTR3_SEL_1, 0);
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/* clear render buffer base addresses */
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WREG32(CB_COLOR0_BASE, 0);
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WREG32(CB_COLOR1_BASE, 0);
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WREG32(CB_COLOR2_BASE, 0);
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WREG32(CB_COLOR3_BASE, 0);
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WREG32(CB_COLOR4_BASE, 0);
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WREG32(CB_COLOR5_BASE, 0);
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WREG32(CB_COLOR6_BASE, 0);
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WREG32(CB_COLOR7_BASE, 0);
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WREG32(CB_COLOR8_BASE, 0);
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WREG32(CB_COLOR9_BASE, 0);
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WREG32(CB_COLOR10_BASE, 0);
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WREG32(CB_COLOR11_BASE, 0);
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/* set the shader const cache sizes to 0 */
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for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
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WREG32(i, 0);
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for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
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WREG32(i, 0);
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hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
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WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
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@ -713,6 +713,9 @@
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#define SQ_GSVS_RING_OFFSET_2 0x28930
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#define SQ_GSVS_RING_OFFSET_3 0x28934
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#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
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#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
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#define SQ_ALU_CONST_CACHE_PS_0 0x28940
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#define SQ_ALU_CONST_CACHE_PS_1 0x28944
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#define SQ_ALU_CONST_CACHE_PS_2 0x28948
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