[media] add stih-cec driver
This patch implement CEC driver for stih4xx platform. Driver compliance has been test with cec-ctl and cec-compliance tools. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Benjamin Gaignard
Mauro Carvalho Chehab
Родитель
c1a2f9898a
Коммит
60fe2bda39
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@ -36,4 +36,6 @@ source "drivers/staging/media/s5p-cec/Kconfig"
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# Keep LIRC at the end, as it has sub-menus
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source "drivers/staging/media/lirc/Kconfig"
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source "drivers/staging/media/st-cec/Kconfig"
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endif
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@ -6,3 +6,4 @@ obj-$(CONFIG_LIRC_STAGING) += lirc/
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obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
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obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
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obj-$(CONFIG_USB_PULSE8_CEC) += pulse8-cec/
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obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += st-cec/
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@ -0,0 +1,8 @@
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config VIDEO_STI_HDMI_CEC
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tristate "STMicroelectronics STiH4xx HDMI CEC driver"
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depends on VIDEO_DEV && MEDIA_CEC && (ARCH_STI || COMPILE_TEST)
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---help---
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This is a driver for STIH4xx HDMI CEC interface. It uses the
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generic CEC framework interface.
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CEC bus is present in the HDMI connector and enables communication
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between compatible devices.
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@ -0,0 +1 @@
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obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += stih-cec.o
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@ -0,0 +1,380 @@
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/*
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* drivers/staging/media/st-cec/stih-cec.c
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*
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* STIH4xx CEC driver
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* Copyright (C) STMicroelectronic SA 2016
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/version.h>
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#include <media/cec.h>
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#define CEC_NAME "stih-cec"
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/* CEC registers */
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#define CEC_CLK_DIV 0x0
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#define CEC_CTRL 0x4
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#define CEC_IRQ_CTRL 0x8
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#define CEC_STATUS 0xC
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#define CEC_EXT_STATUS 0x10
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#define CEC_TX_CTRL 0x14
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#define CEC_FREE_TIME_THRESH 0x18
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#define CEC_BIT_TOUT_THRESH 0x1C
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#define CEC_BIT_PULSE_THRESH 0x20
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#define CEC_DATA 0x24
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#define CEC_TX_ARRAY_CTRL 0x28
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#define CEC_CTRL2 0x2C
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#define CEC_TX_ERROR_STS 0x30
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#define CEC_ADDR_TABLE 0x34
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#define CEC_DATA_ARRAY_CTRL 0x38
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#define CEC_DATA_ARRAY_STATUS 0x3C
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#define CEC_TX_DATA_BASE 0x40
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#define CEC_TX_DATA_TOP 0x50
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#define CEC_TX_DATA_SIZE 0x1
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#define CEC_RX_DATA_BASE 0x54
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#define CEC_RX_DATA_TOP 0x64
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#define CEC_RX_DATA_SIZE 0x1
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/* CEC_CTRL2 */
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#define CEC_LINE_INACTIVE_EN BIT(0)
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#define CEC_AUTO_BUS_ERR_EN BIT(1)
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#define CEC_STOP_ON_ARB_ERR_EN BIT(2)
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#define CEC_TX_REQ_WAIT_EN BIT(3)
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/* CEC_DATA_ARRAY_CTRL */
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#define CEC_TX_ARRAY_EN BIT(0)
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#define CEC_RX_ARRAY_EN BIT(1)
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#define CEC_TX_ARRAY_RESET BIT(2)
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#define CEC_RX_ARRAY_RESET BIT(3)
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#define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4)
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#define CEC_TX_STOP_ON_NACK BIT(7)
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/* CEC_TX_ARRAY_CTRL */
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#define CEC_TX_N_OF_BYTES 0x1F
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#define CEC_TX_START BIT(5)
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#define CEC_TX_AUTO_SOM_EN BIT(6)
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#define CEC_TX_AUTO_EOM_EN BIT(7)
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/* CEC_IRQ_CTRL */
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#define CEC_TX_DONE_IRQ_EN BIT(0)
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#define CEC_ERROR_IRQ_EN BIT(2)
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#define CEC_RX_DONE_IRQ_EN BIT(3)
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#define CEC_RX_SOM_IRQ_EN BIT(4)
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#define CEC_RX_EOM_IRQ_EN BIT(5)
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#define CEC_FREE_TIME_IRQ_EN BIT(6)
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#define CEC_PIN_STS_IRQ_EN BIT(7)
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/* CEC_CTRL */
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#define CEC_IN_FILTER_EN BIT(0)
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#define CEC_PWR_SAVE_EN BIT(1)
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#define CEC_EN BIT(4)
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#define CEC_ACK_CTRL BIT(5)
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#define CEC_RX_RESET_EN BIT(6)
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#define CEC_IGNORE_RX_ERROR BIT(7)
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/* CEC_STATUS */
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#define CEC_TX_DONE_STS BIT(0)
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#define CEC_TX_ACK_GET_STS BIT(1)
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#define CEC_ERROR_STS BIT(2)
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#define CEC_RX_DONE_STS BIT(3)
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#define CEC_RX_SOM_STS BIT(4)
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#define CEC_RX_EOM_STS BIT(5)
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#define CEC_FREE_TIME_IRQ_STS BIT(6)
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#define CEC_PIN_STS BIT(7)
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#define CEC_SBIT_TOUT_STS BIT(8)
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#define CEC_DBIT_TOUT_STS BIT(9)
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#define CEC_LPULSE_ERROR_STS BIT(10)
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#define CEC_HPULSE_ERROR_STS BIT(11)
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#define CEC_TX_ERROR BIT(12)
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#define CEC_TX_ARB_ERROR BIT(13)
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#define CEC_RX_ERROR_MIN BIT(14)
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#define CEC_RX_ERROR_MAX BIT(15)
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/* Signal free time in bit periods (2.4ms) */
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#define CEC_PRESENT_INIT_SFT 7
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#define CEC_NEW_INIT_SFT 5
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#define CEC_RETRANSMIT_SFT 3
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/* Constants for CEC_BIT_TOUT_THRESH register */
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#define CEC_SBIT_TOUT_47MS BIT(1)
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#define CEC_SBIT_TOUT_48MS BIT(0) | BIT(1)
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#define CEC_SBIT_TOUT_50MS BIT(2)
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#define CEC_DBIT_TOUT_27MS BIT(0)
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#define CEC_DBIT_TOUT_28MS BIT(1)
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#define CEC_DBIT_TOUT_29MS BIT(0) | BIT(1)
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/* Constants for CEC_BIT_PULSE_THRESH register */
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#define CEC_BIT_LPULSE_03MS BIT(1)
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#define CEC_BIT_HPULSE_03MS BIT(3)
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/* Constants for CEC_DATA_ARRAY_STATUS register */
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#define CEC_RX_N_OF_BYTES 0x1F
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#define CEC_TX_N_OF_BYTES_SENT BIT(5)
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#define CEC_RX_OVERRUN BIT(6)
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struct stih_cec {
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struct cec_adapter *adap;
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struct device *dev;
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struct clk *clk;
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void __iomem *regs;
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int irq;
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u32 irq_status;
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};
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static int stih_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct stih_cec *cec = adap->priv;
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if (enable) {
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/* The doc says (input TCLK_PERIOD * CEC_CLK_DIV) = 0.1ms */
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unsigned long clk_freq = clk_get_rate(cec->clk);
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u32 cec_clk_div = clk_freq / 10000;
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writel(cec_clk_div, cec->regs + CEC_CLK_DIV);
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/* Configuration of the durations activating a timeout */
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writel(CEC_SBIT_TOUT_47MS | (CEC_DBIT_TOUT_28MS << 4),
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cec->regs + CEC_BIT_TOUT_THRESH);
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/* Configuration of the smallest allowed duration for pulses */
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writel(CEC_BIT_LPULSE_03MS | CEC_BIT_HPULSE_03MS,
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cec->regs + CEC_BIT_PULSE_THRESH);
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/* Minimum received bit period threshold */
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writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL);
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/* Configuration of transceiver data arrays */
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writel(CEC_TX_ARRAY_EN | CEC_RX_ARRAY_EN | CEC_TX_STOP_ON_NACK,
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cec->regs + CEC_DATA_ARRAY_CTRL);
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/* Configuration of the control bits for CEC Transceiver */
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writel(CEC_IN_FILTER_EN | CEC_EN | CEC_RX_RESET_EN,
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cec->regs + CEC_CTRL);
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/* Clear logical addresses */
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writel(0, cec->regs + CEC_ADDR_TABLE);
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/* Clear the status register */
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writel(0x0, cec->regs + CEC_STATUS);
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/* Enable the interrupts */
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writel(CEC_TX_DONE_IRQ_EN | CEC_RX_DONE_IRQ_EN |
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CEC_RX_SOM_IRQ_EN | CEC_RX_EOM_IRQ_EN |
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CEC_ERROR_IRQ_EN,
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cec->regs + CEC_IRQ_CTRL);
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} else {
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/* Clear logical addresses */
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writel(0, cec->regs + CEC_ADDR_TABLE);
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/* Clear the status register */
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writel(0x0, cec->regs + CEC_STATUS);
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/* Disable the interrupts */
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writel(0, cec->regs + CEC_IRQ_CTRL);
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}
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return 0;
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}
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static int stih_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
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{
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struct stih_cec *cec = adap->priv;
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u32 reg = readl(cec->regs + CEC_ADDR_TABLE);
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reg |= 1 << logical_addr;
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if (logical_addr == CEC_LOG_ADDR_INVALID)
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reg = 0;
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writel(reg, cec->regs + CEC_ADDR_TABLE);
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return 0;
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}
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static int stih_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time, struct cec_msg *msg)
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{
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struct stih_cec *cec = adap->priv;
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int i;
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/* Copy message into registers */
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for (i = 0; i < msg->len; i++)
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writeb(msg->msg[i], cec->regs + CEC_TX_DATA_BASE + i);
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/* Start transmission, configure hardware to add start and stop bits
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* Signal free time is handled by the hardware
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*/
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writel(CEC_TX_AUTO_SOM_EN | CEC_TX_AUTO_EOM_EN | CEC_TX_START |
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msg->len, cec->regs + CEC_TX_ARRAY_CTRL);
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return 0;
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}
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static void stih_tx_done(struct stih_cec *cec, u32 status)
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{
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if (status & CEC_TX_ERROR) {
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cec_transmit_done(cec->adap, CEC_TX_STATUS_ERROR, 0, 0, 0, 1);
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return;
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}
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if (status & CEC_TX_ARB_ERROR) {
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cec_transmit_done(cec->adap,
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CEC_TX_STATUS_ARB_LOST, 1, 0, 0, 0);
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return;
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}
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if (!(status & CEC_TX_ACK_GET_STS)) {
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cec_transmit_done(cec->adap, CEC_TX_STATUS_NACK, 0, 1, 0, 0);
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return;
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}
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cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
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}
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static void stih_rx_done(struct stih_cec *cec, u32 status)
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{
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struct cec_msg msg = {};
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u8 i;
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if (status & CEC_RX_ERROR_MIN)
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return;
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if (status & CEC_RX_ERROR_MAX)
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return;
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msg.len = readl(cec->regs + CEC_DATA_ARRAY_STATUS) & 0x1f;
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if (!msg.len)
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return;
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if (msg.len > 16)
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msg.len = 16;
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for (i = 0; i < msg.len; i++)
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msg.msg[i] = readl(cec->regs + CEC_RX_DATA_BASE + i);
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cec_received_msg(cec->adap, &msg);
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}
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static irqreturn_t stih_cec_irq_handler_thread(int irq, void *priv)
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{
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struct stih_cec *cec = priv;
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if (cec->irq_status & CEC_TX_DONE_STS)
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stih_tx_done(cec, cec->irq_status);
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if (cec->irq_status & CEC_RX_DONE_STS)
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stih_rx_done(cec, cec->irq_status);
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cec->irq_status = 0;
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return IRQ_HANDLED;
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}
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static irqreturn_t stih_cec_irq_handler(int irq, void *priv)
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{
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struct stih_cec *cec = priv;
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cec->irq_status = readl(cec->regs + CEC_STATUS);
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writel(cec->irq_status, cec->regs + CEC_STATUS);
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return IRQ_WAKE_THREAD;
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}
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static const struct cec_adap_ops sti_cec_adap_ops = {
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.adap_enable = stih_cec_adap_enable,
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.adap_log_addr = stih_cec_adap_log_addr,
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.adap_transmit = stih_cec_adap_transmit,
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};
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static int stih_cec_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct stih_cec *cec;
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int ret;
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cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
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if (!cec)
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return -ENOMEM;
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cec->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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cec->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(cec->regs))
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return PTR_ERR(cec->regs);
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cec->irq = platform_get_irq(pdev, 0);
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if (cec->irq < 0)
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return cec->irq;
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ret = devm_request_threaded_irq(dev, cec->irq, stih_cec_irq_handler,
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stih_cec_irq_handler_thread, 0,
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pdev->name, cec);
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if (ret)
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return ret;
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cec->clk = devm_clk_get(dev, "cec-clk");
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if (IS_ERR(cec->clk)) {
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dev_err(dev, "Cannot get cec clock\n");
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return PTR_ERR(cec->clk);
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}
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cec->adap = cec_allocate_adapter(&sti_cec_adap_ops, cec,
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CEC_NAME,
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CEC_CAP_LOG_ADDRS | CEC_CAP_PASSTHROUGH |
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CEC_CAP_PHYS_ADDR | CEC_CAP_TRANSMIT,
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1, &pdev->dev);
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ret = PTR_ERR_OR_ZERO(cec->adap);
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if (ret)
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return ret;
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ret = cec_register_adapter(cec->adap);
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if (ret) {
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cec_delete_adapter(cec->adap);
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return ret;
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}
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platform_set_drvdata(pdev, cec);
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return 0;
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}
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static int stih_cec_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id stih_cec_match[] = {
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{
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.compatible = "st,stih-cec",
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},
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{},
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};
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static struct platform_driver stih_cec_pdrv = {
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.probe = stih_cec_probe,
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.remove = stih_cec_remove,
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.driver = {
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.name = CEC_NAME,
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.of_match_table = stih_cec_match,
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},
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};
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module_platform_driver(stih_cec_pdrv);
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@linaro.org>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("STIH4xx CEC driver");
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