Merge branch irq/misc-5.19 into irq/irqchip-next
* irq/misc-5.19: : . : Misc fixes and minor improvements: : : - GIC: Improve warning when the firmware tables are inconsistent : : - csky: Use true/false as boolean litterals : : - imx-irqsteer: Add runtime PM support : : - armada-370-xp: Enable CPU affinity for MSIs, avoid messing with : PMU interrupts on some variants : : - aspeed: Fix handling of irq_of_parse_and_map() errors : : - sun6i: Fix sparse warnings : : - xtensa-mx: Fix initial IRQ affinity in non-SMP setup : : - exiu: Fix acknowledgment of edge-triggered interrupts : : - sunxi: Generalise configuration for further reuse : . irqchip: Add Kconfig symbols for sunxi drivers irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x irqchip/gic: Improved warning about incorrect type irqchip/csky: Return true/false (not 1/0) from bool functions irqchip/imx-irqsteer: Add runtime PM support irqchip/imx-irqsteer: Constify irq_chip struct irqchip/armada-370-xp: Enable MSI affinity configuration irqchip/aspeed-scu-ic: Fix irq_of_parse_and_map() return value irqchip/aspeed-i2c-ic: Fix irq_of_parse_and_map() return value irqchip/sun6i-r: Use NULL for chip_data irqchip/xtensa-mx: Fix initial IRQ affinity in non-SMP setup irqchip/exiu: Fix acknowledgment of edge triggered interrupts Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
Коммит
61299e1838
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@ -4,10 +4,7 @@ menuconfig ARCH_SUNXI
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depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select PM_OPP
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select SUN4I_TIMER
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@ -22,10 +19,12 @@ if ARCH_MULTI_V7
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config MACH_SUN4I
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bool "Allwinner A10 (sun4i) SoCs support"
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default ARCH_SUNXI
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select SUN4I_INTC
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config MACH_SUN5I
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bool "Allwinner A10s / A13 (sun5i) SoCs support"
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default ARCH_SUNXI
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select SUN4I_INTC
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select SUN5I_HSTIMER
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config MACH_SUN6I
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@ -34,6 +33,8 @@ config MACH_SUN6I
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select ARM_GIC
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select MFD_SUN6I_PRCM
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select SUN5I_HSTIMER
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select SUN6I_R_INTC
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select SUNXI_NMI_INTC
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config MACH_SUN7I
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bool "Allwinner A20 (sun7i) SoCs support"
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@ -43,17 +44,21 @@ config MACH_SUN7I
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select ARCH_SUPPORTS_BIG_ENDIAN
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select HAVE_ARM_ARCH_TIMER
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select SUN5I_HSTIMER
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select SUNXI_NMI_INTC
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config MACH_SUN8I
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bool "Allwinner sun8i Family SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select MFD_SUN6I_PRCM
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select SUN6I_R_INTC
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select SUNXI_NMI_INTC
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config MACH_SUN9I
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bool "Allwinner (sun9i) SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select SUNXI_NMI_INTC
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config ARCH_SUNXI_MC_SMP
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bool
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@ -69,6 +74,7 @@ if ARCH_MULTI_V5
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config MACH_SUNIV
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bool "Allwinner ARMv5 F-series (suniv) SoCs support"
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default ARCH_SUNXI
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select SUN4I_INTC
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help
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Support for Allwinner suniv ARMv5 SoCs.
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(F1C100A, F1C100s, F1C200s, F1C500, F1C600)
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@ -11,12 +11,11 @@ config ARCH_ACTIONS
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select RESET_CONTROLLER
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select SUN4I_TIMER
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select SUN6I_R_INTC
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select SUNXI_NMI_INTC
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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@ -253,6 +252,7 @@ config ARCH_INTEL_SOCFPGA
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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@ -257,6 +257,18 @@ config ST_IRQCHIP
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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config SUN4I_INTC
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bool
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config SUN6I_R_INTC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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config SUNXI_NMI_INTC
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bool
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select GENERIC_IRQ_CHIP
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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|
|
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@ -23,9 +23,9 @@ obj-$(CONFIG_OMPIC) += irq-ompic.o
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obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
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obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_SUN4I_INTC) += irq-sun4i.o
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obj-$(CONFIG_SUN6I_R_INTC) += irq-sun6i-r.o
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obj-$(CONFIG_SUNXI_NMI_INTC) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
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|
|
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|
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@ -209,15 +209,29 @@ static struct msi_domain_info armada_370_xp_msi_domain_info = {
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static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));
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msg->address_lo = lower_32_bits(msi_doorbell_addr);
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msg->address_hi = upper_32_bits(msi_doorbell_addr);
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msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
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msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START);
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}
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static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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unsigned int cpu;
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if (!force)
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cpu = cpumask_any_and(mask, cpu_online_mask);
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else
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cpu = cpumask_first(mask);
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if (cpu >= nr_cpu_ids)
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return -EINVAL;
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irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
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@ -264,11 +278,21 @@ static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
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.free = armada_370_xp_msi_free,
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};
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static int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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static void armada_370_xp_msi_reenable_percpu(void)
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{
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u32 reg;
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/* Enable MSI doorbell mask and combined cpu local interrupt */
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
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| PCI_MSI_DOORBELL_MASK;
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writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask local doorbell interrupt */
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writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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msi_doorbell_addr = main_int_phys_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS;
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@ -287,18 +311,13 @@ static int armada_370_xp_msi_init(struct device_node *node,
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return -ENOMEM;
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}
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
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| PCI_MSI_DOORBELL_MASK;
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writel(reg, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask IPI interrupt */
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writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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armada_370_xp_msi_reenable_percpu();
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return 0;
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}
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#else
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static void armada_370_xp_msi_reenable_percpu(void) {}
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static inline int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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@ -308,7 +327,16 @@ static inline int armada_370_xp_msi_init(struct device_node *node,
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static void armada_xp_mpic_perf_init(void)
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{
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unsigned long cpuid = cpu_logical_map(smp_processor_id());
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unsigned long cpuid;
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/*
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* This Performance Counter Overflow interrupt is specific for
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* Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
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*/
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if (!of_machine_is_compatible("marvell,armada-370-xp"))
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return;
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cpuid = cpu_logical_map(smp_processor_id());
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/* Enable Performance Counter Overflow interrupts */
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writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
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@ -501,6 +529,8 @@ static void armada_xp_mpic_reenable_percpu(void)
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}
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ipi_resume();
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armada_370_xp_msi_reenable_percpu();
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}
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static int armada_xp_mpic_starting_cpu(unsigned int cpu)
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|
|
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@ -77,8 +77,8 @@ static int __init aspeed_i2c_ic_of_init(struct device_node *node,
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}
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i2c_ic->parent_irq = irq_of_parse_and_map(node, 0);
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if (i2c_ic->parent_irq < 0) {
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ret = i2c_ic->parent_irq;
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if (!i2c_ic->parent_irq) {
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ret = -EINVAL;
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goto err_iounmap;
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}
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|
|
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|
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@ -157,8 +157,8 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq < 0) {
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rc = irq;
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if (!irq) {
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rc = -EINVAL;
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goto err;
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}
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|
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|
|
|
|||
|
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@ -136,11 +136,11 @@ static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq,
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u32 irq_base)
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{
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if (hwirq == 0)
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return 0;
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return false;
|
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|
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generic_handle_domain_irq(root_domain, irq_base + __fls(hwirq));
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return 1;
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return true;
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}
|
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|
||||
/* gx6605s 64 irqs interrupt controller */
|
||||
|
|
|
|||
|
|
@ -1115,7 +1115,8 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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|||
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
|
||||
|
||||
/* Make it clear that broken DTs are... broken */
|
||||
WARN_ON(*type == IRQ_TYPE_NONE);
|
||||
WARN(*type == IRQ_TYPE_NONE,
|
||||
"HW irq %ld has invalid type\n", *hwirq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1132,7 +1133,8 @@ static int gic_irq_domain_translate(struct irq_domain *d,
|
|||
*hwirq = fwspec->param[0];
|
||||
*type = fwspec->param[1];
|
||||
|
||||
WARN_ON(*type == IRQ_TYPE_NONE);
|
||||
WARN(*type == IRQ_TYPE_NONE,
|
||||
"HW irq %ld has invalid type\n", *hwirq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
|
||||
|
|
@ -70,7 +71,7 @@ static void imx_irqsteer_irq_mask(struct irq_data *d)
|
|||
raw_spin_unlock_irqrestore(&data->lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip imx_irqsteer_irq_chip = {
|
||||
static const struct irq_chip imx_irqsteer_irq_chip = {
|
||||
.name = "irqsteer",
|
||||
.irq_mask = imx_irqsteer_irq_mask,
|
||||
.irq_unmask = imx_irqsteer_irq_unmask,
|
||||
|
|
@ -175,7 +176,7 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
data->irq_count = DIV_ROUND_UP(irqs_num, 64);
|
||||
data->reg_num = irqs_num / 32;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP)) {
|
||||
if (IS_ENABLED(CONFIG_PM)) {
|
||||
data->saved_reg = devm_kzalloc(&pdev->dev,
|
||||
sizeof(u32) * data->reg_num,
|
||||
GFP_KERNEL);
|
||||
|
|
@ -199,6 +200,7 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
irq_domain_set_pm_device(data->domain, &pdev->dev);
|
||||
|
||||
if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
|
||||
ret = -EINVAL;
|
||||
|
|
@ -219,6 +221,9 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
clk_disable_unprepare(data->ipg_clk);
|
||||
|
|
@ -241,7 +246,7 @@ static int imx_irqsteer_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
#ifdef CONFIG_PM
|
||||
static void imx_irqsteer_save_regs(struct irqsteer_data *data)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -288,7 +293,10 @@ static int imx_irqsteer_resume(struct device *dev)
|
|||
#endif
|
||||
|
||||
static const struct dev_pm_ops imx_irqsteer_pm_ops = {
|
||||
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
|
||||
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
SET_RUNTIME_PM_OPS(imx_irqsteer_suspend,
|
||||
imx_irqsteer_resume, NULL)
|
||||
};
|
||||
|
||||
static const struct of_device_id imx_irqsteer_dt_ids[] = {
|
||||
|
|
|
|||
|
|
@ -37,11 +37,26 @@ struct exiu_irq_data {
|
|||
u32 spi_base;
|
||||
};
|
||||
|
||||
static void exiu_irq_eoi(struct irq_data *d)
|
||||
static void exiu_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
|
||||
|
||||
writel(BIT(d->hwirq), data->base + EIREQCLR);
|
||||
}
|
||||
|
||||
static void exiu_irq_eoi(struct irq_data *d)
|
||||
{
|
||||
struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
|
||||
|
||||
/*
|
||||
* Level triggered interrupts are latched and must be cleared during
|
||||
* EOI or the interrupt will be jammed on. Of course if a level
|
||||
* triggered interrupt is still asserted then the write will not clear
|
||||
* the interrupt.
|
||||
*/
|
||||
if (irqd_is_level_type(d))
|
||||
writel(BIT(d->hwirq), data->base + EIREQCLR);
|
||||
|
||||
irq_chip_eoi_parent(d);
|
||||
}
|
||||
|
||||
|
|
@ -91,10 +106,13 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
writel_relaxed(val, data->base + EILVL);
|
||||
|
||||
val = readl_relaxed(data->base + EIEDG);
|
||||
if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
|
||||
if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) {
|
||||
val &= ~BIT(d->hwirq);
|
||||
else
|
||||
irq_set_handler_locked(d, handle_fasteoi_irq);
|
||||
} else {
|
||||
val |= BIT(d->hwirq);
|
||||
irq_set_handler_locked(d, handle_fasteoi_ack_irq);
|
||||
}
|
||||
writel_relaxed(val, data->base + EIEDG);
|
||||
|
||||
writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
|
||||
|
|
@ -104,6 +122,7 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
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||||
static struct irq_chip exiu_irq_chip = {
|
||||
.name = "EXIU",
|
||||
.irq_ack = exiu_irq_ack,
|
||||
.irq_eoi = exiu_irq_eoi,
|
||||
.irq_enable = exiu_irq_enable,
|
||||
.irq_mask = exiu_irq_mask,
|
||||
|
|
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|||
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@ -249,11 +249,13 @@ static int sun6i_r_intc_domain_alloc(struct irq_domain *domain,
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for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) {
|
||||
if (hwirq == nmi_hwirq) {
|
||||
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
|
||||
&sun6i_r_intc_nmi_chip, 0);
|
||||
&sun6i_r_intc_nmi_chip,
|
||||
NULL);
|
||||
irq_set_handler(virq, handle_fasteoi_ack_irq);
|
||||
} else {
|
||||
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
|
||||
&sun6i_r_intc_wakeup_chip, 0);
|
||||
&sun6i_r_intc_wakeup_chip,
|
||||
NULL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -151,14 +151,25 @@ static struct irq_chip xtensa_mx_irq_chip = {
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|||
.irq_set_affinity = xtensa_mx_irq_set_affinity,
|
||||
};
|
||||
|
||||
static void __init xtensa_mx_init_common(struct irq_domain *root_domain)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
irq_set_default_host(root_domain);
|
||||
secondary_init_irq();
|
||||
|
||||
/* Initialize default IRQ routing to CPU 0 */
|
||||
for (i = 0; i < XCHAL_NUM_EXTINTERRUPTS; ++i)
|
||||
set_er(1, MIROUT(i));
|
||||
}
|
||||
|
||||
int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
|
||||
{
|
||||
struct irq_domain *root_domain =
|
||||
irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
|
||||
&xtensa_mx_irq_domain_ops,
|
||||
&xtensa_mx_irq_chip);
|
||||
irq_set_default_host(root_domain);
|
||||
secondary_init_irq();
|
||||
xtensa_mx_init_common(root_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -168,8 +179,7 @@ static int __init xtensa_mx_init(struct device_node *np,
|
|||
struct irq_domain *root_domain =
|
||||
irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
|
||||
&xtensa_mx_irq_chip);
|
||||
irq_set_default_host(root_domain);
|
||||
secondary_init_irq();
|
||||
xtensa_mx_init_common(root_domain);
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);
|
||||
|
|
|
|||
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