powerpc/crypto: AES-XCBC mode routines for nx encryption
These routines add support for AES in XCBC mode on the Power7+ CPU's in-Nest accelerator driver. Signed-off-by: Kent Yoder <key@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Kent Yoder
Benjamin Herrenschmidt
Родитель
f2a15f1d5d
Коммит
6148c1ad6d
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/**
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* AES XCBC routines supporting the Power 7+ Nest Accelerators driver
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*
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* Copyright (C) 2011-2012 International Business Machines Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 only.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Author: Kent Yoder <yoder1@us.ibm.com>
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*/
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#include <crypto/internal/hash.h>
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/crypto.h>
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#include <asm/vio.h>
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#include "nx_csbcpb.h"
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#include "nx.h"
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struct xcbc_state {
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u8 state[AES_BLOCK_SIZE];
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unsigned int count;
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u8 buffer[AES_BLOCK_SIZE];
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};
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static int nx_xcbc_set_key(struct crypto_shash *desc,
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const u8 *in_key,
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unsigned int key_len)
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{
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struct nx_crypto_ctx *nx_ctx = crypto_shash_ctx(desc);
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switch (key_len) {
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case AES_KEYSIZE_128:
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nx_ctx->ap = &nx_ctx->props[NX_PROPS_AES_128];
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break;
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default:
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return -EINVAL;
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}
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memcpy(nx_ctx->priv.xcbc.key, in_key, key_len);
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return 0;
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}
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static int nx_xcbc_init(struct shash_desc *desc)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *out_sg;
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nx_ctx_init(nx_ctx, HCOP_FC_AES);
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memset(sctx, 0, sizeof *sctx);
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NX_CPB_SET_KEY_SIZE(csbcpb, NX_KS_AES_128);
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csbcpb->cpb.hdr.mode = NX_MODE_AES_XCBC_MAC;
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memcpy(csbcpb->cpb.aes_xcbc.key, nx_ctx->priv.xcbc.key, AES_BLOCK_SIZE);
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memset(nx_ctx->priv.xcbc.key, 0, sizeof *nx_ctx->priv.xcbc.key);
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out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
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AES_BLOCK_SIZE, nx_ctx->ap->sglen);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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return 0;
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}
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static int nx_xcbc_update(struct shash_desc *desc,
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const u8 *data,
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unsigned int len)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *in_sg;
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u32 to_process, leftover;
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int rc = 0;
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if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
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/* we've hit the nx chip previously and we're updating again,
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* so copy over the partial digest */
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memcpy(csbcpb->cpb.aes_xcbc.cv,
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csbcpb->cpb.aes_xcbc.out_cv_mac, AES_BLOCK_SIZE);
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}
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/* 2 cases for total data len:
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* 1: <= AES_BLOCK_SIZE: copy into state, return 0
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* 2: > AES_BLOCK_SIZE: process X blocks, copy in leftover
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*/
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if (len + sctx->count <= AES_BLOCK_SIZE) {
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memcpy(sctx->buffer + sctx->count, data, len);
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sctx->count += len;
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goto out;
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}
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/* to_process: the AES_BLOCK_SIZE data chunk to process in this
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* update */
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to_process = (sctx->count + len) & ~(AES_BLOCK_SIZE - 1);
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leftover = (sctx->count + len) & (AES_BLOCK_SIZE - 1);
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/* the hardware will not accept a 0 byte operation for this algorithm
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* and the operation MUST be finalized to be correct. So if we happen
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* to get an update that falls on a block sized boundary, we must
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* save off the last block to finalize with later. */
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if (!leftover) {
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to_process -= AES_BLOCK_SIZE;
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leftover = AES_BLOCK_SIZE;
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}
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if (sctx->count) {
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in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buffer,
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sctx->count, nx_ctx->ap->sglen);
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in_sg = nx_build_sg_list(in_sg, (u8 *)data,
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to_process - sctx->count,
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nx_ctx->ap->sglen);
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
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sizeof(struct nx_sg);
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} else {
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)data, to_process,
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nx_ctx->ap->sglen);
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
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sizeof(struct nx_sg);
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}
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NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
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if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
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desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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/* copy the leftover back into the state struct */
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memcpy(sctx->buffer, data + len - leftover, leftover);
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sctx->count = leftover;
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/* everything after the first update is continuation */
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
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out:
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return rc;
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}
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static int nx_xcbc_final(struct shash_desc *desc, u8 *out)
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{
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struct xcbc_state *sctx = shash_desc_ctx(desc);
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = nx_ctx->csbcpb;
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struct nx_sg *in_sg, *out_sg;
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int rc = 0;
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if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
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/* we've hit the nx chip previously, now we're finalizing,
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* so copy over the partial digest */
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memcpy(csbcpb->cpb.aes_xcbc.cv,
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csbcpb->cpb.aes_xcbc.out_cv_mac, AES_BLOCK_SIZE);
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} else if (sctx->count == 0) {
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/* we've never seen an update, so this is a 0 byte op. The
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* hardware cannot handle a 0 byte op, so just copy out the
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* known 0 byte result. This is cheaper than allocating a
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* software context to do a 0 byte op */
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u8 data[] = { 0x75, 0xf0, 0x25, 0x1d, 0x52, 0x8a, 0xc0, 0x1c,
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0x45, 0x73, 0xdf, 0xd5, 0x84, 0xd7, 0x9f, 0x29 };
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memcpy(out, data, sizeof(data));
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goto out;
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}
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/* final is represented by continuing the operation and indicating that
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* this is not an intermediate operation */
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)sctx->buffer,
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sctx->count, nx_ctx->ap->sglen);
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out_sg = nx_build_sg_list(nx_ctx->out_sg, out, AES_BLOCK_SIZE,
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nx_ctx->ap->sglen);
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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if (!nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
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desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->aes_ops));
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memcpy(out, csbcpb->cpb.aes_xcbc.out_cv_mac, AES_BLOCK_SIZE);
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out:
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return rc;
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}
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struct shash_alg nx_shash_aes_xcbc_alg = {
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.digestsize = AES_BLOCK_SIZE,
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.init = nx_xcbc_init,
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.update = nx_xcbc_update,
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.final = nx_xcbc_final,
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.setkey = nx_xcbc_set_key,
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.descsize = sizeof(struct xcbc_state),
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.statesize = sizeof(struct xcbc_state),
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.base = {
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.cra_name = "xcbc(aes)",
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.cra_driver_name = "xcbc-aes-nx",
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.cra_priority = 300,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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.cra_ctxsize = sizeof(struct nx_crypto_ctx),
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.cra_init = nx_crypto_ctx_aes_xcbc_init,
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.cra_exit = nx_crypto_ctx_exit,
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}
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};
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