drm/radeon/kms: Add specific rs690 authorized register table
rs690 is r3xx 3D engine with AVIVO modesetting so we need to allow AVIVO register for vline synchronization. This add a specific table to rs690 to handle that. Thanks to Marc (marvin24) for debugging this and kudos to Andre (taiu1) for spotting the origin of the bugs. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Коммит
616b843468
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@ -308,6 +308,7 @@ static struct radeon_asic rs600_asic = {
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/*
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* rs690,rs740
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*/
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int rs690_init(struct radeon_device *rdev);
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void rs690_errata(struct radeon_device *rdev);
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void rs690_vram_info(struct radeon_device *rdev);
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int rs690_mc_init(struct radeon_device *rdev);
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@ -316,7 +317,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs690_bandwidth_update(struct radeon_device *rdev);
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static struct radeon_asic rs690_asic = {
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.init = &r300_init,
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.init = &rs690_init,
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.errata = &rs690_errata,
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.vram_info = &rs690_vram_info,
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.gpu_reset = &r300_gpu_reset,
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@ -652,3 +652,68 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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WREG32(RS690_MC_DATA, v);
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WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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}
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static const unsigned rs690_reg_safe_bm[219] = {
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF,
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0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000,
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0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF,
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0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF,
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0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,
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0x00000000,0x0000C100,0x00000000,0x00000000,
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0x00000000,0x00000000,0x00000000,0x00000000,
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0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF,
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0x00000000,0x00000000,0x00000000,0x00000000,
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0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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};
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int rs690_init(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm);
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return 0;
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}
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