drm/i915/perf: fix ctx_id read with GuC & ICL
One thing we didn't really understand about the OA report is that the
ContextID field (dword 2) is copy of the context descriptor (dword 1).
On Gen8->10 and without using GuC we didn't notice the issue because
we only checked the 21bits of the ContextID field in the OA reports
which matches exactly the hw_id stored into the context descriptor.
When using GuC submission we have an issue of a non matching hw_id
because GuC uses bit 20 of the hw_id to signal proxy submission. This
change introduces a mask to compare only the relevant bits.
On ICL the context descriptor format has changed and we failed to
address this. On top of using a mask we also need to shift the bits
properly.
v2: Reuse lrc_desc rather than recomputing part of it (Chris/Michel)
v3: Always pin the context we're filtering with (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1de401c08f ("drm/i915/perf: enable perf support on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252
BSpec: 1237
Testcase: igt/perf/gen8-unprivileged-single-ctx-counters
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180602112946.30803-3-lionel.g.landwerlin@intel.com
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
This commit is contained in:
Lionel Landwerlin
Родитель
218b500098
Коммит
61d5676b55
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@ -1951,6 +1951,7 @@ struct drm_i915_private {
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struct intel_context *pinned_ctx;
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u32 specific_ctx_id;
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u32 specific_ctx_id_mask;
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struct hrtimer poll_check_timer;
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wait_queue_head_t poll_wq;
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@ -737,12 +737,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
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continue;
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}
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/*
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* XXX: Just keep the lower 21 bits for now since I'm not
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* entirely sure if the HW touches any of the higher bits in
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* this field
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*/
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ctx_id = report32[2] & 0x1fffff;
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ctx_id = report32[2] & dev_priv->perf.oa.specific_ctx_id_mask;
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/*
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* Squash whatever is in the CTX_ID field if it's marked as
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@ -1203,6 +1198,33 @@ static int i915_oa_read(struct i915_perf_stream *stream,
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return dev_priv->perf.oa.ops.read(stream, buf, count, offset);
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}
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static struct intel_context *oa_pin_context(struct drm_i915_private *i915,
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struct i915_gem_context *ctx)
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{
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struct intel_engine_cs *engine = i915->engine[RCS];
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struct intel_context *ce;
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int ret;
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ret = i915_mutex_lock_interruptible(&i915->drm);
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if (ret)
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return ERR_PTR(ret);
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/*
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* As the ID is the gtt offset of the context's vma we
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* pin the vma to ensure the ID remains fixed.
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*
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* NB: implied RCS engine...
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*/
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ce = intel_context_pin(ctx, engine);
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mutex_unlock(&i915->drm.struct_mutex);
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if (IS_ERR(ce))
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return ce;
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i915->perf.oa.pinned_ctx = ce;
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return ce;
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}
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/**
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* oa_get_render_ctx_id - determine and hold ctx hw id
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* @stream: An i915-perf stream opened for OA metrics
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@ -1215,40 +1237,76 @@ static int i915_oa_read(struct i915_perf_stream *stream,
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*/
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static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
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{
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struct drm_i915_private *dev_priv = stream->dev_priv;
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struct drm_i915_private *i915 = stream->dev_priv;
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struct intel_context *ce;
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if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
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dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id;
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} else {
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struct intel_engine_cs *engine = dev_priv->engine[RCS];
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struct intel_context *ce;
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int ret;
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ret = i915_mutex_lock_interruptible(&dev_priv->drm);
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if (ret)
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return ret;
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ce = oa_pin_context(i915, stream->ctx);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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switch (INTEL_GEN(i915)) {
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case 7: {
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/*
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* As the ID is the gtt offset of the context's vma we
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* pin the vma to ensure the ID remains fixed.
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*
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* NB: implied RCS engine...
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* On Haswell we don't do any post processing of the reports
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* and don't need to use the mask.
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*/
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ce = intel_context_pin(stream->ctx, engine);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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dev_priv->perf.oa.pinned_ctx = ce;
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/*
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* Explicitly track the ID (instead of calling
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* i915_ggtt_offset() on the fly) considering the difference
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* with gen8+ and execlists
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*/
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dev_priv->perf.oa.specific_ctx_id = i915_ggtt_offset(ce->state);
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i915->perf.oa.specific_ctx_id = i915_ggtt_offset(ce->state);
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i915->perf.oa.specific_ctx_id_mask = 0;
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break;
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}
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case 8:
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case 9:
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case 10:
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if (USES_GUC_SUBMISSION(i915)) {
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/*
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* When using GuC, the context descriptor we write in
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* i915 is read by GuC and rewritten before it's
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* actually written into the hardware. The LRCA is
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* what is put into the context id field of the
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* context descriptor by GuC. Because it's aligned to
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* a page, the lower 12bits are always at 0 and
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* dropped by GuC. They won't be part of the context
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* ID in the OA reports, so squash those lower bits.
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*/
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i915->perf.oa.specific_ctx_id =
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lower_32_bits(ce->lrc_desc) >> 12;
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/*
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* GuC uses the top bit to signal proxy submission, so
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* ignore that bit.
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*/
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i915->perf.oa.specific_ctx_id_mask =
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(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
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} else {
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i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
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i915->perf.oa.specific_ctx_id_mask =
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(1U << GEN8_CTX_ID_WIDTH) - 1;
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}
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break;
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case 11: {
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struct intel_engine_cs *engine = i915->engine[RCS];
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i915->perf.oa.specific_ctx_id =
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stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
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engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
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engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
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i915->perf.oa.specific_ctx_id_mask =
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((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
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((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
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((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) << (GEN11_ENGINE_CLASS_SHIFT - 32);
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break;
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}
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default:
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MISSING_CASE(INTEL_GEN(i915));
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}
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DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
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i915->perf.oa.specific_ctx_id,
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i915->perf.oa.specific_ctx_id_mask);
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return 0;
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}
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@ -1265,6 +1323,7 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
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struct intel_context *ce;
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dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
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dev_priv->perf.oa.specific_ctx_id_mask = 0;
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ce = fetch_and_zero(&dev_priv->perf.oa.pinned_ctx);
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if (ce) {
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@ -233,6 +233,11 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
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/* bits 12-31 */
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GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
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/*
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* The following 32bits are copied into the OA reports (dword 2).
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* Consider updating oa_get_render_ctx_id in i915_perf.c when changing
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* anything below.
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*/
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if (INTEL_GEN(ctx->i915) >= 11) {
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GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
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desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
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