KVM: selftests: Add framework to query KVM CPUID bits
Add X86_FEATURE_* magic in the style of KVM-Unit-Tests' implementation, where the CPUID function, index, output register, and output bit position are embedded in the macro value. Add kvm_cpu_has() to query KVM's supported CPUID and use it set_sregs_test, which is the most prolific user of manual feature querying. Opportunstically rename calc_cr4_feature_bits() to calc_supported_cr4_feature_bits() to better capture how the CR4 bits are chosen. Link: https://lore.kernel.org/all/20210422005626.564163-1-ricarkol@google.com Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Suggested-by: Jim Mattson <jmattson@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220614200707.3315957-4-seanjc@google.com
This commit is contained in:
Sean Christopherson
Родитель
683edfd42b
Коммит
61d76b8a69
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@ -45,23 +45,96 @@
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#define X86_CR4_SMAP (1ul << 21)
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#define X86_CR4_PKE (1ul << 22)
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/* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */
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enum cpuid_output_regs {
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KVM_CPUID_EAX,
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KVM_CPUID_EBX,
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KVM_CPUID_ECX,
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KVM_CPUID_EDX
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};
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/*
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* Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
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* passed by value with no overhead.
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*/
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struct kvm_x86_cpu_feature {
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u32 function;
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u16 index;
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u8 reg;
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u8 bit;
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};
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#define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \
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({ \
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struct kvm_x86_cpu_feature feature = { \
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.function = fn, \
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.index = idx, \
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.reg = KVM_CPUID_##gpr, \
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.bit = __bit, \
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}; \
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\
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feature; \
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})
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/*
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* Basic Leafs, a.k.a. Intel defined
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*/
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#define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3)
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#define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5)
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#define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6)
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#define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17)
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#define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22)
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#define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24)
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#define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26)
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#define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27)
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#define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30)
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#define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7)
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#define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9)
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#define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19)
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#define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25)
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#define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26)
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#define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0)
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#define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1)
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#define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4)
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#define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7)
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#define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10)
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#define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11)
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#define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20)
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#define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22)
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#define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23)
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#define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24)
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#define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2)
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#define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3)
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#define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16)
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#define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22)
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#define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7)
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#define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20)
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#define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26)
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#define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29)
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#define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31)
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/*
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* Extended Leafs, a.k.a. AMD defined
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*/
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#define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
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#define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
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#define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
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#define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
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#define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
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#define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
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#define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
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#define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
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#define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
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#define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
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#define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
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#define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
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#define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
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#define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
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/* CPUID.1.ECX */
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#define CPUID_VMX (1ul << 5)
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#define CPUID_SMX (1ul << 6)
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#define CPUID_PCID (1ul << 17)
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#define CPUID_XSAVE (1ul << 26)
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#define CPUID_OSXSAVE (1ul << 27)
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/* CPUID.7.EBX */
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#define CPUID_FSGSBASE (1ul << 0)
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#define CPUID_SMEP (1ul << 7)
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#define CPUID_SMAP (1ul << 20)
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/* CPUID.7.ECX */
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#define CPUID_UMIP (1ul << 2)
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#define CPUID_PKU (1ul << 3)
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#define CPUID_LA57 (1ul << 16)
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/* CPUID.0x8000_0001.EDX */
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#define CPUID_GBPAGES (1ul << 26)
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@ -490,6 +563,15 @@ static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs)
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}
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struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
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bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid,
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struct kvm_x86_cpu_feature feature);
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static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature)
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{
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return kvm_cpuid_has(kvm_get_supported_cpuid(), feature);
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}
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struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vcpu *vcpu);
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static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu,
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@ -734,6 +734,28 @@ struct kvm_cpuid2 *kvm_get_supported_cpuid(void)
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return cpuid;
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}
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bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid,
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struct kvm_x86_cpu_feature feature)
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{
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const struct kvm_cpuid_entry2 *entry;
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int i;
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for (i = 0; i < cpuid->nent; i++) {
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entry = &cpuid->entries[i];
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/*
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* The output registers in kvm_cpuid_entry2 are in alphabetical
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* order, but kvm_x86_cpu_feature matches that mess, so yay
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* pointer shenanigans!
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*/
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if (entry->function == feature.function &&
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entry->index == feature.index)
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return (&entry->eax)[feature.reg] & BIT(feature.bit);
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}
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return false;
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}
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uint64_t kvm_get_feature_msr(uint64_t msr_index)
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{
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struct {
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@ -43,36 +43,32 @@ static void test_cr4_feature_bit(struct kvm_vcpu *vcpu, struct kvm_sregs *orig,
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TEST_ASSERT(!memcmp(&sregs, orig, sizeof(sregs)), "KVM modified sregs");
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}
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static uint64_t calc_cr4_feature_bits(struct kvm_vm *vm)
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static uint64_t calc_supported_cr4_feature_bits(void)
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{
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struct kvm_cpuid_entry2 *cpuid_1, *cpuid_7;
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uint64_t cr4;
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cpuid_1 = kvm_get_supported_cpuid_entry(1);
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cpuid_7 = kvm_get_supported_cpuid_entry(7);
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cr4 = X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE |
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X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_PGE |
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X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT;
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if (cpuid_7->ecx & CPUID_UMIP)
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if (kvm_cpu_has(X86_FEATURE_UMIP))
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cr4 |= X86_CR4_UMIP;
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if (cpuid_7->ecx & CPUID_LA57)
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if (kvm_cpu_has(X86_FEATURE_LA57))
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cr4 |= X86_CR4_LA57;
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if (cpuid_1->ecx & CPUID_VMX)
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if (kvm_cpu_has(X86_FEATURE_VMX))
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cr4 |= X86_CR4_VMXE;
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if (cpuid_1->ecx & CPUID_SMX)
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if (kvm_cpu_has(X86_FEATURE_SMX))
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cr4 |= X86_CR4_SMXE;
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if (cpuid_7->ebx & CPUID_FSGSBASE)
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if (kvm_cpu_has(X86_FEATURE_FSGSBASE))
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cr4 |= X86_CR4_FSGSBASE;
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if (cpuid_1->ecx & CPUID_PCID)
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if (kvm_cpu_has(X86_FEATURE_PCID))
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cr4 |= X86_CR4_PCIDE;
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if (cpuid_1->ecx & CPUID_XSAVE)
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if (kvm_cpu_has(X86_FEATURE_XSAVE))
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cr4 |= X86_CR4_OSXSAVE;
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if (cpuid_7->ebx & CPUID_SMEP)
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if (kvm_cpu_has(X86_FEATURE_SMEP))
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cr4 |= X86_CR4_SMEP;
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if (cpuid_7->ebx & CPUID_SMAP)
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if (kvm_cpu_has(X86_FEATURE_SMAP))
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cr4 |= X86_CR4_SMAP;
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if (cpuid_7->ecx & CPUID_PKU)
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if (kvm_cpu_has(X86_FEATURE_PKU))
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cr4 |= X86_CR4_PKE;
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return cr4;
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@ -99,7 +95,7 @@ int main(int argc, char *argv[])
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vcpu_sregs_get(vcpu, &sregs);
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sregs.cr4 |= calc_cr4_feature_bits(vm);
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sregs.cr4 |= calc_supported_cr4_feature_bits();
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cr4 = sregs.cr4;
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rc = _vcpu_sregs_set(vcpu, &sregs);
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