iommu/arm-smmu: Convert context bank registers to bitfields
Finish the final part of the job, once again updating some names to match the current spec. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Robin Murphy
Will Deacon
Родитель
5114e96cb2
Коммит
620565a76b
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@ -129,19 +129,59 @@ enum arm_smmu_cbar_type {
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#define CBA2R_VA64 BIT(0)
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#define ARM_SMMU_CB_SCTLR 0x0
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#define SCTLR_S1_ASIDPNE BIT(12)
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#define SCTLR_CFCFG BIT(7)
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#define SCTLR_CFIE BIT(6)
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#define SCTLR_CFRE BIT(5)
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#define SCTLR_E BIT(4)
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#define SCTLR_AFE BIT(2)
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#define SCTLR_TRE BIT(1)
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#define SCTLR_M BIT(0)
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#define ARM_SMMU_CB_ACTLR 0x4
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#define ARM_SMMU_CB_RESUME 0x8
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#define ARM_SMMU_CB_TTBCR2 0x10
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#define RESUME_TERMINATE BIT(0)
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#define ARM_SMMU_CB_TCR2 0x10
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#define TCR2_SEP GENMASK(17, 15)
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#define TCR2_SEP_UPSTREAM 0x7
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#define TCR2_AS BIT(4)
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#define ARM_SMMU_CB_TTBR0 0x20
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#define ARM_SMMU_CB_TTBR1 0x28
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#define ARM_SMMU_CB_TTBCR 0x30
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#define TTBRn_ASID GENMASK_ULL(63, 48)
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#define ARM_SMMU_CB_TCR 0x30
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#define ARM_SMMU_CB_CONTEXTIDR 0x34
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_S1_MAIR1 0x3c
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#define ARM_SMMU_CB_PAR 0x50
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#define CB_PAR_F BIT(0)
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#define ARM_SMMU_CB_FSR 0x58
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#define FSR_MULTI BIT(31)
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#define FSR_SS BIT(30)
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#define FSR_UUT BIT(8)
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#define FSR_ASF BIT(7)
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#define FSR_TLBLKF BIT(6)
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#define FSR_TLBMCF BIT(5)
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#define FSR_EF BIT(4)
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#define FSR_PF BIT(3)
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#define FSR_AFF BIT(2)
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#define FSR_TF BIT(1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define ARM_SMMU_CB_FAR 0x60
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define FSYNR0_WNR BIT(4)
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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@ -150,46 +190,8 @@ enum arm_smmu_cbar_type {
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#define ARM_SMMU_CB_TLBSYNC 0x7f0
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#define ARM_SMMU_CB_TLBSTATUS 0x7f4
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#define ARM_SMMU_CB_ATS1PR 0x800
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#define ARM_SMMU_CB_ATSR 0x8f0
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#define SCTLR_S1_ASIDPNE (1 << 12)
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#define SCTLR_CFCFG (1 << 7)
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#define SCTLR_CFIE (1 << 6)
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#define SCTLR_CFRE (1 << 5)
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#define SCTLR_E (1 << 4)
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#define SCTLR_AFE (1 << 2)
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#define SCTLR_TRE (1 << 1)
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#define SCTLR_M (1 << 0)
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#define CB_PAR_F (1 << 0)
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#define ATSR_ACTIVE (1 << 0)
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#define RESUME_RETRY (0 << 0)
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#define RESUME_TERMINATE (1 << 0)
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
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#define TTBCR2_AS (1 << 4)
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#define TTBRn_ASID_SHIFT 48
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#define FSR_MULTI (1 << 31)
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#define FSR_SS (1 << 30)
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#define FSR_UUT (1 << 8)
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#define FSR_ASF (1 << 7)
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#define FSR_TLBLKF (1 << 6)
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#define FSR_TLBMCF (1 << 5)
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#define FSR_EF (1 << 4)
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#define FSR_PF (1 << 3)
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#define FSR_AFF (1 << 2)
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#define FSR_TF (1 << 1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR (1 << 4)
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#define ATSR_ACTIVE BIT(0)
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#endif /* _ARM_SMMU_REGS_H */
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@ -628,16 +628,16 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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cb->cfg = cfg;
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/* TTBCR */
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/* TCR */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr;
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} else {
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cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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cb->tcr[1] |= TTBCR2_SEP_UPSTREAM;
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cb->tcr[1] |= FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM);
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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cb->tcr[1] |= TTBCR2_AS;
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cb->tcr[1] |= TCR2_AS;
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}
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} else {
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cb->tcr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
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@ -650,9 +650,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
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} else {
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cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
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cb->ttbr[0] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid);
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cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
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cb->ttbr[1] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid);
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}
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} else {
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cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
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@ -721,13 +721,13 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
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writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(idx));
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/*
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* TTBCR
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* TCR
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* We must write this before the TTBRs, since it determines the
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* access behaviour of some fields (in particular, ASID[15:8]).
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*/
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if (stage1 && smmu->version > ARM_SMMU_V1)
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writel_relaxed(cb->tcr[1], cb_base + ARM_SMMU_CB_TTBCR2);
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writel_relaxed(cb->tcr[0], cb_base + ARM_SMMU_CB_TTBCR);
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writel_relaxed(cb->tcr[1], cb_base + ARM_SMMU_CB_TCR2);
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writel_relaxed(cb->tcr[0], cb_base + ARM_SMMU_CB_TCR);
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/* TTBRs */
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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@ -7,6 +7,7 @@
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*/
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#include <linux/atomic.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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@ -247,16 +248,16 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
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/* TTBRs */
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iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
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pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
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((u64)ctx->asid << TTBRn_ASID_SHIFT));
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FIELD_PREP(TTBRn_ASID, ctx->asid));
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iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
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pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
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((u64)ctx->asid << TTBRn_ASID_SHIFT));
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FIELD_PREP(TTBRn_ASID, ctx->asid));
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/* TTBCR */
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iommu_writel(ctx, ARM_SMMU_CB_TTBCR2,
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/* TCR */
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iommu_writel(ctx, ARM_SMMU_CB_TCR2,
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(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
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TTBCR2_SEP_UPSTREAM);
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iommu_writel(ctx, ARM_SMMU_CB_TTBCR,
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FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
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iommu_writel(ctx, ARM_SMMU_CB_TCR,
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pgtbl_cfg.arm_lpae_s1_cfg.tcr);
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/* MAIRs (stage-1 only) */
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