ASoC: omap-mcpdm: Collect link direction configuration under a struct
mcpdm_link_config will collect the link direction related configurations like channel masks, FIFO threshold. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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623766318a
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@ -45,6 +45,11 @@
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#define OMAP44XX_MCPDM_L3_BASE 0x49032000
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#define OMAP44XX_MCPDM_L3_BASE 0x49032000
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struct mcpdm_link_config {
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u32 link_mask; /* channel mask for the direction */
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u32 threshold; /* FIFO threshold */
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};
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struct omap_mcpdm {
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struct omap_mcpdm {
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struct device *dev;
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struct device *dev;
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unsigned long phys_base;
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unsigned long phys_base;
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@ -53,13 +58,8 @@ struct omap_mcpdm {
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struct mutex mutex;
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struct mutex mutex;
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/* channel data */
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/* Playback/Capture configuration */
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u32 dn_channels;
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struct mcpdm_link_config config[2];
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u32 up_channels;
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/* McPDM FIFO thresholds */
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u32 dn_threshold;
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u32 up_threshold;
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/* McPDM dn offsets for rx1, and 2 channels */
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/* McPDM dn offsets for rx1, and 2 channels */
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u32 dn_rx_offset;
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u32 dn_rx_offset;
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@ -130,11 +130,12 @@ static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
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static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
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static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
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{
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{
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
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ctrl |= link_mask;
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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@ -148,11 +149,12 @@ static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
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static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
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static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
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{
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{
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
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ctrl &= ~(link_mask);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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@ -188,8 +190,10 @@ static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
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omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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}
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}
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
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mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
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mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
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MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
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MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
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@ -296,6 +300,7 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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int stream = substream->stream;
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int stream = substream->stream;
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struct omap_pcm_dma_data *dma_data;
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struct omap_pcm_dma_data *dma_data;
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u32 threshold;
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int channels;
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int channels;
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int link_mask = 0;
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int link_mask = 0;
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@ -325,15 +330,16 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
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dma_data = snd_soc_dai_get_dma_data(dai, substream);
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dma_data = snd_soc_dai_get_dma_data(dai, substream);
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threshold = mcpdm->config[stream].threshold;
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/* Configure McPDM channels, and DMA packet size */
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/* Configure McPDM channels, and DMA packet size */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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mcpdm->dn_channels = link_mask << 3;
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link_mask <<= 3;
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dma_data->packet_size =
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dma_data->packet_size =
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(MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
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(MCPDM_DN_THRES_MAX - threshold) * channels;
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} else {
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} else {
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mcpdm->up_channels = link_mask << 0;
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dma_data->packet_size = threshold * channels;
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dma_data->packet_size = mcpdm->up_threshold * channels;
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}
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}
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mcpdm->config[stream].link_mask = link_mask;
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return 0;
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return 0;
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}
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}
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@ -380,8 +386,9 @@ static int omap_mcpdm_probe(struct snd_soc_dai *dai)
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}
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}
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/* Configure McPDM threshold values */
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/* Configure McPDM threshold values */
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mcpdm->dn_threshold = 2;
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mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
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mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
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mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
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MCPDM_UP_THRES_MAX - 3;
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return ret;
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return ret;
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}
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}
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