Bluetooth: Implement Get PHY Configuration mgmt command
This commands basically retrieve the supported packet types of
BREDR and supported PHYs of the controller.
BR_1M_1SLOT, LE_1M_TX and LE_1M_RX would be supported by default.
Other PHYs are supported based on the local features.
Also this sets PHY_CONFIGURATION bit in supported settings.
@ MGMT Command: Get PHY Configuration (0x0044) plen 0
@ MGMT Event: Command Complete (0x0001) plen 15
Get PHY Configuration (0x0044) plen 12
Status: Success (0x00)
Supported PHYs: 0x7fff
BR 1M 1SLOT
BR 1M 3SLOT
BR 1M 5SLOT
EDR 2M 1SLOT
EDR 2M 3SLOT
EDR 2M 5SLOT
EDR 3M 1SLOT
EDR 3M 3SLOT
EDR 3M 5SLOT
LE 1M TX
LE 1M RX
LE 2M TX
LE 2M RX
LE CODED TX
LE CODED RX
Configurable PHYs: 0x79fe
BR 1M 3SLOT
BR 1M 5SLOT
EDR 2M 1SLOT
EDR 2M 3SLOT
EDR 2M 5SLOT
EDR 3M 1SLOT
EDR 3M 3SLOT
EDR 3M 5SLOT
LE 2M TX
LE 2M RX
LE CODED TX
LE CODED RX
Selected PHYs: 0x07ff
BR 1M 1SLOT
BR 1M 3SLOT
BR 1M 5SLOT
EDR 2M 1SLOT
EDR 2M 3SLOT
EDR 2M 5SLOT
EDR 3M 1SLOT
EDR 3M 3SLOT
EDR 3M 5SLOT
LE 1M TX
LE 1M RX
Signed-off-by: Jaganath Kanakkassery <jaganathx.kanakkassery@intel.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
This commit is contained in:
Jaganath Kanakkassery
Marcel Holtmann
Родитель
5075b972f2
Коммит
6244691fec
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@ -101,6 +101,7 @@ struct mgmt_rp_read_index_list {
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#define MGMT_SETTING_PRIVACY 0x00002000
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#define MGMT_SETTING_CONFIGURATION 0x00004000
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#define MGMT_SETTING_STATIC_ADDRESS 0x00008000
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#define MGMT_SETTING_PHY_CONFIGURATION 0x00010000
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#define MGMT_OP_READ_INFO 0x0004
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#define MGMT_READ_INFO_SIZE 0
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@ -604,6 +605,30 @@ struct mgmt_cp_set_appearance {
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} __packed;
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#define MGMT_SET_APPEARANCE_SIZE 2
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#define MGMT_OP_GET_PHY_CONFIGURATION 0x0044
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struct mgmt_rp_get_phy_confguration {
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__le32 supported_phys;
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__le32 configurable_phys;
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__le32 selected_phys;
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} __packed;
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#define MGMT_GET_PHY_CONFIGURATION_SIZE 0
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#define MGMT_PHY_BR_1M_1SLOT 0x00000001
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#define MGMT_PHY_BR_1M_3SLOT 0x00000002
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#define MGMT_PHY_BR_1M_5SLOT 0x00000004
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#define MGMT_PHY_EDR_2M_1SLOT 0x00000008
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#define MGMT_PHY_EDR_2M_3SLOT 0x00000010
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#define MGMT_PHY_EDR_2M_5SLOT 0x00000020
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#define MGMT_PHY_EDR_3M_1SLOT 0x00000040
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#define MGMT_PHY_EDR_3M_3SLOT 0x00000080
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#define MGMT_PHY_EDR_3M_5SLOT 0x00000100
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#define MGMT_PHY_LE_1M_TX 0x00000200
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#define MGMT_PHY_LE_1M_RX 0x00000400
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#define MGMT_PHY_LE_2M_TX 0x00000800
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#define MGMT_PHY_LE_2M_RX 0x00001000
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#define MGMT_PHY_LE_CODED_TX 0x00002000
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#define MGMT_PHY_LE_CODED_RX 0x00004000
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#define MGMT_EV_CMD_COMPLETE 0x0001
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struct mgmt_ev_cmd_complete {
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__le16 opcode;
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@ -617,6 +617,127 @@ static int read_config_info(struct sock *sk, struct hci_dev *hdev,
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&rp, sizeof(rp));
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}
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static u32 get_supported_phys(struct hci_dev *hdev)
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{
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u32 supported_phys = 0;
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if (lmp_bredr_capable(hdev)) {
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supported_phys |= MGMT_PHY_BR_1M_1SLOT;
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if (hdev->features[0][0] & LMP_3SLOT)
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supported_phys |= MGMT_PHY_BR_1M_3SLOT;
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if (hdev->features[0][0] & LMP_5SLOT)
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supported_phys |= MGMT_PHY_BR_1M_5SLOT;
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if (lmp_edr_2m_capable(hdev)) {
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supported_phys |= MGMT_PHY_EDR_2M_1SLOT;
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if (lmp_edr_3slot_capable(hdev))
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supported_phys |= MGMT_PHY_EDR_2M_3SLOT;
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if (lmp_edr_5slot_capable(hdev))
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supported_phys |= MGMT_PHY_EDR_2M_5SLOT;
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if (lmp_edr_3m_capable(hdev)) {
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supported_phys |= MGMT_PHY_EDR_3M_1SLOT;
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if (lmp_edr_3slot_capable(hdev))
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supported_phys |= MGMT_PHY_EDR_3M_3SLOT;
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if (lmp_edr_5slot_capable(hdev))
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supported_phys |= MGMT_PHY_EDR_3M_5SLOT;
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}
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}
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}
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if (lmp_le_capable(hdev)) {
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supported_phys |= MGMT_PHY_LE_1M_TX;
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supported_phys |= MGMT_PHY_LE_1M_RX;
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if (hdev->le_features[1] & HCI_LE_PHY_2M) {
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supported_phys |= MGMT_PHY_LE_2M_TX;
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supported_phys |= MGMT_PHY_LE_2M_RX;
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}
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if (hdev->le_features[1] & HCI_LE_PHY_CODED) {
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supported_phys |= MGMT_PHY_LE_CODED_TX;
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supported_phys |= MGMT_PHY_LE_CODED_RX;
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}
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}
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return supported_phys;
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}
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static u32 get_selected_phys(struct hci_dev *hdev)
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{
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u32 selected_phys = 0;
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if (lmp_bredr_capable(hdev)) {
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selected_phys |= MGMT_PHY_BR_1M_1SLOT;
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if (hdev->pkt_type & (HCI_DM3 | HCI_DH3))
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selected_phys |= MGMT_PHY_BR_1M_3SLOT;
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if (hdev->pkt_type & (HCI_DM5 | HCI_DH5))
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selected_phys |= MGMT_PHY_BR_1M_5SLOT;
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if (lmp_edr_2m_capable(hdev)) {
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if (!(hdev->pkt_type & HCI_2DH1))
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selected_phys |= MGMT_PHY_EDR_2M_1SLOT;
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if (lmp_edr_3slot_capable(hdev) &&
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!(hdev->pkt_type & HCI_2DH3))
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selected_phys |= MGMT_PHY_EDR_2M_3SLOT;
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if (lmp_edr_5slot_capable(hdev) &&
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!(hdev->pkt_type & HCI_2DH5))
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selected_phys |= MGMT_PHY_EDR_2M_5SLOT;
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if (lmp_edr_3m_capable(hdev)) {
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if (!(hdev->pkt_type & HCI_3DH1))
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selected_phys |= MGMT_PHY_EDR_3M_1SLOT;
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if (lmp_edr_3slot_capable(hdev) &&
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!(hdev->pkt_type & HCI_3DH3))
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selected_phys |= MGMT_PHY_EDR_3M_3SLOT;
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if (lmp_edr_5slot_capable(hdev) &&
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!(hdev->pkt_type & HCI_3DH5))
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selected_phys |= MGMT_PHY_EDR_3M_5SLOT;
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}
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}
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}
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if (lmp_le_capable(hdev)) {
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if (hdev->le_tx_def_phys & HCI_LE_SET_PHY_1M)
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selected_phys |= MGMT_PHY_LE_1M_TX;
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if (hdev->le_rx_def_phys & HCI_LE_SET_PHY_1M)
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selected_phys |= MGMT_PHY_LE_1M_RX;
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if (hdev->le_tx_def_phys & HCI_LE_SET_PHY_2M)
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selected_phys |= MGMT_PHY_LE_2M_TX;
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if (hdev->le_rx_def_phys & HCI_LE_SET_PHY_2M)
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selected_phys |= MGMT_PHY_LE_2M_RX;
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if (hdev->le_tx_def_phys & HCI_LE_SET_PHY_CODED)
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selected_phys |= MGMT_PHY_LE_CODED_TX;
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if (hdev->le_rx_def_phys & HCI_LE_SET_PHY_CODED)
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selected_phys |= MGMT_PHY_LE_CODED_RX;
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}
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return selected_phys;
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}
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static u32 get_configurable_phys(struct hci_dev *hdev)
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{
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return (get_supported_phys(hdev) & ~MGMT_PHY_BR_1M_1SLOT &
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~MGMT_PHY_LE_1M_TX & ~MGMT_PHY_LE_1M_RX);
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}
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static u32 get_supported_settings(struct hci_dev *hdev)
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{
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u32 settings = 0;
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@ -654,6 +775,8 @@ static u32 get_supported_settings(struct hci_dev *hdev)
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hdev->set_bdaddr)
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settings |= MGMT_SETTING_CONFIGURATION;
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settings |= MGMT_SETTING_PHY_CONFIGURATION;
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return settings;
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}
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@ -3184,6 +3307,27 @@ static int set_appearance(struct sock *sk, struct hci_dev *hdev, void *data,
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return err;
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}
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static int get_phy_configuration(struct sock *sk, struct hci_dev *hdev,
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void *data, u16 len)
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{
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struct mgmt_rp_get_phy_confguration rp;
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BT_DBG("sock %p %s", sk, hdev->name);
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hci_dev_lock(hdev);
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memset(&rp, 0, sizeof(rp));
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rp.supported_phys = cpu_to_le32(get_supported_phys(hdev));
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rp.selected_phys = cpu_to_le32(get_selected_phys(hdev));
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rp.configurable_phys = cpu_to_le32(get_configurable_phys(hdev));
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hci_dev_unlock(hdev);
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return mgmt_cmd_complete(sk, hdev->id, MGMT_OP_GET_PHY_CONFIGURATION, 0,
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&rp, sizeof(rp));
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}
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static void read_local_oob_data_complete(struct hci_dev *hdev, u8 status,
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u16 opcode, struct sk_buff *skb)
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{
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@ -6544,6 +6688,7 @@ static const struct hci_mgmt_handler mgmt_handlers[] = {
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{ read_ext_controller_info,MGMT_READ_EXT_INFO_SIZE,
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HCI_MGMT_UNTRUSTED },
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{ set_appearance, MGMT_SET_APPEARANCE_SIZE },
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{ get_phy_configuration, MGMT_GET_PHY_CONFIGURATION_SIZE },
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};
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void mgmt_index_added(struct hci_dev *hdev)
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