driver/net: enic: Try DMA 64 first, then failover to DMA
In servers with more than 1.1 TB of RAM, the existing 40/32 bit DMA could cause failure as the DMA-able address could go outside the range addressable using 40/32 bits. The following patch first tried 64 bit DMA if possible, failover to 32 bit. Signed-off-by: Sujith Sankar <ssujith@cisco.com> Signed-off-by: Christian Benvenuti <benve@cisco.com> Signed-off-by: Govindarajulu Varadarajan <govindarajulu90@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Коммит
624dbf55a3
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@ -2080,11 +2080,11 @@ static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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pci_set_master(pdev);
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pci_set_master(pdev);
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/* Query PCI controller on system for DMA addressing
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/* Query PCI controller on system for DMA addressing
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* limitation for the device. Try 40-bit first, and
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* limitation for the device. Try 64-bit first, and
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* fail to 32-bit.
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* fail to 32-bit.
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*/
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*/
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (err) {
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (err) {
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if (err) {
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@ -2098,10 +2098,10 @@ static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto err_out_release_regions;
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goto err_out_release_regions;
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}
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}
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} else {
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} else {
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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if (err) {
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if (err) {
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dev_err(dev, "Unable to obtain %u-bit DMA "
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dev_err(dev, "Unable to obtain %u-bit DMA "
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"for consistent allocations, aborting\n", 40);
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"for consistent allocations, aborting\n", 64);
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goto err_out_release_regions;
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goto err_out_release_regions;
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}
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}
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using_dac = 1;
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using_dac = 1;
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