x86, UV: Update node controller MMRs
A new version of the SGI UV hub node controller is being developed. A few of the MMRs (control registers) that exist on the current hub no longer exist on the new hub. Fortunately, there are alternate MMRs that are are functionally equivalent and that exist on both hubs. This patch changes the UV code to use MMRs that exist in BOTH versions of the hub node controller. Signed-off-by: Jack Steiner <steiner@sgi.com> LKML-Reference: <20101106204056.GA27584@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Jack Steiner
Ingo Molnar
Родитель
8e5e9521c1
Коммит
62b0cfc240
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@ -805,6 +805,78 @@ union uvh_node_present_table_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
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/* ========================================================================= */
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@ -856,6 +928,29 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
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#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
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#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
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#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
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#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
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#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
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#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
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union uvh_rh_gam_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_config_mmr_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_10_11: 2; /* */
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unsigned long mmiol_cfg : 1; /* RW */
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unsigned long rsvd_13_63: 51; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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@ -987,97 +1082,5 @@ union uvh_rtc1_int_config_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ADDR_MAP_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
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union uvh_si_addr_map_config_u {
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unsigned long v;
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struct uvh_si_addr_map_config_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long rsvd_6_7: 2; /* */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_12_63: 52; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias0_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias0_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias1_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias1_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias2_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias2_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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#endif /* _ASM_X86_UV_UV_MMRS_H */
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#endif /* __ASM_UV_MMRS_X86_H__ */
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@ -379,14 +379,14 @@ struct redir_addr {
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#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
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static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
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};
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_si_alias0_overlay_config_u alias;
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
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int i;
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@ -660,7 +660,7 @@ void uv_nmi_init(void)
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void __init uv_system_init(void)
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{
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union uvh_si_addr_map_config_u m_n_config;
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union uvh_rh_gam_config_mmr_u m_n_config;
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union uvh_node_id_u node_id;
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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@ -670,7 +670,7 @@ void __init uv_system_init(void)
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map_low_mmrs();
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m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
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m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
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m_val = m_n_config.s.m_skt;
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n_val = m_n_config.s.n_skt;
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mmr_base =
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