drm/i915/guc: Support request cancellation
This adds GuC backend support for i915_request_cancel(), which in turn makes CONFIG_DRM_I915_REQUEST_TIMEOUT work. This implementation makes use of fence while there are likely simplier options. A fence was chosen because of another feature coming soon which requires a user to block on a context until scheduling is disabled. In that case we return the fence to the user and the user can wait on that fence. v2: (Daniele) - A comment about locking the blocked incr / decr - A comments about the use of the fence - Update commit message explaining why fence - Delete redundant check blocked count in unblock function - Ring buffer implementation - Comment about blocked in submission path - Shorter rpm path v3: (Checkpatch) - Fix typos in commit message (Daniel) - Rework to simplier locking structure in guc_context_block / unblock Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210727002348.97202-26-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
John Harrison
Родитель
ae8ac10dfd
Коммит
62eaf0ae21
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@ -366,6 +366,12 @@ static int __intel_context_active(struct i915_active *active)
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return 0;
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}
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static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
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enum i915_sw_fence_notify state)
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{
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return NOTIFY_DONE;
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}
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void
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intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
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{
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@ -399,6 +405,13 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
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ce->guc_id = GUC_INVALID_LRC_ID;
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INIT_LIST_HEAD(&ce->guc_id_link);
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/*
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* Initialize fence to be complete as this is expected to be complete
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* unless there is a pending schedule disable outstanding.
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*/
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i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
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i915_sw_fence_commit(&ce->guc_blocked);
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i915_active_init(&ce->active,
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__intel_context_active, __intel_context_retire, 0);
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}
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@ -70,6 +70,13 @@ intel_context_is_pinned(struct intel_context *ce)
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return atomic_read(&ce->pin_count);
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}
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static inline void intel_context_cancel_request(struct intel_context *ce,
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struct i915_request *rq)
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{
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GEM_BUG_ON(!ce->ops->cancel_request);
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return ce->ops->cancel_request(ce, rq);
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}
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/**
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* intel_context_unlock_pinned - Releases the earlier locking of 'pinned' status
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* @ce - the context
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@ -13,6 +13,7 @@
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#include <linux/types.h>
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#include "i915_active_types.h"
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#include "i915_sw_fence.h"
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#include "i915_utils.h"
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#include "intel_engine_types.h"
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#include "intel_sseu.h"
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@ -42,6 +43,9 @@ struct intel_context_ops {
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void (*unpin)(struct intel_context *ce);
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void (*post_unpin)(struct intel_context *ce);
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void (*cancel_request)(struct intel_context *ce,
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struct i915_request *rq);
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void (*enter)(struct intel_context *ce);
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void (*exit)(struct intel_context *ce);
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@ -156,7 +160,7 @@ struct intel_context {
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* sched_state: scheduling state of this context using GuC
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* submission
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*/
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u8 sched_state;
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u16 sched_state;
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/*
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* fences: maintains of list of requests that have a submit
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* fence related to GuC submission
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@ -184,6 +188,9 @@ struct intel_context {
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* GuC ID link - in list when unpinned but guc_id still valid in GuC
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*/
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struct list_head guc_id_link;
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/* GuC context blocked fence */
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struct i915_sw_fence guc_blocked;
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};
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#endif /* __INTEL_CONTEXT_TYPES__ */
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@ -114,6 +114,7 @@
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#include "gen8_engine_cs.h"
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#include "intel_breadcrumbs.h"
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#include "intel_context.h"
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#include "intel_engine_heartbeat.h"
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#include "intel_engine_pm.h"
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#include "intel_engine_stats.h"
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#include "intel_execlists_submission.h"
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@ -2587,11 +2588,26 @@ static int execlists_context_alloc(struct intel_context *ce)
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return lrc_alloc(ce, ce->engine);
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}
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static void execlists_context_cancel_request(struct intel_context *ce,
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struct i915_request *rq)
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{
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struct intel_engine_cs *engine = NULL;
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i915_request_active_engine(rq, &engine);
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if (engine && intel_engine_pulse(engine))
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intel_gt_handle_error(engine->gt, engine->mask, 0,
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"request cancellation by %s",
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current->comm);
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}
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static const struct intel_context_ops execlists_context_ops = {
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.flags = COPS_HAS_INFLIGHT,
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.alloc = execlists_context_alloc,
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.cancel_request = execlists_context_cancel_request,
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.pre_pin = execlists_context_pre_pin,
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.pin = execlists_context_pin,
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.unpin = lrc_unpin,
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@ -3608,6 +3624,8 @@ static const struct intel_context_ops virtual_context_ops = {
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.alloc = virtual_context_alloc,
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.cancel_request = execlists_context_cancel_request,
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.pre_pin = virtual_context_pre_pin,
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.pin = virtual_context_pin,
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.unpin = lrc_unpin,
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@ -16,6 +16,7 @@
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#include "intel_reset.h"
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#include "intel_ring.h"
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#include "shmem_utils.h"
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#include "intel_engine_heartbeat.h"
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/* Rough estimate of the typical request size, performing a flush,
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* set-context and then emitting the batch.
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@ -604,9 +605,24 @@ static void ring_context_ban(struct intel_context *ce,
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}
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}
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static void ring_context_cancel_request(struct intel_context *ce,
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struct i915_request *rq)
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{
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struct intel_engine_cs *engine = NULL;
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i915_request_active_engine(rq, &engine);
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if (engine && intel_engine_pulse(engine))
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intel_gt_handle_error(engine->gt, engine->mask, 0,
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"request cancellation by %s",
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current->comm);
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}
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static const struct intel_context_ops ring_context_ops = {
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.alloc = ring_context_alloc,
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.cancel_request = ring_context_cancel_request,
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.ban = ring_context_ban,
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.pre_pin = ring_context_pre_pin,
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@ -126,6 +126,9 @@ static inline void clr_context_pending_enable(struct intel_context *ce)
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#define SCHED_STATE_DESTROYED BIT(1)
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#define SCHED_STATE_PENDING_DISABLE BIT(2)
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#define SCHED_STATE_BANNED BIT(3)
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#define SCHED_STATE_BLOCKED_SHIFT 4
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#define SCHED_STATE_BLOCKED BIT(SCHED_STATE_BLOCKED_SHIFT)
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#define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT)
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static inline void init_sched_state(struct intel_context *ce)
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{
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/* Only should be called from guc_lrc_desc_pin() */
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@ -203,6 +206,32 @@ static inline void clr_context_banned(struct intel_context *ce)
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ce->guc_state.sched_state &= ~SCHED_STATE_BANNED;
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}
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static inline u32 context_blocked(struct intel_context *ce)
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{
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return (ce->guc_state.sched_state & SCHED_STATE_BLOCKED_MASK) >>
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SCHED_STATE_BLOCKED_SHIFT;
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}
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static inline void incr_context_blocked(struct intel_context *ce)
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{
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lockdep_assert_held(&ce->engine->sched_engine->lock);
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lockdep_assert_held(&ce->guc_state.lock);
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ce->guc_state.sched_state += SCHED_STATE_BLOCKED;
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GEM_BUG_ON(!context_blocked(ce)); /* Overflow check */
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}
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static inline void decr_context_blocked(struct intel_context *ce)
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{
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lockdep_assert_held(&ce->engine->sched_engine->lock);
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lockdep_assert_held(&ce->guc_state.lock);
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GEM_BUG_ON(!context_blocked(ce)); /* Underflow check */
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ce->guc_state.sched_state -= SCHED_STATE_BLOCKED;
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}
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static inline bool context_guc_id_invalid(struct intel_context *ce)
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{
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return ce->guc_id == GUC_INVALID_LRC_ID;
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@ -404,6 +433,14 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
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if (unlikely(err))
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goto out;
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}
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/*
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* The request / context will be run on the hardware when scheduling
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* gets enabled in the unblock.
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*/
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if (unlikely(context_blocked(ce)))
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goto out;
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enabled = context_enabled(ce);
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if (!enabled) {
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@ -532,6 +569,7 @@ static void __guc_context_destroy(struct intel_context *ce);
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static void release_guc_id(struct intel_guc *guc, struct intel_context *ce);
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static void guc_signal_context_fence(struct intel_context *ce);
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static void guc_cancel_context_requests(struct intel_context *ce);
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static void guc_blocked_fence_complete(struct intel_context *ce);
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static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc)
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{
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@ -579,6 +617,10 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc)
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}
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intel_context_sched_disable_unpin(ce);
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atomic_dec(&guc->outstanding_submission_g2h);
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spin_lock_irqsave(&ce->guc_state.lock, flags);
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guc_blocked_fence_complete(ce);
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spin_unlock_irqrestore(&ce->guc_state.lock, flags);
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intel_context_put(ce);
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}
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}
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@ -1354,6 +1396,21 @@ static void guc_context_post_unpin(struct intel_context *ce)
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lrc_post_unpin(ce);
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}
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static void __guc_context_sched_enable(struct intel_guc *guc,
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struct intel_context *ce)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET,
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ce->guc_id,
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GUC_CONTEXT_ENABLE
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};
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trace_intel_context_sched_enable(ce);
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guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
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G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
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}
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static void __guc_context_sched_disable(struct intel_guc *guc,
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struct intel_context *ce,
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u16 guc_id)
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@ -1372,17 +1429,143 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
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G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
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}
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static void guc_blocked_fence_complete(struct intel_context *ce)
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{
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lockdep_assert_held(&ce->guc_state.lock);
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if (!i915_sw_fence_done(&ce->guc_blocked))
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i915_sw_fence_complete(&ce->guc_blocked);
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}
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static void guc_blocked_fence_reinit(struct intel_context *ce)
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{
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lockdep_assert_held(&ce->guc_state.lock);
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GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_blocked));
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/*
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* This fence is always complete unless a pending schedule disable is
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* outstanding. We arm the fence here and complete it when we receive
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* the pending schedule disable complete message.
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*/
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i915_sw_fence_fini(&ce->guc_blocked);
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i915_sw_fence_reinit(&ce->guc_blocked);
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i915_sw_fence_await(&ce->guc_blocked);
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i915_sw_fence_commit(&ce->guc_blocked);
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}
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static u16 prep_context_pending_disable(struct intel_context *ce)
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{
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lockdep_assert_held(&ce->guc_state.lock);
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set_context_pending_disable(ce);
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clr_context_enabled(ce);
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guc_blocked_fence_reinit(ce);
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intel_context_get(ce);
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return ce->guc_id;
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}
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static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
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{
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struct intel_guc *guc = ce_to_guc(ce);
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struct i915_sched_engine *sched_engine = ce->engine->sched_engine;
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unsigned long flags;
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struct intel_runtime_pm *runtime_pm = ce->engine->uncore->rpm;
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intel_wakeref_t wakeref;
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u16 guc_id;
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bool enabled;
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spin_lock_irqsave(&ce->guc_state.lock, flags);
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/*
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* Sync with submission path, increment before below changes to context
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* state.
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*/
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spin_lock(&sched_engine->lock);
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incr_context_blocked(ce);
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spin_unlock(&sched_engine->lock);
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enabled = context_enabled(ce);
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if (unlikely(!enabled || submission_disabled(guc))) {
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if (enabled)
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clr_context_enabled(ce);
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spin_unlock_irqrestore(&ce->guc_state.lock, flags);
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return &ce->guc_blocked;
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}
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/*
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* We add +2 here as the schedule disable complete CTB handler calls
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* intel_context_sched_disable_unpin (-2 to pin_count).
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*/
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atomic_add(2, &ce->pin_count);
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guc_id = prep_context_pending_disable(ce);
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spin_unlock_irqrestore(&ce->guc_state.lock, flags);
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with_intel_runtime_pm(runtime_pm, wakeref)
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__guc_context_sched_disable(guc, ce, guc_id);
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return &ce->guc_blocked;
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}
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static void guc_context_unblock(struct intel_context *ce)
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{
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struct intel_guc *guc = ce_to_guc(ce);
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struct i915_sched_engine *sched_engine = ce->engine->sched_engine;
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unsigned long flags;
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struct intel_runtime_pm *runtime_pm = ce->engine->uncore->rpm;
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intel_wakeref_t wakeref;
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bool enable;
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GEM_BUG_ON(context_enabled(ce));
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spin_lock_irqsave(&ce->guc_state.lock, flags);
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if (unlikely(submission_disabled(guc) ||
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!intel_context_is_pinned(ce) ||
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context_pending_disable(ce) ||
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context_blocked(ce) > 1)) {
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enable = false;
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} else {
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enable = true;
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set_context_pending_enable(ce);
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set_context_enabled(ce);
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intel_context_get(ce);
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}
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/*
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* Sync with submission path, decrement after above changes to context
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* state.
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*/
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spin_lock(&sched_engine->lock);
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decr_context_blocked(ce);
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spin_unlock(&sched_engine->lock);
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spin_unlock_irqrestore(&ce->guc_state.lock, flags);
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if (enable) {
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with_intel_runtime_pm(runtime_pm, wakeref)
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__guc_context_sched_enable(guc, ce);
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}
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}
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static void guc_context_cancel_request(struct intel_context *ce,
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struct i915_request *rq)
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{
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if (i915_sw_fence_signaled(&rq->submit)) {
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struct i915_sw_fence *fence = guc_context_block(ce);
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i915_sw_fence_wait(fence);
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if (!i915_request_completed(rq)) {
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__i915_request_skip(rq);
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guc_reset_state(ce, intel_ring_wrap(ce->ring, rq->head),
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true);
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}
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guc_context_unblock(ce);
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}
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}
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|
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static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
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u16 guc_id,
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u32 preemption_timeout)
|
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|
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@ -1642,6 +1825,8 @@ static const struct intel_context_ops guc_context_ops = {
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.ban = guc_context_ban,
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.cancel_request = guc_context_cancel_request,
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.enter = intel_context_enter_engine,
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.exit = intel_context_exit_engine,
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|
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@ -1837,6 +2022,8 @@ static const struct intel_context_ops virtual_guc_context_ops = {
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.ban = guc_context_ban,
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.cancel_request = guc_context_cancel_request,
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.enter = guc_virtual_context_enter,
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.exit = guc_virtual_context_exit,
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|
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@ -2295,6 +2482,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
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clr_context_banned(ce);
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clr_context_pending_disable(ce);
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__guc_signal_context_fence(ce);
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guc_blocked_fence_complete(ce);
|
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spin_unlock_irqrestore(&ce->guc_state.lock, flags);
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|
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if (banned) {
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||||
|
|
|
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|
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@ -710,18 +710,6 @@ void i915_request_unsubmit(struct i915_request *request)
|
|||
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
|
||||
}
|
||||
|
||||
static void __cancel_request(struct i915_request *rq)
|
||||
{
|
||||
struct intel_engine_cs *engine = NULL;
|
||||
|
||||
i915_request_active_engine(rq, &engine);
|
||||
|
||||
if (engine && intel_engine_pulse(engine))
|
||||
intel_gt_handle_error(engine->gt, engine->mask, 0,
|
||||
"request cancellation by %s",
|
||||
current->comm);
|
||||
}
|
||||
|
||||
void i915_request_cancel(struct i915_request *rq, int error)
|
||||
{
|
||||
if (!i915_request_set_error_once(rq, error))
|
||||
|
|
@ -729,7 +717,7 @@ void i915_request_cancel(struct i915_request *rq, int error)
|
|||
|
||||
set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags);
|
||||
|
||||
__cancel_request(rq);
|
||||
intel_context_cancel_request(rq->context, rq);
|
||||
}
|
||||
|
||||
static int __i915_sw_fence_call
|
||||
|
|
|
|||
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Ссылка в новой задаче