dmaengine: mpc512x: add support for peripheral transfers
Introduce support for slave s/g transfer preparation and the associated device control callback in the MPC512x DMA controller driver, which adds support for data transfers between memory and peripheral I/O to the previously supported mem-to-mem transfers. Signed-off-by: Alexander Popov <a13xp0p0v88@gmail.com> [fixed subsytem name] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Alexander Popov
Vinod Koul
Родитель
ba730340f9
Коммит
63da8e0d4f
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@ -2,6 +2,7 @@
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* Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
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* Copyright (C) Semihalf 2009
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010
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* Copyright (C) Alexander Popov, Promcontroller 2014
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*
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* Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
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* (defines, structures and comments) was taken from MPC5121 DMA driver
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@ -29,8 +30,18 @@
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*/
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/*
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* This is initial version of MPC5121 DMA driver. Only memory to memory
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* transfers are supported (tested using dmatest module).
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* MPC512x and MPC8308 DMA driver. It supports
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* memory to memory data transfers (tested using dmatest module) and
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* data transfers between memory and peripheral I/O memory
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* by means of slave scatter/gather with these limitations:
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* - chunked transfers (described by s/g lists with more than one item)
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* are refused as long as proper support for scatter/gather is missing;
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* - transfers on MPC8308 always start from software as this SoC appears
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* not to have external request lines for peripheral flow control;
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* - only peripheral devices with 4-byte FIFO access register are supported;
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* - minimal memory <-> I/O memory transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst) boundary;
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*/
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#include <linux/module.h>
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@ -189,6 +200,7 @@ struct mpc_dma_desc {
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dma_addr_t tcd_paddr;
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int error;
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struct list_head node;
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int will_access_peripheral;
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};
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struct mpc_dma_chan {
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@ -201,6 +213,12 @@ struct mpc_dma_chan {
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struct mpc_dma_tcd *tcd;
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dma_addr_t tcd_paddr;
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/* Settings for access to peripheral FIFO */
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dma_addr_t src_per_paddr;
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u32 src_tcd_nunits;
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dma_addr_t dst_per_paddr;
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u32 dst_tcd_nunits;
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/* Lock for this structure */
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spinlock_t lock;
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};
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@ -251,8 +269,23 @@ static void mpc_dma_execute(struct mpc_dma_chan *mchan)
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struct mpc_dma_desc *mdesc;
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int cid = mchan->chan.chan_id;
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/* Move all queued descriptors to active list */
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list_splice_tail_init(&mchan->queued, &mchan->active);
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while (!list_empty(&mchan->queued)) {
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mdesc = list_first_entry(&mchan->queued,
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struct mpc_dma_desc, node);
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/*
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* Grab either several mem-to-mem transfer descriptors
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* or one peripheral transfer descriptor,
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* don't mix mem-to-mem and peripheral transfer descriptors
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* within the same 'active' list.
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*/
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if (mdesc->will_access_peripheral) {
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if (list_empty(&mchan->active))
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list_move_tail(&mdesc->node, &mchan->active);
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break;
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} else {
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list_move_tail(&mdesc->node, &mchan->active);
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}
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}
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/* Chain descriptors into one transaction */
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list_for_each_entry(mdesc, &mchan->active, node) {
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@ -278,7 +311,17 @@ static void mpc_dma_execute(struct mpc_dma_chan *mchan)
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if (first != prev)
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mdma->tcd[cid].e_sg = 1;
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out_8(&mdma->regs->dmassrt, cid);
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if (mdma->is_mpc8308) {
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/* MPC8308, no request lines, software initiated start */
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out_8(&mdma->regs->dmassrt, cid);
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} else if (first->will_access_peripheral) {
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/* Peripherals involved, start by external request signal */
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out_8(&mdma->regs->dmaserq, cid);
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} else {
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/* Memory to memory transfer, software initiated start */
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out_8(&mdma->regs->dmassrt, cid);
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}
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}
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/* Handle interrupt on one half of DMA controller (32 channels) */
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@ -596,6 +639,7 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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}
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mdesc->error = 0;
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mdesc->will_access_peripheral = 0;
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tcd = mdesc->tcd;
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/* Prepare Transfer Control Descriptor for this transaction */
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@ -643,6 +687,193 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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return &mdesc->desc;
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}
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static struct dma_async_tx_descriptor *
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mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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struct mpc_dma_desc *mdesc = NULL;
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dma_addr_t per_paddr;
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u32 tcd_nunits;
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struct mpc_dma_tcd *tcd;
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unsigned long iflags;
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struct scatterlist *sg;
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size_t len;
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int iter, i;
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/* Currently there is no proper support for scatter/gather */
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if (sg_len != 1)
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return NULL;
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if (!is_slave_direction(direction))
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return NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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spin_lock_irqsave(&mchan->lock, iflags);
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mdesc = list_first_entry(&mchan->free,
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struct mpc_dma_desc, node);
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if (!mdesc) {
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spin_unlock_irqrestore(&mchan->lock, iflags);
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/* Try to free completed descriptors */
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mpc_dma_process_completed(mdma);
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return NULL;
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}
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list_del(&mdesc->node);
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if (direction == DMA_DEV_TO_MEM) {
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per_paddr = mchan->src_per_paddr;
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tcd_nunits = mchan->src_tcd_nunits;
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} else {
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per_paddr = mchan->dst_per_paddr;
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tcd_nunits = mchan->dst_tcd_nunits;
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}
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spin_unlock_irqrestore(&mchan->lock, iflags);
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if (per_paddr == 0 || tcd_nunits == 0)
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goto err_prep;
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mdesc->error = 0;
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mdesc->will_access_peripheral = 1;
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/* Prepare Transfer Control Descriptor for this transaction */
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tcd = mdesc->tcd;
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memset(tcd, 0, sizeof(struct mpc_dma_tcd));
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if (!IS_ALIGNED(sg_dma_address(sg), 4))
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goto err_prep;
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if (direction == DMA_DEV_TO_MEM) {
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tcd->saddr = per_paddr;
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tcd->daddr = sg_dma_address(sg);
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tcd->soff = 0;
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tcd->doff = 4;
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} else {
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tcd->saddr = sg_dma_address(sg);
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tcd->daddr = per_paddr;
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tcd->soff = 4;
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tcd->doff = 0;
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}
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tcd->ssize = MPC_DMA_TSIZE_4;
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tcd->dsize = MPC_DMA_TSIZE_4;
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len = sg_dma_len(sg);
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tcd->nbytes = tcd_nunits * 4;
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if (!IS_ALIGNED(len, tcd->nbytes))
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goto err_prep;
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iter = len / tcd->nbytes;
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if (iter >= 1 << 15) {
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/* len is too big */
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goto err_prep;
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}
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/* citer_linkch contains the high bits of iter */
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tcd->biter = iter & 0x1ff;
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tcd->biter_linkch = iter >> 9;
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tcd->citer = tcd->biter;
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tcd->citer_linkch = tcd->biter_linkch;
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tcd->e_sg = 0;
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tcd->d_req = 1;
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/* Place descriptor in prepared list */
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spin_lock_irqsave(&mchan->lock, iflags);
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list_add_tail(&mdesc->node, &mchan->prepared);
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spin_unlock_irqrestore(&mchan->lock, iflags);
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}
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return &mdesc->desc;
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err_prep:
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/* Put the descriptor back */
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spin_lock_irqsave(&mchan->lock, iflags);
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list_add_tail(&mdesc->node, &mchan->free);
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spin_unlock_irqrestore(&mchan->lock, iflags);
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return NULL;
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}
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static int mpc_dma_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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struct mpc_dma_chan *mchan;
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struct mpc_dma *mdma;
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struct dma_slave_config *cfg;
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unsigned long flags;
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mchan = dma_chan_to_mpc_dma_chan(chan);
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switch (cmd) {
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case DMA_TERMINATE_ALL:
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/* Disable channel requests */
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mdma = dma_chan_to_mpc_dma(chan);
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spin_lock_irqsave(&mchan->lock, flags);
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out_8(&mdma->regs->dmacerq, chan->chan_id);
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list_splice_tail_init(&mchan->prepared, &mchan->free);
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list_splice_tail_init(&mchan->queued, &mchan->free);
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list_splice_tail_init(&mchan->active, &mchan->free);
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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case DMA_SLAVE_CONFIG:
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/*
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* Software constraints:
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* - only transfers between a peripheral device and
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* memory are supported;
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* - only peripheral devices with 4-byte FIFO access register
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* are supported;
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* - minimal transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst)
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* boundary;
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* - during the transfer RAM address is being incremented by
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* the size of minimal transfer chunk;
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* - peripheral port's address is constant during the transfer.
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*/
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cfg = (void *)arg;
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if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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!IS_ALIGNED(cfg->src_addr, 4) ||
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!IS_ALIGNED(cfg->dst_addr, 4)) {
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return -EINVAL;
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}
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spin_lock_irqsave(&mchan->lock, flags);
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mchan->src_per_paddr = cfg->src_addr;
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mchan->src_tcd_nunits = cfg->src_maxburst;
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mchan->dst_per_paddr = cfg->dst_addr;
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mchan->dst_tcd_nunits = cfg->dst_maxburst;
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/* Apply defaults */
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if (mchan->src_tcd_nunits == 0)
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mchan->src_tcd_nunits = 1;
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if (mchan->dst_tcd_nunits == 0)
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mchan->dst_tcd_nunits = 1;
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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default:
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/* Unknown command */
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break;
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}
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return -ENXIO;
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}
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static int mpc_dma_probe(struct platform_device *op)
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{
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struct device_node *dn = op->dev.of_node;
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@ -733,9 +964,12 @@ static int mpc_dma_probe(struct platform_device *op)
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dma->device_issue_pending = mpc_dma_issue_pending;
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dma->device_tx_status = mpc_dma_tx_status;
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dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
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dma->device_prep_slave_sg = mpc_dma_prep_slave_sg;
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dma->device_control = mpc_dma_device_control;
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INIT_LIST_HEAD(&dma->channels);
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dma_cap_set(DMA_MEMCPY, dma->cap_mask);
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dma_cap_set(DMA_SLAVE, dma->cap_mask);
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for (i = 0; i < dma->chancnt; i++) {
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mchan = &mdma->channels[i];
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