drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
Small changes to intel_dp_mode_valid(), allow listing modes that can only be supported in the bigjoiner configuration, which is not supported yet. v13: * Allow bigjoiner if hdisplay >5120 v12: * slice_count logic simplify (Ville) * Fix unnecessary changes in downstream_mode_valid (Ville) v11: * Make intel_dp_can_bigjoiner non static so it can be used in intel_display (Manasi) v10: * Simplify logic (Ville) * Allow bigjoiner on edp (Ville) v9: * Restric Bigjoiner on PORT A (Ville) v8: * use source dotclock for max dotclock (Manasi) v7: * Add can_bigjoiner() helper (Ville) * Pass bigjoiner to plane_size validation (Ville) v6: * Rebase after dp_downstream mode valid changes (Manasi) v5: * Increase max plane width to support 8K with bigjoiner (Maarten) v4: * Rebase (Manasi) Changes since v1: - Disallow bigjoiner on eDP. Changes since v2: - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock, and split off the downstream and source checking to its own function. (Ville) v3: * Rebase (Manasi) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [vsyrjala: * Keep bigjoiner disabled until everything is ready * Appease checkpatch] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201117194718.11462-3-manasi.d.navare@intel.com
This commit is contained in:
Maarten Lankhorst
Manasi Navare
Родитель
e85e745829
Коммит
63dc014e37
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@ -17780,7 +17780,8 @@ intel_mode_valid(struct drm_device *dev,
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enum drm_mode_status
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intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
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const struct drm_display_mode *mode)
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const struct drm_display_mode *mode,
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bool bigjoiner)
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{
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int plane_width_max, plane_height_max;
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@ -17797,7 +17798,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
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* too big for that.
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*/
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if (INTEL_GEN(dev_priv) >= 11) {
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plane_width_max = 5120;
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plane_width_max = 5120 << bigjoiner;
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plane_height_max = 4320;
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} else {
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plane_width_max = 5120;
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@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
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bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
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enum drm_mode_status
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intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
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const struct drm_display_mode *mode);
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const struct drm_display_mode *mode,
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bool bigjoiner);
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enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
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bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
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@ -254,6 +254,20 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
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return max_link_clock * max_lanes;
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}
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bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct intel_encoder *encoder = &intel_dig_port->base;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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/* FIXME remove once everything is in place */
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return false;
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return INTEL_GEN(dev_priv) >= 12 ||
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(INTEL_GEN(dev_priv) == 11 &&
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encoder->port != PORT_A);
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}
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static int cnl_max_source_rate(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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@ -519,7 +533,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
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static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay)
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u32 mode_clock, u32 mode_hdisplay,
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bool bigjoiner)
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{
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u32 bits_per_pixel, max_bpp_small_joiner_ram;
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int i;
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@ -537,6 +552,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
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max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
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mode_hdisplay;
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if (bigjoiner)
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max_bpp_small_joiner_ram *= 2;
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drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
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max_bpp_small_joiner_ram);
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@ -546,6 +565,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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*/
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bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
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if (bigjoiner) {
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u32 max_bpp_bigjoiner =
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i915->max_cdclk_freq * 48 /
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intel_dp_mode_to_fec_clock(mode_clock);
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DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
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bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
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}
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/* Error out if the max bpp is less than smallest allowed valid bpp */
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if (bits_per_pixel < valid_dsc_bpp[0]) {
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drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
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@ -568,7 +596,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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}
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static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock, int mode_hdisplay)
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int mode_clock, int mode_hdisplay,
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bool bigjoiner)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 min_slice_count, i;
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@ -595,12 +624,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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/* Find the closest match to the valid slice count values */
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for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
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if (valid_dsc_slicecount[i] >
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drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
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false))
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u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
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if (test_slice_count >
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drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
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break;
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if (min_slice_count <= valid_dsc_slicecount[i])
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return valid_dsc_slicecount[i];
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/* big joiner needs small joiner to be enabled */
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if (bigjoiner && test_slice_count < 4)
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continue;
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if (min_slice_count <= test_slice_count)
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return test_slice_count;
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}
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drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
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@ -717,6 +752,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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u16 dsc_max_output_bpp = 0;
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u8 dsc_slice_count = 0;
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enum drm_mode_status status;
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bool dsc = false, bigjoiner = false;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return MODE_NO_DBLESCAN;
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@ -737,6 +773,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
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if (mode->clock < 10000)
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return MODE_CLOCK_LOW;
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if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
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intel_dp_can_bigjoiner(intel_dp)) {
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bigjoiner = true;
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max_dotclk *= 2;
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}
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if (target_clock > max_dotclk)
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return MODE_CLOCK_HIGH;
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max_link_clock = intel_dp_max_link_rate(intel_dp);
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max_lanes = intel_dp_max_lane_count(intel_dp);
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@ -765,16 +809,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
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max_link_clock,
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max_lanes,
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target_clock,
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mode->hdisplay) >> 4;
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mode->hdisplay,
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bigjoiner) >> 4;
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dsc_slice_count =
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intel_dp_dsc_get_slice_count(intel_dp,
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target_clock,
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mode->hdisplay);
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mode->hdisplay,
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bigjoiner);
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}
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dsc = dsc_max_output_bpp && dsc_slice_count;
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}
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if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
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target_clock > max_dotclk)
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/* big joiner configuration needs DSC */
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if (bigjoiner && !dsc)
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return MODE_CLOCK_HIGH;
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if (mode_rate > max_rate && !dsc)
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return MODE_CLOCK_HIGH;
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status = intel_dp_mode_valid_downstream(intel_connector,
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@ -782,7 +833,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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if (status != MODE_OK)
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return status;
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return intel_mode_valid_max_plane_size(dev_priv, mode);
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return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
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}
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u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
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@ -2351,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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pipe_config->port_clock,
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pipe_config->lane_count,
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adjusted_mode->crtc_clock,
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adjusted_mode->crtc_hdisplay);
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adjusted_mode->crtc_hdisplay,
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false);
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dsc_dp_slice_count =
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intel_dp_dsc_get_slice_count(intel_dp,
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adjusted_mode->crtc_clock,
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adjusted_mode->crtc_hdisplay);
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adjusted_mode->crtc_hdisplay,
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false);
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if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
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drm_dbg_kms(&dev_priv->drm,
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"Compressed BPP/Slice Count not supported\n");
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@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
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bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
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int intel_dp_link_required(int pixel_clock, int bpp);
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int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
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bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
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bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
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@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
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return 0;
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}
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*status = intel_mode_valid_max_plane_size(dev_priv, mode);
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*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
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return 0;
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}
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@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
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return MODE_CLOCK_HIGH;
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}
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return intel_mode_valid_max_plane_size(dev_priv, mode);
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return intel_mode_valid_max_plane_size(dev_priv, mode, false);
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}
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struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
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@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
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if (status != MODE_OK)
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return status;
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return intel_mode_valid_max_plane_size(dev_priv, mode);
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return intel_mode_valid_max_plane_size(dev_priv, mode, false);
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}
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bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
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