Merge branch 'pci/ctrl/tegra194'
- Fix tegra_pcie_config_ep() power management in error path (Miaoqian Lin) - Convert DT binding to json-schema (Vidya Sagar) - Add DT bindings and driver support for Tegra234 Root Port and Endpoint mode (Vidya Sagar) - Disable MSI for Tegra234 Root Ports so they use INTx for all events (PCIe doesn't allow mixing INTx and MSI/MSI-X) (Vidya Sagar) - Search for Vendor-Specific RAS-DEC capability instead of hard-coding offset (Vidya Sagar) - Fix unintentional APPL_INTR_STATUS_L0 value overwrite in Root Port interrupt handling (Vidya Sagar) - Clear Bandwidth Management interrupt status bit to avoid interrupt storm (Vidya Sagar) - Set default Max Payload Size to 256 bytes (Vidya Sagar) - Fix offset when clearing bit in Data Link Feature capability (Vidya Sagar) - Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar) * pci/ctrl/tegra194: PCI: tegra194: Add Tegra234 PCIe support PCI: tegra194: Extend Endpoint mode support PCI: tegra194: Fix link up retry sequence PCI: tegra194: Clean up the exit path for Endpoint mode PCI: tegra194: Enable support for 256 Byte payload PCI: tegra194: Clear bandwidth management status PCI: tegra194: Fix Root Port interrupt handling PCI: tegra194: Find RAS DES PCIe capability offset Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" PCI: Disable MSI for Tegra234 Root Ports dt-bindings: PCI: tegra234: Add schema for tegra234 Endpoint mode dt-bindings: PCI: tegra234: Add schema for tegra234 Root Port mode dt-bindings: PCI: tegra194: Convert to json-schema PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep() # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h # drivers/pci/controller/dwc/pcie-tegra194.c
This commit is contained in:
Bjorn Helgaas
Коммит
64451ac83f
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@ -0,0 +1,319 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Vidya Sagar <vidyas@nvidia.com>
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description: |
|
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
|
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inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
|
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of the controller instances are dual mode; they can work either in Root
|
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Port mode or Endpoint mode but one at a time.
|
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On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
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On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
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Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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operate in the Endpoint mode because of the way the platform is designed.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-pcie-ep
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- nvidia,tegra234-pcie-ep
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reg:
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items:
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- description: controller's application logic registers
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- description: iATU and DMA registers. This is where the iATU (internal
|
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Address Translation Unit) registers of the PCIe core are made
|
||||
available for software access.
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- description: aperture where the Root Port's own configuration
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||||
registers are available.
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- description: aperture used to map the remote Root Complex address space
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reg-names:
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items:
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- const: appl
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- const: atu_dma
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- const: dbi
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- const: addr_space
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|
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interrupts:
|
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items:
|
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- description: controller interrupt
|
||||
|
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interrupt-names:
|
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items:
|
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- const: intr
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|
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clocks:
|
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items:
|
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- description: module clock
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||||
|
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clock-names:
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items:
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- const: core
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|
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resets:
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items:
|
||||
- description: APB bus interface reset
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- description: module reset
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reset-names:
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items:
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- const: apb
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- const: core
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|
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reset-gpios:
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description: Must contain a phandle to a GPIO controller followed by GPIO
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that is being used as PERST input signal. Please refer to pci.txt.
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|
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phys:
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minItems: 1
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maxItems: 8
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||||
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phy-names:
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minItems: 1
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||||
items:
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||||
- const: p2u-0
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- const: p2u-1
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- const: p2u-2
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- const: p2u-3
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- const: p2u-4
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- const: p2u-5
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- const: p2u-6
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- const: p2u-7
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|
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power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
A phandle to the node that controls power to the respective PCIe
|
||||
controller and a specifier name for the PCIe controller.
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|
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Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
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Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
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|
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interconnects:
|
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items:
|
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- description: memory read client
|
||||
- description: memory write client
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||||
|
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interconnect-names:
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items:
|
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- const: dma-mem # read
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- const: write
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|
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dma-coherent: true
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||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
|
||||
Must contain a pair of phandles to BPMP controller node followed by
|
||||
controller ID. Following are the controller IDs for each controller:
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|
||||
Tegra194
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|
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0: C0
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1: C1
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2: C2
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||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
|
||||
Tegra234
|
||||
|
||||
0 : C0
|
||||
1 : C1
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||||
2 : C2
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||||
3 : C3
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||||
4 : C4
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||||
5 : C5
|
||||
6 : C6
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||||
7 : C7
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8 : C8
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9 : C9
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10: C10
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|
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items:
|
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- items:
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- description: phandle to BPMP controller node
|
||||
- description: PCIe controller ID
|
||||
maximum: 10
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||||
|
||||
nvidia,aspm-cmrt-us:
|
||||
description: Common Mode Restore Time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
|
||||
nvidia,aspm-pwr-on-t-us:
|
||||
description: Power On time for proper operation of ASPM to be specified in
|
||||
microseconds
|
||||
|
||||
nvidia,aspm-l0s-entrance-latency-us:
|
||||
description: ASPM L0s entrance latency to be specified in microseconds
|
||||
|
||||
vddio-pex-ctl-supply:
|
||||
description: A phandle to the regulator supply for PCIe side band signals
|
||||
|
||||
nvidia,refclk-select-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO used to enable REFCLK to controller from the host
|
||||
|
||||
nvidia,enable-ext-refclk:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is configured
|
||||
to receive Reference Clock from the host.
|
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NOTE: This is applicable only for Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
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|
||||
nvidia,enable-srns:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to operate in SRNS (Separate Reference Clocks with No
|
||||
Spread-Spectrum Clocking). NOTE: This is applicable only for
|
||||
Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- reset-gpios
|
||||
- vddio-pex-ctl-supply
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
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||||
#include <dt-bindings/gpio/tegra194-gpio.h>
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||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
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||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
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||||
#size-cells = <2>;
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||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie-ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep";
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||||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
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reset-names = "apb", "core";
|
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|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
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pinctrl-names = "default";
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pinctrl-0 = <&clkreq_c5_bi_dir_state>;
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||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
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||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
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|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
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|
||||
reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
num-lanes = <8>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/gpio/tegra234-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
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#include <dt-bindings/reset/tegra234-reset.h>
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|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
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||||
|
||||
pcie-ep@141a0000 {
|
||||
compatible = "nvidia,tegra234-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
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<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
|
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<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
|
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reset-names = "apb", "core";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,enable-ext-refclk;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon
|
||||
TEGRA234_AON_GPIO(AA, 4)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
num-lanes = <8>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,245 +0,0 @@
|
|||
NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
|
||||
|
||||
This PCIe controller is based on the Synopsis Designware PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml and
|
||||
snps,dw-pcie-ep.yaml.
|
||||
Some of the controller instances are dual mode where in they can work either
|
||||
in root port mode or endpoint mode but one at a time.
|
||||
|
||||
Required properties:
|
||||
- power-domains: A phandle to the node that controls power to the respective
|
||||
PCIe controller and a specifier name for the PCIe controller. Following are
|
||||
the specifiers for the different PCIe controllers
|
||||
TEGRA194_POWER_DOMAIN_PCIEX8B: C0
|
||||
TEGRA194_POWER_DOMAIN_PCIEX1A: C1
|
||||
TEGRA194_POWER_DOMAIN_PCIEX1A: C2
|
||||
TEGRA194_POWER_DOMAIN_PCIEX1A: C3
|
||||
TEGRA194_POWER_DOMAIN_PCIEX4A: C4
|
||||
TEGRA194_POWER_DOMAIN_PCIEX8A: C5
|
||||
these specifiers are defined in
|
||||
"include/dt-bindings/power/tegra194-powergate.h" file.
|
||||
- reg: A list of physical base address and length pairs for each set of
|
||||
controller registers. Must contain an entry for each entry in the reg-names
|
||||
property.
|
||||
- reg-names: Must include the following entries:
|
||||
"appl": Controller's application logic registers
|
||||
"config": As per the definition in snps,dw-pcie.yaml
|
||||
"atu_dma": iATU and DMA registers. This is where the iATU (internal Address
|
||||
Translation Unit) registers of the PCIe core are made available
|
||||
for SW access.
|
||||
"dbi": The aperture where root port's own configuration registers are
|
||||
available
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
"intr": The Tegra interrupt that is asserted for controller interrupts
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- core
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- apb
|
||||
- core
|
||||
- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
|
||||
- phy-names: Must include an entry for each active lane.
|
||||
"p2u-N": where N ranges from 0 to one less than the total number of lanes
|
||||
- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
|
||||
by controller-id. Following are the controller ids for each controller.
|
||||
0: C0
|
||||
1: C1
|
||||
2: C2
|
||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
|
||||
|
||||
RC mode:
|
||||
- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
|
||||
- device_type: Must be "pci" for RC mode
|
||||
- interrupt-names: Must include the following entries:
|
||||
"msi": The Tegra interrupt that is asserted when an MSI is received
|
||||
- bus-range: Range of bus numbers associated with this controller
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- cell 0 specifies the bus and device numbers of the root port:
|
||||
[23:16]: bus number
|
||||
[15:11]: device number
|
||||
- cell 1 denotes the upper 32 address bits and should be 0
|
||||
- cell 2 contains the lower 32 address bits and is used to translate to the
|
||||
CPU address space
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
- ranges: Describes the translation of addresses for root ports and standard
|
||||
PCI regions. The entries must be 7 cells each, where the first three cells
|
||||
correspond to the address as described for the #address-cells property
|
||||
above, the fourth and fifth cells are for the physical CPU address to
|
||||
translate to and the sixth and seventh cells are as described for the
|
||||
#size-cells property above.
|
||||
- Entries setup the mapping for the standard I/O, memory and
|
||||
prefetchable PCI regions. The first cell determines the type of region
|
||||
that is setup:
|
||||
- 0x81000000: I/O memory region
|
||||
- 0x82000000: non-prefetchable memory region
|
||||
- 0xc2000000: prefetchable memory region
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- #interrupt-cells: Size representation for interrupts (must be 1)
|
||||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
|
||||
EP mode:
|
||||
In Tegra194, Only controllers C0, C4 & C5 support EP mode.
|
||||
- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
|
||||
- reg-names: Must include the following entries:
|
||||
"addr_space": Used to map remote RC address space
|
||||
- reset-gpios: Must contain a phandle to a GPIO controller followed by
|
||||
GPIO that is being used as PERST input signal. Please refer to pci.txt
|
||||
document.
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names: A list of pinctrl state names.
|
||||
It is mandatory for C5 controller and optional for other controllers.
|
||||
- "default": Configures PCIe I/O for proper operation.
|
||||
- pinctrl-0: phandle for the 'default' state of pin configuration.
|
||||
It is mandatory for C5 controller and optional for other controllers.
|
||||
- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
|
||||
- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
|
||||
improve performance when a platform is designed in such a way that it
|
||||
satisfies at least one of the following conditions thereby enabling root
|
||||
port to exchange optimum number of FC (Flow Control) credits with
|
||||
downstream devices
|
||||
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
|
||||
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
|
||||
a) speed is Gen-2 and MPS is 256B
|
||||
b) speed is >= Gen-3 with any MPS
|
||||
- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
|
||||
to be specified in microseconds
|
||||
- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
|
||||
specified in microseconds
|
||||
|
||||
RC mode:
|
||||
- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
|
||||
if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
|
||||
in p2972-0000 platform).
|
||||
- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
|
||||
if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
|
||||
in p2972-0000 platform).
|
||||
|
||||
EP mode:
|
||||
- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
|
||||
followed by GPIO that is being used to enable REFCLK to controller from host
|
||||
|
||||
NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
|
||||
operate in the endpoint mode because of the way the platform is designed.
|
||||
|
||||
Examples:
|
||||
=========
|
||||
|
||||
Tegra194 RC mode:
|
||||
-----------------
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
|
||||
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
vpcie12v-supply = <&vdd_12v_pcie>;
|
||||
|
||||
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
|
||||
<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
Tegra194 EP mode:
|
||||
-----------------
|
||||
|
||||
pcie-ep@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
|
||||
0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
num-lanes = <8>;
|
||||
num-ib-windows = <2>;
|
||||
num-ob-windows = <8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Vidya Sagar <vidyas@nvidia.com>
|
||||
|
||||
description: |
|
||||
This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
|
||||
inherits all the common properties defined in snps,dw-pcie.yaml. Some of
|
||||
the controller instances are dual mode where in they can work either in
|
||||
Root Port mode or Endpoint mode but one at a time.
|
||||
|
||||
See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
|
||||
tree bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie
|
||||
- nvidia,tegra234-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: controller's application logic registers
|
||||
- description: configuration registers
|
||||
- description: iATU and DMA registers. This is where the iATU (internal
|
||||
Address Translation Unit) registers of the PCIe core are made
|
||||
available for software access.
|
||||
- description: aperture where the Root Port's own configuration
|
||||
registers are available.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: appl
|
||||
- const: config
|
||||
- const: atu_dma
|
||||
- const: dbi
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: controller interrupt
|
||||
- description: MSI interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: intr
|
||||
- const: msi
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB bus interface reset
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: core
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: p2u-0
|
||||
- const: p2u-1
|
||||
- const: p2u-2
|
||||
- const: p2u-3
|
||||
- const: p2u-4
|
||||
- const: p2u-5
|
||||
- const: p2u-6
|
||||
- const: p2u-7
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
A phandle to the node that controls power to the respective PCIe
|
||||
controller and a specifier name for the PCIe controller.
|
||||
|
||||
Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
|
||||
Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: |
|
||||
Must contain a pair of phandles to BPMP controller node followed by
|
||||
controller ID. Following are the controller IDs for each controller:
|
||||
|
||||
Tegra194
|
||||
|
||||
0: C0
|
||||
1: C1
|
||||
2: C2
|
||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
|
||||
Tegra234
|
||||
|
||||
0 : C0
|
||||
1 : C1
|
||||
2 : C2
|
||||
3 : C3
|
||||
4 : C4
|
||||
5 : C5
|
||||
6 : C6
|
||||
7 : C7
|
||||
8 : C8
|
||||
9 : C9
|
||||
10: C10
|
||||
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to BPMP controller node
|
||||
- description: PCIe controller ID
|
||||
maximum: 10
|
||||
|
||||
nvidia,update-fc-fixup:
|
||||
description: |
|
||||
This is a boolean property and needs to be present to improve performance
|
||||
when a platform is designed in such a way that it satisfies at least one
|
||||
of the following conditions thereby enabling Root Port to exchange
|
||||
optimum number of FC (Flow Control) credits with downstream devices:
|
||||
|
||||
NOTE: This is applicable only for Tegra194.
|
||||
|
||||
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
|
||||
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
|
||||
a) speed is Gen-2 and MPS is 256B
|
||||
b) speed is >= Gen-3 with any MPS
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,aspm-cmrt-us:
|
||||
description: Common Mode Restore Time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
|
||||
nvidia,aspm-pwr-on-t-us:
|
||||
description: Power On time for proper operation of ASPM to be specified in
|
||||
microseconds
|
||||
|
||||
nvidia,aspm-l0s-entrance-latency-us:
|
||||
description: ASPM L0s entrance latency to be specified in microseconds
|
||||
|
||||
vddio-pex-ctl-supply:
|
||||
description: A phandle to the regulator supply for PCIe side band signals.
|
||||
|
||||
vpcie3v3-supply:
|
||||
description: A phandle to the regulator node that supplies 3.3V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
vpcie12v-supply:
|
||||
description: A phandle to the regulator node that supplies 12V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
nvidia,enable-srns:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to operate in SRNS (Separate Reference Clocks with No
|
||||
Spread-Spectrum Clocking). NOTE: This is applicable only for
|
||||
Tegra234.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,enable-ext-refclk:
|
||||
description: |
|
||||
This boolean property needs to be present if the controller is
|
||||
configured to use the reference clocking coming in from an external
|
||||
clock source instead of using the internal clock source.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- vddio-pex-ctl-supply
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
|
||||
<0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
|
||||
<0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
vpcie12v-supply = <&vdd_12v_pcie>;
|
||||
|
||||
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
|
||||
<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie@14160000 {
|
||||
compatible = "nvidia,tegra234-pcie";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <4>;
|
||||
|
||||
clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
|
||||
<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 4>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
|
||||
<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
|
||||
<0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
|
||||
|
||||
vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
|
||||
|
||||
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
|
||||
<&p2u_hsio_7>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
};
|
||||
|
|
@ -34,8 +34,8 @@ properties:
|
|||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
|
||||
ulreg, smu, mpu, apb, phy ]
|
||||
enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
|
||||
parf, cfg, link, ulreg, smu, mpu, apb, phy ]
|
||||
|
||||
num-lanes:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -161,6 +161,38 @@
|
|||
|
||||
#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
|
||||
|
||||
/*
|
||||
* iATU Unroll-specific register definitions
|
||||
* From 4.80 core version the address translation will be made by unroll
|
||||
*/
|
||||
#define PCIE_ATU_UNR_REGION_CTRL1 0x00
|
||||
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
|
||||
#define PCIE_ATU_UNR_LOWER_BASE 0x08
|
||||
#define PCIE_ATU_UNR_UPPER_BASE 0x0C
|
||||
#define PCIE_ATU_UNR_LOWER_LIMIT 0x10
|
||||
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
|
||||
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
|
||||
#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
|
||||
|
||||
/*
|
||||
* RAS-DES register definitions
|
||||
*/
|
||||
#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8
|
||||
#define EVENT_COUNTER_ALL_CLEAR 0x3
|
||||
#define EVENT_COUNTER_ENABLE_ALL 0x7
|
||||
#define EVENT_COUNTER_ENABLE_SHIFT 2
|
||||
#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
|
||||
#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
|
||||
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
|
||||
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
|
||||
#define EVENT_COUNTER_EVENT_L1 0x5
|
||||
#define EVENT_COUNTER_EVENT_L1_1 0x7
|
||||
#define EVENT_COUNTER_EVENT_L1_2 0x8
|
||||
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
|
||||
#define EVENT_COUNTER_GROUP_5 0x5
|
||||
|
||||
#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc
|
||||
|
||||
/*
|
||||
* The default address offset between dbi_base and atu_base. Root controller
|
||||
* drivers are not required to initialize atu_base if the offset matches this
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -2709,10 +2709,10 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
|
|||
nvenet_msi_disable);
|
||||
|
||||
/*
|
||||
* PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
|
||||
* then the device can't use INTx interrupts. Tegra's PCIe root ports don't
|
||||
* generate MSI interrupts for PME and AER events instead only INTx interrupts
|
||||
* are generated. Though Tegra's PCIe root ports can generate MSI interrupts
|
||||
* PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
|
||||
* can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
|
||||
* interrupts for PME and AER events; instead only INTx interrupts are
|
||||
* generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
|
||||
* for other events, since PCIe specification doesn't support using a mix of
|
||||
* INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
|
||||
* service drivers registering their respective ISRs for MSIs.
|
||||
|
|
@ -2760,6 +2760,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
|
|||
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
|
||||
PCI_CLASS_BRIDGE_PCI, 8,
|
||||
pci_quirk_nvidia_tegra_disable_rp_msi);
|
||||
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
|
||||
PCI_CLASS_BRIDGE_PCI, 8,
|
||||
pci_quirk_nvidia_tegra_disable_rp_msi);
|
||||
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
|
||||
PCI_CLASS_BRIDGE_PCI, 8,
|
||||
pci_quirk_nvidia_tegra_disable_rp_msi);
|
||||
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
|
||||
PCI_CLASS_BRIDGE_PCI, 8,
|
||||
pci_quirk_nvidia_tegra_disable_rp_msi);
|
||||
|
||||
/*
|
||||
* Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
|
||||
|
|
|
|||
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