MIPS: Add 64-bit HTW fields
Add field definitions for some of the 64-bit specific Hardware page Table Walker (HTW) register fields in PWSize and PWCtl, in preparation for fixing the 64-bit HTW configuration. Also print these fields out along with the others in print_htw_config(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13363/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -729,6 +729,8 @@
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#define MIPS_PWFIELD_PTEI_SHIFT 0
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#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
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#define MIPS_PWSIZE_PS_SHIFT 30
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#define MIPS_PWSIZE_PS_MASK 0x40000000
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#define MIPS_PWSIZE_GDW_SHIFT 24
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#define MIPS_PWSIZE_GDW_MASK 0x3f000000
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#define MIPS_PWSIZE_UDW_SHIFT 18
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@ -742,6 +744,12 @@
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#define MIPS_PWCTL_PWEN_SHIFT 31
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#define MIPS_PWCTL_PWEN_MASK 0x80000000
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#define MIPS_PWCTL_XK_SHIFT 28
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#define MIPS_PWCTL_XK_MASK 0x10000000
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#define MIPS_PWCTL_XS_SHIFT 27
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#define MIPS_PWCTL_XS_MASK 0x08000000
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#define MIPS_PWCTL_XU_SHIFT 26
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#define MIPS_PWCTL_XU_MASK 0x04000000
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#define MIPS_PWCTL_DPH_SHIFT 7
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#define MIPS_PWCTL_DPH_MASK 0x00000080
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#define MIPS_PWCTL_HUGEPG_SHIFT 6
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@ -2361,8 +2361,9 @@ static void print_htw_config(void)
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(config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
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config = read_c0_pwsize();
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pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
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pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
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field, config,
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(config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
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(config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
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(config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
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(config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
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@ -2370,9 +2371,12 @@ static void print_htw_config(void)
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(config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
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pwctl = read_c0_pwctl();
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pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
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pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
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pwctl,
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(pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
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(pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
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(pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
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(pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
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(pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
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(pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
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(pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
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