qed: Add support for Energy efficient ethernet.
The patch adds required driver support for reading/configuring the Energy Efficient Ethernet (EEE) parameters. Signed-off-by: Sudarsana Reddy Kalluru <sudarsana.kalluru@cavium.com> Signed-off-by: Yuval Mintz <yuval.mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sudarsana Reddy Kalluru
David S. Miller
Родитель
3f2a2b8b7a
Коммит
645874e580
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@ -1684,6 +1684,8 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
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"Load request was sent. Load code: 0x%x\n",
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load_code);
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qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
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qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
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p_hwfn->first_on_engine = (load_code ==
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@ -2472,6 +2474,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
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u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
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struct qed_mcp_link_capabilities *p_caps;
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struct qed_mcp_link_params *link;
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/* Read global nvm_cfg address */
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@ -2534,6 +2537,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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/* Read default link configuration */
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link = &p_hwfn->mcp_info->link_input;
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p_caps = &p_hwfn->mcp_info->link_capabilities;
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port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
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link_temp = qed_rd(p_hwfn, p_ptt,
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@ -2588,10 +2592,45 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
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link->loopback_mode = 0;
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DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
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"Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
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link->speed.forced_speed, link->speed.advertised_speeds,
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link->speed.autoneg, link->pause.autoneg);
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if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
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link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
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offsetof(struct nvm_cfg1_port, ext_phy));
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link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
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link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
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p_caps->default_eee = QED_MCP_EEE_ENABLED;
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link->eee.enable = true;
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switch (link_temp) {
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case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
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p_caps->default_eee = QED_MCP_EEE_DISABLED;
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link->eee.enable = false;
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break;
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case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
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p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
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break;
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case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
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p_caps->eee_lpi_timer =
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EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
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break;
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case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
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p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
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break;
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}
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link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
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link->eee.tx_lpi_enable = link->eee.enable;
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link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
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} else {
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p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
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}
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DP_VERBOSE(p_hwfn,
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NETIF_MSG_LINK,
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"Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
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link->speed.forced_speed,
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link->speed.advertised_speeds,
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link->speed.autoneg,
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link->pause.autoneg,
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p_caps->default_eee, p_caps->eee_lpi_timer);
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/* Read Multi-function information from shmem */
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addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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@ -2751,6 +2790,27 @@ static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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qed_hw_info_port_num_ah(p_hwfn, p_ptt);
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}
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static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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struct qed_mcp_link_capabilities *p_caps;
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u32 eee_status;
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p_caps = &p_hwfn->mcp_info->link_capabilities;
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if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
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return;
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p_caps->eee_speed_caps = 0;
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eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
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offsetof(struct public_port, eee_status));
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eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
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EEE_SUPPORTED_SPEED_OFFSET;
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if (eee_status & EEE_1G_SUPPORTED)
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p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
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if (eee_status & EEE_10G_ADV)
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p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
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}
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static int
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qed_get_hw_info(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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@ -2767,6 +2827,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
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qed_hw_info_port_num(p_hwfn, p_ptt);
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qed_mcp_get_capabilities(p_hwfn, p_ptt);
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qed_hw_get_nvm_info(p_hwfn, p_ptt);
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rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
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@ -2785,6 +2847,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
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p_hwfn->mcp_info->func_info.ovlan;
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qed_mcp_cmd_port_init(p_hwfn, p_ptt);
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qed_get_eee_caps(p_hwfn, p_ptt);
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}
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if (qed_mcp_is_init(p_hwfn)) {
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@ -10825,6 +10825,17 @@ struct eth_phy_cfg {
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#define ETH_LOOPBACK_EXT (3)
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#define ETH_LOOPBACK_MAC (4)
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u32 eee_cfg;
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#define EEE_CFG_EEE_ENABLED BIT(0)
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#define EEE_CFG_TX_LPI BIT(1)
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#define EEE_CFG_ADV_SPEED_1G BIT(2)
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#define EEE_CFG_ADV_SPEED_10G BIT(3)
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#define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
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#define EEE_TX_TIMER_USEC_OFFSET 4
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#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
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#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
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#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
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u32 feature_config_flags;
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#define ETH_EEE_MODE_ADV_LPI (1 << 0)
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};
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@ -11242,6 +11253,25 @@ struct public_port {
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u32 wol_pkt_len;
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u32 wol_pkt_details;
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struct dcb_dscp_map dcb_dscp_map;
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u32 eee_status;
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#define EEE_ACTIVE_BIT BIT(0)
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#define EEE_LD_ADV_STATUS_MASK 0x000000f0
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#define EEE_LD_ADV_STATUS_OFFSET 4
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#define EEE_1G_ADV BIT(1)
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#define EEE_10G_ADV BIT(2)
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#define EEE_LP_ADV_STATUS_MASK 0x00000f00
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#define EEE_LP_ADV_STATUS_OFFSET 8
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#define EEE_SUPPORTED_SPEED_MASK 0x0000f000
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#define EEE_SUPPORTED_SPEED_OFFSET 12
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#define EEE_1G_SUPPORTED BIT(1)
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#define EEE_10G_SUPPORTED BIT(2)
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u32 eee_remote;
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#define EEE_REMOTE_TW_TX_MASK 0x0000ffff
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#define EEE_REMOTE_TW_TX_OFFSET 0
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#define EEE_REMOTE_TW_RX_MASK 0xffff0000
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#define EEE_REMOTE_TW_RX_OFFSET 16
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};
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struct public_func {
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@ -11570,6 +11600,9 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
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#define DRV_MSG_CODE_OS_WOL 0x002e0000
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#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
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#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
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#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
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u32 drv_mb_param;
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@ -11653,6 +11686,10 @@ struct public_drv_mb {
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#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
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#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
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#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
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#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
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#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
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u32 fw_mb_header;
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#define FW_MSG_CODE_MASK 0xffff0000
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#define FW_MSG_CODE_UNSUPPORTED 0x00000000
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@ -11696,6 +11733,9 @@ struct public_drv_mb {
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#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
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#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
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/* get MFW feature support response */
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#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
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#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
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u32 drv_pulse_mb;
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@ -11891,7 +11931,16 @@ struct nvm_cfg1_port {
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#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
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u32 phy_cfg;
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u32 mgmt_traffic;
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u32 ext_phy;
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/* EEE power saving mode */
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
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u32 mba_cfg1;
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u32 mba_cfg2;
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u32 vf_cfg;
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@ -1297,6 +1297,10 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
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}
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}
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if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
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memcpy(&link_params->eee, ¶ms->eee,
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sizeof(link_params->eee));
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rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
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qed_ptt_release(hwfn, ptt);
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@ -1483,6 +1487,21 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
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if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
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link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
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if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
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if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
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if_link->eee_supported = false;
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} else {
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if_link->eee_supported = true;
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if_link->eee_active = link.eee_active;
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if_link->sup_caps = link_caps.eee_speed_caps;
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/* MFW clears adv_caps on eee disable; use configured value */
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if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
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params.eee.adv_caps;
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if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
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if_link->eee.enable = params.eee.enable;
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if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
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if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
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}
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}
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static void qed_get_current_link(struct qed_dev *cdev,
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@ -1097,6 +1097,31 @@ static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
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DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
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}
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static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_mcp_link_state *p_link)
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{
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u32 eee_status, val;
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p_link->eee_adv_caps = 0;
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p_link->eee_lp_adv_caps = 0;
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eee_status = qed_rd(p_hwfn,
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p_ptt,
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p_hwfn->mcp_info->port_addr +
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offsetof(struct public_port, eee_status));
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p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
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val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
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if (val & EEE_1G_ADV)
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p_link->eee_adv_caps |= QED_EEE_1G_ADV;
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if (val & EEE_10G_ADV)
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p_link->eee_adv_caps |= QED_EEE_10G_ADV;
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val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
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if (val & EEE_1G_ADV)
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p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
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if (val & EEE_10G_ADV)
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p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
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}
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static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, bool b_reset)
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{
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@ -1228,6 +1253,9 @@ static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
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p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
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if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
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qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
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qed_link_update(p_hwfn);
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out:
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spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
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@ -1251,6 +1279,19 @@ int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
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phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
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phy_cfg.adv_speed = params->speed.advertised_speeds;
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phy_cfg.loopback_mode = params->loopback_mode;
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if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
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if (params->eee.enable)
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phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
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if (params->eee.tx_lpi_enable)
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phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
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if (params->eee.adv_caps & QED_EEE_1G_ADV)
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phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
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if (params->eee.adv_caps & QED_EEE_10G_ADV)
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phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
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phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
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EEE_TX_TIMER_USEC_OFFSET) &
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EEE_TX_TIMER_USEC_MASK;
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}
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p_hwfn->b_drv_link_init = b_up;
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@ -2822,3 +2863,28 @@ void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
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p_unlock->resource = resource;
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}
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}
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int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 mcp_resp;
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int rc;
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rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
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0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
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if (!rc)
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DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
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"MFW supported features: %08x\n",
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p_hwfn->mcp_info->capabilities);
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return rc;
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}
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int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 mcp_resp, mcp_param, features;
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features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
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return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
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features, &mcp_resp, &mcp_param);
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}
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@ -53,15 +53,25 @@ struct qed_mcp_link_pause_params {
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bool forced_tx;
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};
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|
||||
enum qed_mcp_eee_mode {
|
||||
QED_MCP_EEE_DISABLED,
|
||||
QED_MCP_EEE_ENABLED,
|
||||
QED_MCP_EEE_UNSUPPORTED
|
||||
};
|
||||
|
||||
struct qed_mcp_link_params {
|
||||
struct qed_mcp_link_speed_params speed;
|
||||
struct qed_mcp_link_pause_params pause;
|
||||
u32 loopback_mode;
|
||||
struct qed_mcp_link_speed_params speed;
|
||||
struct qed_mcp_link_pause_params pause;
|
||||
u32 loopback_mode;
|
||||
struct qed_link_eee_params eee;
|
||||
};
|
||||
|
||||
struct qed_mcp_link_capabilities {
|
||||
u32 speed_capabilities;
|
||||
bool default_speed_autoneg;
|
||||
enum qed_mcp_eee_mode default_eee;
|
||||
u32 eee_lpi_timer;
|
||||
u8 eee_speed_caps;
|
||||
};
|
||||
|
||||
struct qed_mcp_link_state {
|
||||
|
|
@ -102,6 +112,9 @@ struct qed_mcp_link_state {
|
|||
u8 partner_adv_pause;
|
||||
|
||||
bool sfp_tx_fault;
|
||||
bool eee_active;
|
||||
u8 eee_adv_caps;
|
||||
u8 eee_lp_adv_caps;
|
||||
};
|
||||
|
||||
struct qed_mcp_function_info {
|
||||
|
|
@ -546,6 +559,9 @@ struct qed_mcp_info {
|
|||
u8 *mfw_mb_shadow;
|
||||
u16 mfw_mb_length;
|
||||
u32 mcp_hist;
|
||||
|
||||
/* Capabilties negotiated with the MFW */
|
||||
u32 capabilities;
|
||||
};
|
||||
|
||||
struct qed_mcp_mb_params {
|
||||
|
|
@ -925,5 +941,20 @@ void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
|
|||
struct qed_resc_unlock_params *p_unlock,
|
||||
enum qed_resc_lock
|
||||
resource, bool b_is_permanent);
|
||||
/**
|
||||
* @brief Learn of supported MFW features; To be done during early init
|
||||
*
|
||||
* @param p_hwfn
|
||||
* @param p_ptt
|
||||
*/
|
||||
int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
||||
|
||||
/**
|
||||
* @brief Inform MFW of set of features supported by driver. Should be done
|
||||
* inside the content of the LOAD_REQ.
|
||||
*
|
||||
* @param p_hwfn
|
||||
* @param p_ptt
|
||||
*/
|
||||
int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -161,6 +161,18 @@ enum qed_nvm_images {
|
|||
QED_NVM_IMAGE_FCOE_CFG,
|
||||
};
|
||||
|
||||
struct qed_link_eee_params {
|
||||
u32 tx_lpi_timer;
|
||||
#define QED_EEE_1G_ADV BIT(0)
|
||||
#define QED_EEE_10G_ADV BIT(1)
|
||||
|
||||
/* Capabilities are represented using QED_EEE_*_ADV values */
|
||||
u8 adv_caps;
|
||||
u8 lp_adv_caps;
|
||||
bool enable;
|
||||
bool tx_lpi_enable;
|
||||
};
|
||||
|
||||
enum qed_led_mode {
|
||||
QED_LED_MODE_OFF,
|
||||
QED_LED_MODE_ON,
|
||||
|
|
@ -408,6 +420,7 @@ struct qed_link_params {
|
|||
#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
|
||||
#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
|
||||
#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
|
||||
#define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
|
||||
u32 override_flags;
|
||||
bool autoneg;
|
||||
u32 adv_speeds;
|
||||
|
|
@ -422,6 +435,7 @@ struct qed_link_params {
|
|||
#define QED_LINK_LOOPBACK_EXT BIT(3)
|
||||
#define QED_LINK_LOOPBACK_MAC BIT(4)
|
||||
u32 loopback_mode;
|
||||
struct qed_link_eee_params eee;
|
||||
};
|
||||
|
||||
struct qed_link_output {
|
||||
|
|
@ -437,6 +451,12 @@ struct qed_link_output {
|
|||
u8 port; /* In PORT defs */
|
||||
bool autoneg;
|
||||
u32 pause_config;
|
||||
|
||||
/* EEE - capability & param */
|
||||
bool eee_supported;
|
||||
bool eee_active;
|
||||
u8 sup_caps;
|
||||
struct qed_link_eee_params eee;
|
||||
};
|
||||
|
||||
struct qed_probe_params {
|
||||
|
|
|
|||
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