PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
ThunderX pass1.x requires to emulate the EA headers for on-chip devices hence it has to use custom pci_thunder_ecam_ops for accessing PCI config space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it can be applied while probing ACPI based PCI host controller. ThunderX pass1.x is using the same way for accessing off-chip devices (so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries too. Quirk is considered for ThunderX silicon pass1.x only which is identified via MCFG revision 2. ThunderX pass 1.x requires the following accessors: NUMA node 0 PCI segments 0- 3: pci_thunder_ecam_ops (MCFG quirk) NUMA node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk) [bhelgaas: change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_ECAM] Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -93,6 +93,21 @@ static struct mcfg_fixup mcfg_quirks[] = {
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/* SoC pass2.x */
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THUNDER_PEM_QUIRK(1, 0),
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THUNDER_PEM_QUIRK(1, 1),
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#define THUNDER_ECAM_QUIRK(rev, seg) \
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{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
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&pci_thunder_ecam_ops }
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/* SoC pass1.x */
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THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
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THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
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THUNDER_ECAM_QUIRK(2, 0),
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THUNDER_ECAM_QUIRK(2, 1),
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THUNDER_ECAM_QUIRK(2, 2),
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THUNDER_ECAM_QUIRK(2, 3),
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THUNDER_ECAM_QUIRK(2, 10),
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THUNDER_ECAM_QUIRK(2, 11),
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THUNDER_ECAM_QUIRK(2, 12),
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THUNDER_ECAM_QUIRK(2, 13),
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};
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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@ -248,7 +248,8 @@ config PCI_HOST_THUNDER_PEM
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config PCI_HOST_THUNDER_ECAM
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bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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depends on OF && ARM64
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depends on ARM64
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCI_HOST_COMMON
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help
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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@ -27,7 +27,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_ARM64) += pcie-hisi.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
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obj-$(CONFIG_ARM64) += pci-thunder-pem.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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@ -14,6 +14,8 @@
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static void set_val(u32 v, int where, int size, u32 *val)
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{
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int shift = (where & 3) * 8;
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@ -346,7 +348,7 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static struct pci_ecam_ops pci_thunder_ecam_ops = {
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struct pci_ecam_ops pci_thunder_ecam_ops = {
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.bus_shift = 20,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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@ -355,6 +357,8 @@ static struct pci_ecam_ops pci_thunder_ecam_ops = {
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}
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};
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#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
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static const struct of_device_id thunder_ecam_of_match[] = {
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{ .compatible = "cavium,pci-host-thunder-ecam" },
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{ },
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@ -373,3 +377,6 @@ static struct platform_driver thunder_ecam_driver = {
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.probe = thunder_ecam_probe,
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};
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builtin_platform_driver(thunder_ecam_driver);
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#endif
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#endif
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@ -62,7 +62,8 @@ extern struct pci_ecam_ops pci_generic_ecam_ops;
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 2.x */
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extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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#endif
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#ifdef CONFIG_PCI_HOST_GENERIC
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