drm/amd/display: Add DCN3.1 HWSEQ
Add DCN3.1 specific hardware sequence programming - extending off of our existing DCN3/DCN2 support. Extend stream hardware sequencing to include new DCCG programming. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
Alex Deucher
Родитель
fcffbcf48d
Коммит
64b1d0e8d5
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@ -444,6 +444,7 @@ struct dc_bw_validation_profile {
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union mem_low_power_enable_options {
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struct {
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bool vga: 1;
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bool i2c: 1;
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bool dmcu: 1;
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bool dscl: 1;
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@ -585,6 +586,9 @@ struct dc_phy_addr_space_config {
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uint64_t page_table_start_addr;
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uint64_t page_table_end_addr;
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uint64_t page_table_base_addr;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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bool base_addr_is_mc_addr;
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#endif
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} gart_config;
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bool valid;
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@ -635,6 +635,7 @@ struct dce_hwseq_registers {
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uint32_t HPO_TOP_CLOCK_CONTROL;
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uint32_t ODM_MEM_PWR_CTRL3;
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uint32_t DMU_MEM_PWR_CNTL;
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uint32_t MMHUBBUB_MEM_PWR_CNTL;
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};
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/* set field name */
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#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
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@ -875,7 +876,8 @@ struct dce_hwseq_registers {
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HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
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HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
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HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
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HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh)
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HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
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HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
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#define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
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@ -1092,7 +1094,8 @@ struct dce_hwseq_registers {
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type AZALIA_AUDIO_DTO_MODULE; \
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type ODM_MEM_UNASSIGNED_PWR_MODE; \
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type ODM_MEM_VBLANK_PWR_MODE; \
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type DMCU_ERAM_MEM_PWR_FORCE;
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type DMCU_ERAM_MEM_PWR_FORCE; \
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type VGA_MEM_PWR_FORCE;
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#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
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type HPO_HDMISTREAMCLK_GATE_DIS;
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@ -1103,11 +1106,22 @@ struct dce_hwseq_registers {
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type PANEL_DIGON_OVRD;\
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type PANEL_PWRSEQ_TARGET_STATE_R;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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#define HWSEQ_DCN31_REG_FIELD_LIST(type) \
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type DOMAIN_POWER_FORCEON;\
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type DOMAIN_POWER_GATE;\
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type DOMAIN_PGFSM_PWR_STATUS;\
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type HPO_HDMISTREAMCLK_G_GATE_DIS;
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#endif
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struct dce_hwseq_shift {
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HWSEQ_REG_FIELD_LIST(uint8_t)
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HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
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HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
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HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
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#endif
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};
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struct dce_hwseq_mask {
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@ -1115,6 +1129,9 @@ struct dce_hwseq_mask {
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HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
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HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
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HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
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#endif
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};
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@ -49,6 +49,9 @@
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#include "link_encoder.h"
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#include "link_hwss.h"
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#include "dc_link_dp.h"
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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#include "dccg.h"
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#endif
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#include "clock_source.h"
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#include "clk_mgr.h"
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#include "abm.h"
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@ -2124,11 +2127,31 @@ static void dce110_setup_audio_dto(
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build_audio_output(context, pipe_ctx, &audio_output);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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/* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
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if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
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/* disable audio DTBCLK DTO */
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dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
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dc->res_pool->dccg, 0);
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pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
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pipe_ctx->stream_res.audio,
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pipe_ctx->stream->signal,
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&audio_output.crtc_info,
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&audio_output.pll_info);
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} else
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pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
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pipe_ctx->stream_res.audio,
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pipe_ctx->stream->signal,
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&audio_output.crtc_info,
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&audio_output.pll_info);
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#else
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pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
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pipe_ctx->stream_res.audio,
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pipe_ctx->stream->signal,
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&audio_output.crtc_info,
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&audio_output.pll_info);
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#endif
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break;
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}
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}
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@ -0,0 +1,598 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dm_helpers.h"
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#include "core_types.h"
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#include "resource.h"
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#include "dccg.h"
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#include "dce/dce_hwseq.h"
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#include "clk_mgr.h"
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#include "reg_helper.h"
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#include "abm.h"
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#include "clk_mgr.h"
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#include "hubp.h"
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#include "dchubbub.h"
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#include "timing_generator.h"
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#include "opp.h"
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#include "ipp.h"
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#include "mpc.h"
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#include "mcif_wb.h"
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#include "dc_dmub_srv.h"
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#include "dcn31_hwseq.h"
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#include "link_hwss.h"
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#include "dpcd_defs.h"
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#include "dce/dmub_outbox.h"
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#include "dc_link_dp.h"
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#define DC_LOGGER_INIT(logger)
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#define CTX \
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hws->ctx
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#define REG(reg)\
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hws->regs->reg
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#define DC_LOGGER \
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dc->ctx->logger
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#undef FN
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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void dcn31_init_hw(struct dc *dc)
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{
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struct abm **abms = dc->res_pool->multiple_abms;
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struct dce_hwseq *hws = dc->hwseq;
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struct dc_bios *dcb = dc->ctx->dc_bios;
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struct resource_pool *res_pool = dc->res_pool;
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uint32_t backlight = MAX_BACKLIGHT_LEVEL;
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int i, j;
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int edp_num;
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if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
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dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
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// Initialize the dccg
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if (res_pool->dccg->funcs->dccg_init)
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res_pool->dccg->funcs->dccg_init(res_pool->dccg);
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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REG_WRITE(REFCLK_CNTL, 0);
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REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
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REG_WRITE(DIO_MEM_PWR_CTRL, 0);
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if (!dc->debug.disable_clock_gate) {
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/* enable all DCN clock gating */
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REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
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REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
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REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
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}
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//Enable ability to power gate / don't force power on permanently
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if (hws->funcs.enable_power_gating_plane)
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hws->funcs.enable_power_gating_plane(hws, true);
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return;
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}
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if (!dcb->funcs->is_accelerated_mode(dcb)) {
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hws->funcs.bios_golden_init(dc);
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hws->funcs.disable_vga(dc->hwseq);
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}
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if (dc->debug.enable_mem_low_power.bits.dmcu) {
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// Force ERAM to shutdown if DMCU is not enabled
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if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
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REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
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}
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}
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// Set default OPTC memory power states
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if (dc->debug.enable_mem_low_power.bits.optc) {
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// Shutdown when unassigned and light sleep in VBLANK
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REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
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}
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if (dc->debug.enable_mem_low_power.bits.vga) {
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// Power down VGA memory
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REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
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}
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if (dc->ctx->dc_bios->fw_info_valid) {
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res_pool->ref_clocks.xtalin_clock_inKhz =
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dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
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if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (res_pool->dccg && res_pool->hubbub) {
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(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
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dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
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&res_pool->ref_clocks.dccg_ref_clock_inKhz);
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(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
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res_pool->ref_clocks.dccg_ref_clock_inKhz,
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&res_pool->ref_clocks.dchub_ref_clock_inKhz);
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} else {
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// Not all ASICs have DCCG sw component
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res_pool->ref_clocks.dccg_ref_clock_inKhz =
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res_pool->ref_clocks.xtalin_clock_inKhz;
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res_pool->ref_clocks.dchub_ref_clock_inKhz =
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res_pool->ref_clocks.xtalin_clock_inKhz;
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}
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}
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} else
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ASSERT_CRITICAL(false);
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for (i = 0; i < dc->link_count; i++) {
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/* Power up AND update implementation according to the
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* required signal (which may be different from the
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* default signal on connector).
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*/
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struct dc_link *link = dc->links[i];
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link->link_enc->funcs->hw_init(link->link_enc);
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/* Check for enabled DIG to identify enabled display */
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if (link->link_enc->funcs->is_dig_enabled &&
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link->link_enc->funcs->is_dig_enabled(link->link_enc))
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link->link_status.link_active = true;
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}
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/* Power gate DSCs */
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for (i = 0; i < res_pool->res_cap->num_dsc; i++)
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if (hws->funcs.dsc_pg_control != NULL)
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hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
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/* we want to turn off all dp displays before doing detection */
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if (dc->config.power_down_display_on_boot) {
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uint8_t dpcd_power_state = '\0';
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enum dc_status status = DC_ERROR_UNEXPECTED;
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for (i = 0; i < dc->link_count; i++) {
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if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
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continue;
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/* if any of the displays are lit up turn them off */
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status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
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&dpcd_power_state, sizeof(dpcd_power_state));
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if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
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/* blank dp stream before power off receiver*/
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if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
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unsigned int fe;
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fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
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dc->links[i]->link_enc);
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if (fe == ENGINE_ID_UNKNOWN)
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continue;
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for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
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if (fe == dc->res_pool->stream_enc[j]->id) {
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dc->res_pool->stream_enc[j]->funcs->dp_blank(
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dc->res_pool->stream_enc[j]);
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break;
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}
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}
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}
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dp_receiver_power_ctrl(dc->links[i], false);
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}
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}
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}
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/* If taking control over from VBIOS, we may want to optimize our first
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* mode set, so we need to skip powering down pipes until we know which
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* pipes we want to use.
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* Otherwise, if taking control is not possible, we need to power
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* everything down.
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*/
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if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
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hws->funcs.init_pipes(dc, dc->current_state);
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if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
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dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
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!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
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}
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/* In headless boot cases, DIG may be turned
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* on which causes HW/SW discrepancies.
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* To avoid this, power down hardware on boot
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* if DIG is turned on and seamless boot not enabled
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*/
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if (dc->config.power_down_display_on_boot) {
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struct dc_link *edp_links[MAX_NUM_EDP];
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struct dc_link *edp_link;
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get_edp_links(dc, edp_links, &edp_num);
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if (edp_num) {
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for (i = 0; i < edp_num; i++) {
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edp_link = edp_links[i];
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if (edp_link->link_enc->funcs->is_dig_enabled &&
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edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
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dc->hwss.edp_backlight_control &&
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dc->hwss.power_down &&
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dc->hwss.edp_power_control) {
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dc->hwss.edp_backlight_control(edp_link, false);
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dc->hwss.power_down(dc);
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dc->hwss.edp_power_control(edp_link, false);
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}
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}
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} else {
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for (i = 0; i < dc->link_count; i++) {
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struct dc_link *link = dc->links[i];
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if (link->link_enc->funcs->is_dig_enabled &&
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link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
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dc->hwss.power_down) {
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dc->hwss.power_down(dc);
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break;
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}
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}
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}
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}
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for (i = 0; i < res_pool->audio_count; i++) {
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struct audio *audio = res_pool->audios[i];
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audio->funcs->hw_init(audio);
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}
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for (i = 0; i < dc->link_count; i++) {
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struct dc_link *link = dc->links[i];
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if (link->panel_cntl)
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backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
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}
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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if (abms[i] != NULL)
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abms[i]->funcs->abm_init(abms[i], backlight);
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}
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|
||||
/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
|
||||
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
|
||||
|
||||
if (!dc->debug.disable_clock_gate) {
|
||||
/* enable all DCN clock gating */
|
||||
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
|
||||
|
||||
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
|
||||
|
||||
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
|
||||
}
|
||||
if (hws->funcs.enable_power_gating_plane)
|
||||
hws->funcs.enable_power_gating_plane(dc->hwseq, true);
|
||||
|
||||
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
|
||||
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
|
||||
|
||||
if (dc->clk_mgr->funcs->notify_wm_ranges)
|
||||
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
|
||||
|
||||
if (dc->clk_mgr->funcs->set_hard_max_memclk)
|
||||
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
|
||||
|
||||
if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
|
||||
dc->res_pool->hubbub->funcs->force_pstate_change_control(
|
||||
dc->res_pool->hubbub, false, false);
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
|
||||
if (dc->res_pool->hubbub->funcs->init_crb)
|
||||
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
|
||||
#endif
|
||||
}
|
||||
|
||||
void dcn31_dsc_pg_control(
|
||||
struct dce_hwseq *hws,
|
||||
unsigned int dsc_inst,
|
||||
bool power_on)
|
||||
{
|
||||
uint32_t power_gate = power_on ? 0 : 1;
|
||||
uint32_t pwr_status = power_on ? 0 : 2;
|
||||
uint32_t org_ip_request_cntl = 0;
|
||||
|
||||
if (hws->ctx->dc->debug.disable_dsc_power_gate)
|
||||
return;
|
||||
|
||||
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
|
||||
if (org_ip_request_cntl == 0)
|
||||
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
|
||||
|
||||
switch (dsc_inst) {
|
||||
case 0: /* DSC0 */
|
||||
REG_UPDATE(DOMAIN16_PG_CONFIG,
|
||||
DOMAIN_POWER_GATE, power_gate);
|
||||
|
||||
REG_WAIT(DOMAIN16_PG_STATUS,
|
||||
DOMAIN_PGFSM_PWR_STATUS, pwr_status,
|
||||
1, 1000);
|
||||
break;
|
||||
case 1: /* DSC1 */
|
||||
REG_UPDATE(DOMAIN17_PG_CONFIG,
|
||||
DOMAIN_POWER_GATE, power_gate);
|
||||
|
||||
REG_WAIT(DOMAIN17_PG_STATUS,
|
||||
DOMAIN_PGFSM_PWR_STATUS, pwr_status,
|
||||
1, 1000);
|
||||
break;
|
||||
case 2: /* DSC2 */
|
||||
REG_UPDATE(DOMAIN18_PG_CONFIG,
|
||||
DOMAIN_POWER_GATE, power_gate);
|
||||
|
||||
REG_WAIT(DOMAIN18_PG_STATUS,
|
||||
DOMAIN_PGFSM_PWR_STATUS, pwr_status,
|
||||
1, 1000);
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
break;
|
||||
}
|
||||
|
||||
if (org_ip_request_cntl == 0)
|
||||
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
|
||||
}
|
||||
|
||||
|
||||
void dcn31_enable_power_gating_plane(
|
||||
struct dce_hwseq *hws,
|
||||
bool enable)
|
||||
{
|
||||
bool force_on = true; /* disable power gating */
|
||||
|
||||
if (enable)
|
||||
force_on = false;
|
||||
|
||||
/* DCHUBP0/1/2/3/4/5 */
|
||||
REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
|
||||
/* DPP0/1/2/3/4/5 */
|
||||
REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
|
||||
/* DCS0/1/2/3/4/5 */
|
||||
REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
|
||||
}
|
||||
|
||||
void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
|
||||
{
|
||||
bool is_hdmi_tmds;
|
||||
bool is_dp;
|
||||
|
||||
ASSERT(pipe_ctx->stream);
|
||||
|
||||
if (pipe_ctx->stream_res.stream_enc == NULL)
|
||||
return; /* this is not root pipe */
|
||||
|
||||
is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
|
||||
is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
|
||||
|
||||
if (!is_hdmi_tmds)
|
||||
return;
|
||||
|
||||
if (is_hdmi_tmds)
|
||||
pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
|
||||
pipe_ctx->stream_res.stream_enc,
|
||||
&pipe_ctx->stream_res.encoder_info_frame);
|
||||
else {
|
||||
pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
|
||||
pipe_ctx->stream_res.stream_enc,
|
||||
&pipe_ctx->stream_res.encoder_info_frame);
|
||||
}
|
||||
}
|
||||
|
||||
void dcn31_z10_restore(struct dc *dc)
|
||||
{
|
||||
union dmub_rb_cmd cmd;
|
||||
|
||||
/*
|
||||
* DMUB notifies whether restore is required.
|
||||
* Optimization to avoid sending commands when not required.
|
||||
*/
|
||||
if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
|
||||
return;
|
||||
|
||||
memset(&cmd, 0, sizeof(cmd));
|
||||
cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
|
||||
cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
|
||||
|
||||
dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
|
||||
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
|
||||
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
|
||||
}
|
||||
|
||||
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
|
||||
{
|
||||
uint32_t power_gate = power_on ? 0 : 1;
|
||||
uint32_t pwr_status = power_on ? 0 : 2;
|
||||
|
||||
if (hws->ctx->dc->debug.disable_hubp_power_gate)
|
||||
return;
|
||||
|
||||
if (REG(DOMAIN0_PG_CONFIG) == 0)
|
||||
return;
|
||||
|
||||
switch (hubp_inst) {
|
||||
case 0:
|
||||
REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
|
||||
REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
|
||||
break;
|
||||
case 1:
|
||||
REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
|
||||
REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
|
||||
break;
|
||||
case 2:
|
||||
REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
|
||||
REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
|
||||
break;
|
||||
case 3:
|
||||
REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
|
||||
REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
|
||||
{
|
||||
struct dcn_hubbub_phys_addr_config config;
|
||||
|
||||
config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
|
||||
config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
|
||||
config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
|
||||
config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
|
||||
config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
|
||||
config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
|
||||
config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
|
||||
config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
|
||||
|
||||
if (pa_config->gart_config.base_addr_is_mc_addr) {
|
||||
/* Convert from MC address to offset into FB */
|
||||
config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
|
||||
pa_config->system_aperture.fb_base +
|
||||
pa_config->system_aperture.fb_offset;
|
||||
} else
|
||||
config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
|
||||
|
||||
return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
|
||||
}
|
||||
|
||||
static void dcn31_reset_back_end_for_pipe(
|
||||
struct dc *dc,
|
||||
struct pipe_ctx *pipe_ctx,
|
||||
struct dc_state *context)
|
||||
{
|
||||
struct dc_link *link;
|
||||
|
||||
DC_LOGGER_INIT(dc->ctx->logger);
|
||||
if (pipe_ctx->stream_res.stream_enc == NULL) {
|
||||
pipe_ctx->stream = NULL;
|
||||
return;
|
||||
}
|
||||
ASSERT(!pipe_ctx->top_pipe);
|
||||
|
||||
dc->hwss.set_abm_immediate_disable(pipe_ctx);
|
||||
|
||||
pipe_ctx->stream_res.tg->funcs->set_dsc_config(
|
||||
pipe_ctx->stream_res.tg,
|
||||
OPTC_DSC_DISABLED, 0, 0);
|
||||
pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
|
||||
|
||||
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
|
||||
if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
|
||||
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
|
||||
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
|
||||
|
||||
if (pipe_ctx->stream_res.tg->funcs->set_drr)
|
||||
pipe_ctx->stream_res.tg->funcs->set_drr(
|
||||
pipe_ctx->stream_res.tg, NULL);
|
||||
|
||||
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
||||
link = pipe_ctx->stream->link;
|
||||
/* DPMS may already disable or */
|
||||
/* dpms_off status is incorrect due to fastboot
|
||||
* feature. When system resume from S4 with second
|
||||
* screen only, the dpms_off would be true but
|
||||
* VBIOS lit up eDP, so check link status too.
|
||||
*/
|
||||
if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
|
||||
core_link_disable_stream(pipe_ctx);
|
||||
else if (pipe_ctx->stream_res.audio)
|
||||
dc->hwss.disable_audio_stream(pipe_ctx);
|
||||
|
||||
/* free acquired resources */
|
||||
if (pipe_ctx->stream_res.audio) {
|
||||
/*disable az_endpoint*/
|
||||
pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
|
||||
|
||||
/*free audio*/
|
||||
if (dc->caps.dynamic_audio == true) {
|
||||
/*we have to dynamic arbitrate the audio endpoints*/
|
||||
/*we free the resource, need reset is_audio_acquired*/
|
||||
update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
|
||||
pipe_ctx->stream_res.audio, false);
|
||||
pipe_ctx->stream_res.audio = NULL;
|
||||
}
|
||||
}
|
||||
} else if (pipe_ctx->stream_res.dsc) {
|
||||
dp_set_dsc_enable(pipe_ctx, false);
|
||||
}
|
||||
|
||||
pipe_ctx->stream = NULL;
|
||||
DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
|
||||
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
|
||||
}
|
||||
|
||||
void dcn31_reset_hw_ctx_wrap(
|
||||
struct dc *dc,
|
||||
struct dc_state *context)
|
||||
{
|
||||
int i;
|
||||
struct dce_hwseq *hws = dc->hwseq;
|
||||
|
||||
/* Reset Back End*/
|
||||
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
|
||||
struct pipe_ctx *pipe_ctx_old =
|
||||
&dc->current_state->res_ctx.pipe_ctx[i];
|
||||
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (!pipe_ctx_old->stream)
|
||||
continue;
|
||||
|
||||
if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
|
||||
continue;
|
||||
|
||||
if (!pipe_ctx->stream ||
|
||||
pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
|
||||
struct clock_source *old_clk = pipe_ctx_old->clock_source;
|
||||
|
||||
dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
|
||||
if (hws->funcs.enable_stream_gating)
|
||||
hws->funcs.enable_stream_gating(dc, pipe_ctx);
|
||||
if (old_clk)
|
||||
old_clk->funcs->cs_power_down(old_clk);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool dcn31_is_abm_supported(struct dc *dc,
|
||||
struct dc_state *context, struct dc_stream_state *stream)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (pipe_ctx->stream == stream &&
|
||||
(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_HWSS_DCN31_H__
|
||||
#define __DC_HWSS_DCN31_H__
|
||||
|
||||
#include "hw_sequencer_private.h"
|
||||
|
||||
struct dc;
|
||||
|
||||
void dcn31_init_hw(struct dc *dc);
|
||||
|
||||
void dcn31_dsc_pg_control(
|
||||
struct dce_hwseq *hws,
|
||||
unsigned int dsc_inst,
|
||||
bool power_on);
|
||||
|
||||
void dcn31_enable_power_gating_plane(
|
||||
struct dce_hwseq *hws,
|
||||
bool enable);
|
||||
|
||||
void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
|
||||
|
||||
void dcn31_z10_restore(struct dc *dc);
|
||||
|
||||
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
|
||||
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
|
||||
void dcn31_reset_hw_ctx_wrap(
|
||||
struct dc *dc,
|
||||
struct dc_state *context);
|
||||
bool dcn31_is_abm_supported(struct dc *dc,
|
||||
struct dc_state *context, struct dc_stream_state *stream);
|
||||
|
||||
#endif /* __DC_HWSS_DCN31_H__ */
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#include "dce110/dce110_hw_sequencer.h"
|
||||
#include "dcn10/dcn10_hw_sequencer.h"
|
||||
#include "dcn20/dcn20_hwseq.h"
|
||||
#include "dcn21/dcn21_hwseq.h"
|
||||
#include "dcn30/dcn30_hwseq.h"
|
||||
#include "dcn301/dcn301_hwseq.h"
|
||||
#include "dcn31/dcn31_hwseq.h"
|
||||
|
||||
static const struct hw_sequencer_funcs dcn31_funcs = {
|
||||
.program_gamut_remap = dcn10_program_gamut_remap,
|
||||
.init_hw = dcn31_init_hw,
|
||||
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
|
||||
.apply_ctx_for_surface = NULL,
|
||||
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
|
||||
.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
|
||||
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
|
||||
.update_plane_addr = dcn20_update_plane_addr,
|
||||
.update_dchub = dcn10_update_dchub,
|
||||
.update_pending_status = dcn10_update_pending_status,
|
||||
.program_output_csc = dcn20_program_output_csc,
|
||||
.enable_accelerated_mode = dce110_enable_accelerated_mode,
|
||||
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
|
||||
.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
|
||||
.update_info_frame = dcn31_update_info_frame,
|
||||
.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
|
||||
.enable_stream = dcn20_enable_stream,
|
||||
.disable_stream = dce110_disable_stream,
|
||||
.unblank_stream = dcn20_unblank_stream,
|
||||
.blank_stream = dce110_blank_stream,
|
||||
.enable_audio_stream = dce110_enable_audio_stream,
|
||||
.disable_audio_stream = dce110_disable_audio_stream,
|
||||
.disable_plane = dcn20_disable_plane,
|
||||
.pipe_control_lock = dcn20_pipe_control_lock,
|
||||
.interdependent_update_lock = dcn10_lock_all_pipes,
|
||||
.cursor_lock = dcn10_cursor_lock,
|
||||
.prepare_bandwidth = dcn20_prepare_bandwidth,
|
||||
.optimize_bandwidth = dcn20_optimize_bandwidth,
|
||||
.update_bandwidth = dcn20_update_bandwidth,
|
||||
.set_drr = dcn10_set_drr,
|
||||
.get_position = dcn10_get_position,
|
||||
.set_static_screen_control = dcn10_set_static_screen_control,
|
||||
.setup_stereo = dcn10_setup_stereo,
|
||||
.set_avmute = dcn30_set_avmute,
|
||||
.log_hw_state = dcn10_log_hw_state,
|
||||
.get_hw_state = dcn10_get_hw_state,
|
||||
.clear_status_bits = dcn10_clear_status_bits,
|
||||
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
|
||||
.edp_backlight_control = dce110_edp_backlight_control,
|
||||
.edp_power_control = dce110_edp_power_control,
|
||||
.edp_wait_for_T12 = dce110_edp_wait_for_T12,
|
||||
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
|
||||
.set_cursor_position = dcn10_set_cursor_position,
|
||||
.set_cursor_attribute = dcn10_set_cursor_attribute,
|
||||
.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
|
||||
.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
|
||||
.set_clock = dcn10_set_clock,
|
||||
.get_clock = dcn10_get_clock,
|
||||
.program_triplebuffer = dcn20_program_triple_buffer,
|
||||
.enable_writeback = dcn30_enable_writeback,
|
||||
.disable_writeback = dcn30_disable_writeback,
|
||||
.update_writeback = dcn30_update_writeback,
|
||||
.mmhubbub_warmup = dcn30_mmhubbub_warmup,
|
||||
.dmdata_status_done = dcn20_dmdata_status_done,
|
||||
.program_dmdata_engine = dcn30_program_dmdata_engine,
|
||||
.set_dmdata_attributes = dcn20_set_dmdata_attributes,
|
||||
.init_sys_ctx = dcn31_init_sys_ctx,
|
||||
.init_vm_ctx = dcn20_init_vm_ctx,
|
||||
.set_flip_control_gsl = dcn20_set_flip_control_gsl,
|
||||
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
|
||||
.calc_vupdate_position = dcn10_calc_vupdate_position,
|
||||
.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
|
||||
.set_backlight_level = dcn21_set_backlight_level,
|
||||
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
|
||||
.set_pipe = dcn21_set_pipe,
|
||||
.z10_restore = dcn31_z10_restore,
|
||||
.is_abm_supported = dcn31_is_abm_supported,
|
||||
.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
|
||||
};
|
||||
|
||||
static const struct hwseq_private_funcs dcn31_private_funcs = {
|
||||
.init_pipes = dcn10_init_pipes,
|
||||
.update_plane_addr = dcn20_update_plane_addr,
|
||||
.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
|
||||
.update_mpcc = dcn20_update_mpcc,
|
||||
.set_input_transfer_func = dcn30_set_input_transfer_func,
|
||||
.set_output_transfer_func = dcn30_set_output_transfer_func,
|
||||
.power_down = dce110_power_down,
|
||||
.enable_display_power_gating = dcn10_dummy_display_power_gating,
|
||||
.blank_pixel_data = dcn20_blank_pixel_data,
|
||||
.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
|
||||
.enable_stream_timing = dcn20_enable_stream_timing,
|
||||
.edp_backlight_control = dce110_edp_backlight_control,
|
||||
.disable_stream_gating = dcn20_disable_stream_gating,
|
||||
.enable_stream_gating = dcn20_enable_stream_gating,
|
||||
.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
|
||||
.did_underflow_occur = dcn10_did_underflow_occur,
|
||||
.init_blank = dcn20_init_blank,
|
||||
.disable_vga = dcn20_disable_vga,
|
||||
.bios_golden_init = dcn10_bios_golden_init,
|
||||
.plane_atomic_disable = dcn20_plane_atomic_disable,
|
||||
.plane_atomic_power_down = dcn10_plane_atomic_power_down,
|
||||
.enable_power_gating_plane = dcn31_enable_power_gating_plane,
|
||||
.hubp_pg_control = dcn31_hubp_pg_control,
|
||||
.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
|
||||
.update_odm = dcn20_update_odm,
|
||||
.dsc_pg_control = dcn31_dsc_pg_control,
|
||||
.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
|
||||
.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
|
||||
.set_hdr_multiplier = dcn10_set_hdr_multiplier,
|
||||
.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
|
||||
.wait_for_blank_complete = dcn20_wait_for_blank_complete,
|
||||
.dccg_init = dcn20_dccg_init,
|
||||
.set_blend_lut = dcn30_set_blend_lut,
|
||||
.set_shaper_3dlut = dcn20_set_shaper_3dlut,
|
||||
};
|
||||
|
||||
void dcn31_hw_sequencer_construct(struct dc *dc)
|
||||
{
|
||||
dc->hwss = dcn31_funcs;
|
||||
dc->hwseq->funcs = dcn31_private_funcs;
|
||||
|
||||
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
||||
dc->hwss.init_hw = dcn20_fpga_init_hw;
|
||||
dc->hwseq->funcs.init_pipes = NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_DCN31_INIT_H__
|
||||
#define __DC_DCN31_INIT_H__
|
||||
|
||||
struct dc;
|
||||
|
||||
void dcn31_hw_sequencer_construct(struct dc *dc);
|
||||
|
||||
#endif /* __DC_DCN31_INIT_H__ */
|
||||
|
|
@ -235,6 +235,10 @@ struct hw_sequencer_funcs {
|
|||
enum dc_color_depth color_depth,
|
||||
const struct tg_color *solid_color,
|
||||
int width, int height, int offset);
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
|
||||
void (*z10_restore)(struct dc *dc);
|
||||
#endif
|
||||
};
|
||||
|
||||
void color_space_to_black_color(
|
||||
|
|
|
|||
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