Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev: (32 commits) [libata] sata_mv: print out additional chip info during probe [libata] Use ATA_UDMAx standard masks when filling driver's udma_mask info [libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145) [libata] Clean up driver udma_mask initializers libata: Support chips with 64K PRD quirk Add a PCI ID for santa rosa's PATA controller. sata_sil24: sil24_interrupt() micro-optimisation Add irq_flags to struct pata_platform_info sata_promise: cleanups [libata] pata_ixp4xx: kill unused var ata_piix: fix pio/mwdma programming [libata] ahci: minor internal cleanups [ATA] Add named constant for ATAPI command DEVICE RESET [libata] sata_sx4, sata_via: minor documentation updates [libata] ahci: minor internal cleanups [libata] ahci: Factor out SATA port init into a separate function [libata] pata_sil680: minor cleanups from benh [libata] sata_sx4: named constant cleanup [libata] pata_ixp4xx: convert to new EH [libata] pdc_adma: Reorder initializers with a couple structs ...
This commit is contained in:
Коммит
64b853aa32
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@ -46,7 +46,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "ahci"
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#define DRV_VERSION "2.2"
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#define DRV_VERSION "2.3"
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enum {
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@ -54,7 +54,7 @@ enum {
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AHCI_MAX_PORTS = 32,
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AHCI_MAX_SG = 168, /* hardware max is 64K */
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AHCI_DMA_BOUNDARY = 0xffffffff,
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AHCI_USE_CLUSTERING = 0,
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AHCI_USE_CLUSTERING = 1,
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AHCI_MAX_CMDS = 32,
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AHCI_CMD_SZ = 32,
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AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
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@ -81,6 +81,7 @@ enum {
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board_ahci_vt8251 = 2,
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board_ahci_ign_iferr = 3,
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board_ahci_sb600 = 4,
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board_ahci_mv = 5,
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/* global controller registers */
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HOST_CAP = 0x00, /* host capabilities */
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@ -171,6 +172,8 @@ enum {
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AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
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AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
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AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
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AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
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AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
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AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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@ -228,9 +231,12 @@ static void ahci_thaw(struct ata_port *ap);
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static void ahci_error_handler(struct ata_port *ap);
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static void ahci_vt8251_error_handler(struct ata_port *ap);
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static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
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static int ahci_port_resume(struct ata_port *ap);
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
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static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
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u32 opts);
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#ifdef CONFIG_PM
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static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
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static int ahci_port_resume(struct ata_port *ap);
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static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int ahci_pci_device_resume(struct pci_dev *pdev);
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#endif
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@ -327,14 +333,14 @@ static const struct ata_port_info ahci_port_info[] = {
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{
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_pi */
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{
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.flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_vt8251 */
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@ -342,14 +348,14 @@ static const struct ata_port_info ahci_port_info[] = {
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
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AHCI_FLAG_NO_NCQ,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_vt8251_ops,
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},
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/* board_ahci_ign_iferr */
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{
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.flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_sb600 */
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@ -358,7 +364,19 @@ static const struct ata_port_info ahci_port_info[] = {
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AHCI_FLAG_IGN_SERR_INTERNAL |
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AHCI_FLAG_32BIT_ONLY,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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/* board_ahci_mv */
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{
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.sht = &ahci_sht,
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI |
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AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
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AHCI_FLAG_MV_PATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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};
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@ -456,6 +474,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
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{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
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/* Marvell */
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{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
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/* Generic, PCI class code for AHCI */
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
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@ -481,11 +502,17 @@ static inline int ahci_nr_ports(u32 cap)
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return (cap & 0x1f) + 1;
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}
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static inline void __iomem *__ahci_port_base(struct ata_host *host,
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unsigned int port_no)
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{
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void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
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return mmio + 0x100 + (port_no * 0x80);
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}
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static inline void __iomem *ahci_port_base(struct ata_port *ap)
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{
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void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
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return mmio + 0x100 + (ap->port_no * 0x80);
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return __ahci_port_base(ap->host, ap->port_no);
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}
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/**
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@ -535,6 +562,20 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
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hpriv->saved_port_map = port_map;
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}
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/*
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* Temporary Marvell 6145 hack: PATA port presence
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* is asserted through the standard AHCI port
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* presence register, as bit 4 (counting from 0)
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*/
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if (pi->flags & AHCI_FLAG_MV_PATA) {
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dev_printk(KERN_ERR, &pdev->dev,
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"MV_AHCI HACK: port_map %x -> %x\n",
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hpriv->port_map,
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hpriv->port_map & 0xf);
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port_map &= 0xf;
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}
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/* cross check port_map and cap.n_ports */
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if (pi->flags & AHCI_FLAG_HONOR_PI) {
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u32 tmp_port_map = port_map;
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@ -740,7 +781,7 @@ static void ahci_power_down(struct ata_port *ap)
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}
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#endif
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static void ahci_init_port(struct ata_port *ap)
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static void ahci_start_port(struct ata_port *ap)
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{
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/* enable FIS reception */
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ahci_start_fis_rx(ap);
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@ -814,39 +855,62 @@ static int ahci_reset_controller(struct ata_host *host)
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return 0;
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}
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static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
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int port_no, void __iomem *mmio,
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void __iomem *port_mmio)
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{
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const char *emsg = NULL;
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int rc;
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u32 tmp;
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/* make sure port is not active */
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rc = ahci_deinit_port(ap, &emsg);
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if (rc)
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dev_printk(KERN_WARNING, &pdev->dev,
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"%s (%d)\n", emsg, rc);
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/* clear SError */
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tmp = readl(port_mmio + PORT_SCR_ERR);
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VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
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writel(tmp, port_mmio + PORT_SCR_ERR);
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/* clear port IRQ */
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tmp = readl(port_mmio + PORT_IRQ_STAT);
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VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
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if (tmp)
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writel(tmp, port_mmio + PORT_IRQ_STAT);
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writel(1 << port_no, mmio + HOST_IRQ_STAT);
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}
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static void ahci_init_controller(struct ata_host *host)
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{
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struct pci_dev *pdev = to_pci_dev(host->dev);
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void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
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int i, rc;
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int i;
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void __iomem *port_mmio;
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u32 tmp;
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap = host->ports[i];
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void __iomem *port_mmio = ahci_port_base(ap);
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const char *emsg = NULL;
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if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
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port_mmio = __ahci_port_base(host, 4);
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if (ata_port_is_dummy(ap))
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continue;
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/* make sure port is not active */
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rc = ahci_deinit_port(ap, &emsg);
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if (rc)
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dev_printk(KERN_WARNING, &pdev->dev,
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"%s (%d)\n", emsg, rc);
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/* clear SError */
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tmp = readl(port_mmio + PORT_SCR_ERR);
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VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
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writel(tmp, port_mmio + PORT_SCR_ERR);
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writel(0, port_mmio + PORT_IRQ_MASK);
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/* clear port IRQ */
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tmp = readl(port_mmio + PORT_IRQ_STAT);
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VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
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if (tmp)
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writel(tmp, port_mmio + PORT_IRQ_STAT);
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}
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writel(1 << i, mmio + HOST_IRQ_STAT);
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap = host->ports[i];
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port_mmio = ahci_port_base(ap);
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if (ata_port_is_dummy(ap))
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continue;
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ahci_port_init(pdev, ap, i, mmio, port_mmio);
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}
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tmp = readl(mmio + HOST_CTL);
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@ -1232,7 +1296,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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ata_port_abort(ap);
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}
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static void ahci_host_intr(struct ata_port *ap)
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static void ahci_port_intr(struct ata_port *ap)
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{
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void __iomem *port_mmio = ap->ioaddr.cmd_addr;
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struct ata_eh_info *ehi = &ap->eh_info;
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@ -1358,7 +1422,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
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ap = host->ports[i];
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if (ap) {
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ahci_host_intr(ap);
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ahci_port_intr(ap);
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VPRINTK("port %u\n", i);
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} else {
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VPRINTK("port %u (no irq)\n", i);
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@ -1466,7 +1530,7 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
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ahci_power_down(ap);
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else {
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ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
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ahci_init_port(ap);
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ahci_start_port(ap);
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}
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return rc;
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@ -1475,7 +1539,7 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
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static int ahci_port_resume(struct ata_port *ap)
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{
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ahci_power_up(ap);
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ahci_init_port(ap);
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ahci_start_port(ap);
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return 0;
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}
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@ -1573,13 +1637,8 @@ static int ahci_port_start(struct ata_port *ap)
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ap->private_data = pp;
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/* power up port */
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ahci_power_up(ap);
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/* initialize port */
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ahci_init_port(ap);
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return 0;
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/* engage engines, captain */
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return ahci_port_resume(ap);
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}
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static void ahci_port_stop(struct ata_port *ap)
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@ -1724,7 +1783,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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if (pci_enable_msi(pdev))
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if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
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pci_intx(pdev, 1);
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hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
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@ -1745,14 +1804,18 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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host->private_data = hpriv;
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for (i = 0; i < host->n_ports; i++) {
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if (hpriv->port_map & (1 << i)) {
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struct ata_port *ap = host->ports[i];
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ata_port *ap = host->ports[i];
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void __iomem *port_mmio = ahci_port_base(ap);
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/* standard SATA port setup */
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if (hpriv->port_map & (1 << i)) {
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ap->ioaddr.cmd_addr = port_mmio;
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ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
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} else
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host->ports[i]->ops = &ata_dummy_port_ops;
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}
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/* disabled/not-implemented port */
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else
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ap->ops = &ata_dummy_port_ops;
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}
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/* initialize adapter */
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|
|
|
@ -143,10 +143,10 @@ static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id
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u16 command;
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static const struct ata_port_info info = {
|
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.sht = &generic_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = 0x3f,
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.udma_mask = ATA_UDMA5,
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.port_ops = &generic_port_ops
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};
|
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const struct ata_port_info *ppi[] = { &info, NULL };
|
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|
|
|
@ -200,6 +200,8 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* ICH7/7-R (i945, i975) UDMA 100*/
|
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
|
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
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/* ICH8 Mobile PATA Controller */
|
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{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
||||
|
||||
/* NOTE: The following PCI ids must be kept in sync with the
|
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* list in drivers/pci/quirks.c.
|
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|
@ -495,7 +497,7 @@ static struct ata_port_info piix_port_info[] = {
|
|||
.flags = PIIX_SATA_FLAGS,
|
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.pio_mask = 0x1f, /* pio0-4 */
|
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.mwdma_mask = 0x07, /* mwdma0-2 */
|
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.udma_mask = 0x7f, /* udma0-6 */
|
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.udma_mask = ATA_UDMA6,
|
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.port_ops = &piix_sata_ops,
|
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},
|
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|
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|
@ -505,7 +507,7 @@ static struct ata_port_info piix_port_info[] = {
|
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
|
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.pio_mask = 0x1f, /* pio0-4 */
|
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.mwdma_mask = 0x07, /* mwdma0-2 */
|
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.udma_mask = 0x7f, /* udma0-6 */
|
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.udma_mask = ATA_UDMA6,
|
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.port_ops = &piix_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -516,7 +518,7 @@ static struct ata_port_info piix_port_info[] = {
|
|||
PIIX_FLAG_AHCI,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &piix_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -527,7 +529,7 @@ static struct ata_port_info piix_port_info[] = {
|
|||
PIIX_FLAG_AHCI,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &piix_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -538,7 +540,7 @@ static struct ata_port_info piix_port_info[] = {
|
|||
PIIX_FLAG_AHCI,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &piix_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -685,8 +687,14 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
|
|||
if (adev->class == ATA_DEV_ATA)
|
||||
control |= 4; /* PPE enable */
|
||||
|
||||
/* PIO configuration clears DTE unconditionally. It will be
|
||||
* programmed in set_dmamode which is guaranteed to be called
|
||||
* after set_piomode if any DMA mode is available.
|
||||
*/
|
||||
pci_read_config_word(dev, master_port, &master_data);
|
||||
if (is_slave) {
|
||||
/* clear TIME1|IE1|PPE1|DTE1 */
|
||||
master_data &= 0xff0f;
|
||||
/* Enable SITRE (seperate slave timing register) */
|
||||
master_data |= 0x4000;
|
||||
/* enable PPE1, IE1 and TIME1 as needed */
|
||||
|
@ -694,12 +702,14 @@ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
|
|||
pci_read_config_byte(dev, slave_port, &slave_data);
|
||||
slave_data &= (ap->port_no ? 0x0f : 0xf0);
|
||||
/* Load the timing nibble for this slave */
|
||||
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
|
||||
slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
|
||||
<< (ap->port_no ? 4 : 0);
|
||||
} else {
|
||||
/* Master keeps the bits in a different format */
|
||||
master_data &= 0xccf8;
|
||||
/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
|
||||
master_data &= 0xccf0;
|
||||
/* Enable PPE, IE and TIME as appropriate */
|
||||
master_data |= control;
|
||||
/* load ISP and RCT */
|
||||
master_data |=
|
||||
(timings[pio][0] << 12) |
|
||||
(timings[pio][1] << 8);
|
||||
|
@ -816,7 +826,7 @@ static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, i
|
|||
master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
|
||||
master_data |= control << 4;
|
||||
pci_read_config_byte(dev, 0x44, &slave_data);
|
||||
slave_data &= (0x0F + 0xE1 * ap->port_no);
|
||||
slave_data &= (ap->port_no ? 0x0f : 0xf0);
|
||||
/* Load the matching timing */
|
||||
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
|
||||
pci_write_config_byte(dev, 0x44, slave_data);
|
||||
|
@ -828,8 +838,11 @@ static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, i
|
|||
(timings[pio][0] << 12) |
|
||||
(timings[pio][1] << 8);
|
||||
}
|
||||
udma_enable &= ~(1 << devid);
|
||||
pci_write_config_word(dev, master_port, master_data);
|
||||
|
||||
if (ap->udma_mask) {
|
||||
udma_enable &= ~(1 << devid);
|
||||
pci_write_config_word(dev, master_port, master_data);
|
||||
}
|
||||
}
|
||||
/* Don't scribble on 0x48 if the controller does not support UDMA */
|
||||
if (ap->udma_mask)
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1845,7 +1845,8 @@ static void ata_dev_config_ncq(struct ata_device *dev,
|
|||
int ata_dev_configure(struct ata_device *dev)
|
||||
{
|
||||
struct ata_port *ap = dev->ap;
|
||||
int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
|
||||
struct ata_eh_context *ehc = &ap->eh_context;
|
||||
int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
|
||||
const u16 *id = dev->id;
|
||||
unsigned int xfer_mask;
|
||||
char revbuf[7]; /* XYZ-99\0 */
|
||||
|
@ -1862,15 +1863,10 @@ int ata_dev_configure(struct ata_device *dev)
|
|||
if (ata_msg_probe(ap))
|
||||
ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER\n", __FUNCTION__);
|
||||
|
||||
/* set _SDD */
|
||||
rc = ata_acpi_push_id(dev);
|
||||
if (rc) {
|
||||
ata_dev_printk(dev, KERN_WARNING, "failed to set _SDD(%d)\n",
|
||||
rc);
|
||||
}
|
||||
|
||||
/* retrieve and execute the ATA task file of _GTF */
|
||||
ata_acpi_exec_tfs(ap);
|
||||
/* let ACPI work its magic */
|
||||
rc = ata_acpi_on_devcfg(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* print device capabilities */
|
||||
if (ata_msg_probe(ap))
|
||||
|
@ -3359,7 +3355,7 @@ int ata_std_prereset(struct ata_port *ap, unsigned long deadline)
|
|||
return 0;
|
||||
|
||||
/* if SATA, resume phy */
|
||||
if (ap->cbl == ATA_CBL_SATA) {
|
||||
if (ap->flags & ATA_FLAG_SATA) {
|
||||
rc = sata_phy_resume(ap, timing, deadline);
|
||||
/* whine about phy resume failure but proceed */
|
||||
if (rc && rc != -EOPNOTSUPP)
|
||||
|
@ -4106,6 +4102,68 @@ static void ata_fill_sg(struct ata_queued_cmd *qc)
|
|||
ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
|
||||
}
|
||||
|
||||
/**
|
||||
* ata_fill_sg_dumb - Fill PCI IDE PRD table
|
||||
* @qc: Metadata associated with taskfile to be transferred
|
||||
*
|
||||
* Fill PCI IDE PRD (scatter-gather) table with segments
|
||||
* associated with the current disk command. Perform the fill
|
||||
* so that we avoid writing any length 64K records for
|
||||
* controllers that don't follow the spec.
|
||||
*
|
||||
* LOCKING:
|
||||
* spin_lock_irqsave(host lock)
|
||||
*
|
||||
*/
|
||||
static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
struct scatterlist *sg;
|
||||
unsigned int idx;
|
||||
|
||||
WARN_ON(qc->__sg == NULL);
|
||||
WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
|
||||
|
||||
idx = 0;
|
||||
ata_for_each_sg(sg, qc) {
|
||||
u32 addr, offset;
|
||||
u32 sg_len, len, blen;
|
||||
|
||||
/* determine if physical DMA addr spans 64K boundary.
|
||||
* Note h/w doesn't support 64-bit, so we unconditionally
|
||||
* truncate dma_addr_t to u32.
|
||||
*/
|
||||
addr = (u32) sg_dma_address(sg);
|
||||
sg_len = sg_dma_len(sg);
|
||||
|
||||
while (sg_len) {
|
||||
offset = addr & 0xffff;
|
||||
len = sg_len;
|
||||
if ((offset + sg_len) > 0x10000)
|
||||
len = 0x10000 - offset;
|
||||
|
||||
blen = len & 0xffff;
|
||||
ap->prd[idx].addr = cpu_to_le32(addr);
|
||||
if (blen == 0) {
|
||||
/* Some PATA chipsets like the CS5530 can't
|
||||
cope with 0x0000 meaning 64K as the spec says */
|
||||
ap->prd[idx].flags_len = cpu_to_le32(0x8000);
|
||||
blen = 0x8000;
|
||||
ap->prd[++idx].addr = cpu_to_le32(addr + 0x8000);
|
||||
}
|
||||
ap->prd[idx].flags_len = cpu_to_le32(blen);
|
||||
VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
|
||||
|
||||
idx++;
|
||||
sg_len -= len;
|
||||
addr += len;
|
||||
}
|
||||
}
|
||||
|
||||
if (idx)
|
||||
ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
|
||||
}
|
||||
|
||||
/**
|
||||
* ata_check_atapi_dma - Check whether ATAPI DMA can be supported
|
||||
* @qc: Metadata associated with taskfile to check
|
||||
|
@ -4153,6 +4211,23 @@ void ata_qc_prep(struct ata_queued_cmd *qc)
|
|||
ata_fill_sg(qc);
|
||||
}
|
||||
|
||||
/**
|
||||
* ata_dumb_qc_prep - Prepare taskfile for submission
|
||||
* @qc: Metadata associated with taskfile to be prepared
|
||||
*
|
||||
* Prepare ATA taskfile for submission.
|
||||
*
|
||||
* LOCKING:
|
||||
* spin_lock_irqsave(host lock)
|
||||
*/
|
||||
void ata_dumb_qc_prep(struct ata_queued_cmd *qc)
|
||||
{
|
||||
if (!(qc->flags & ATA_QCFLAG_DMAMAP))
|
||||
return;
|
||||
|
||||
ata_fill_sg_dumb(qc);
|
||||
}
|
||||
|
||||
void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
|
||||
|
||||
/**
|
||||
|
@ -5660,7 +5735,7 @@ irqreturn_t ata_interrupt (int irq, void *dev_instance)
|
|||
*/
|
||||
int sata_scr_valid(struct ata_port *ap)
|
||||
{
|
||||
return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
|
||||
return (ap->flags & ATA_FLAG_SATA) && ap->ops->scr_read;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -6293,6 +6368,9 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
|
|||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* associate with ACPI nodes */
|
||||
ata_acpi_associate(host);
|
||||
|
||||
/* set cable, sata_spd_limit and report */
|
||||
for (i = 0; i < host->n_ports; i++) {
|
||||
struct ata_port *ap = host->ports[i];
|
||||
|
@ -6324,7 +6402,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
|
|||
if (!ata_port_is_dummy(ap))
|
||||
ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%p "
|
||||
"ctl 0x%p bmdma 0x%p irq %d\n",
|
||||
ap->cbl == ATA_CBL_SATA ? 'S' : 'P',
|
||||
(ap->flags & ATA_FLAG_SATA) ? 'S' : 'P',
|
||||
ata_mode_string(xfer_mask),
|
||||
ap->ioaddr.cmd_addr,
|
||||
ap->ioaddr.ctl_addr,
|
||||
|
@ -6822,6 +6900,7 @@ EXPORT_SYMBOL_GPL(ata_do_set_mode);
|
|||
EXPORT_SYMBOL_GPL(ata_data_xfer);
|
||||
EXPORT_SYMBOL_GPL(ata_data_xfer_noirq);
|
||||
EXPORT_SYMBOL_GPL(ata_qc_prep);
|
||||
EXPORT_SYMBOL_GPL(ata_dumb_qc_prep);
|
||||
EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
|
||||
EXPORT_SYMBOL_GPL(ata_bmdma_setup);
|
||||
EXPORT_SYMBOL_GPL(ata_bmdma_start);
|
||||
|
|
|
@ -2154,19 +2154,25 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
|
|||
|
||||
WARN_ON(ap->pflags & ATA_PFLAG_SUSPENDED);
|
||||
|
||||
/* tell ACPI we're suspending */
|
||||
rc = ata_acpi_on_suspend(ap);
|
||||
if (rc)
|
||||
goto out;
|
||||
|
||||
/* suspend */
|
||||
ata_eh_freeze_port(ap);
|
||||
|
||||
if (ap->ops->port_suspend)
|
||||
rc = ap->ops->port_suspend(ap, ap->pm_mesg);
|
||||
|
||||
out:
|
||||
/* report result */
|
||||
spin_lock_irqsave(ap->lock, flags);
|
||||
|
||||
ap->pflags &= ~ATA_PFLAG_PM_PENDING;
|
||||
if (rc == 0)
|
||||
ap->pflags |= ATA_PFLAG_SUSPENDED;
|
||||
else
|
||||
else if (ap->pflags & ATA_PFLAG_FROZEN)
|
||||
ata_port_schedule_eh(ap);
|
||||
|
||||
if (ap->pm_result) {
|
||||
|
@ -2207,6 +2213,9 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
|
|||
if (ap->ops->port_resume)
|
||||
rc = ap->ops->port_resume(ap);
|
||||
|
||||
/* tell ACPI that we're resuming */
|
||||
ata_acpi_on_resume(ap);
|
||||
|
||||
/* report result */
|
||||
spin_lock_irqsave(ap->lock, flags);
|
||||
ap->pflags &= ~(ATA_PFLAG_PM_PENDING | ATA_PFLAG_SUSPENDED);
|
||||
|
|
|
@ -2620,7 +2620,7 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
|
|||
ata_dev_printk(dev, KERN_WARNING,
|
||||
"invalid multi_count %u ignored\n",
|
||||
multi_count);
|
||||
}
|
||||
}
|
||||
|
||||
/* READ/WRITE LONG use a non-standard sect_size */
|
||||
qc->sect_size = ATA_SECT_SIZE;
|
||||
|
|
|
@ -98,17 +98,15 @@ extern struct ata_port *ata_port_alloc(struct ata_host *host);
|
|||
|
||||
/* libata-acpi.c */
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
extern int ata_acpi_exec_tfs(struct ata_port *ap);
|
||||
extern int ata_acpi_push_id(struct ata_device *dev);
|
||||
extern void ata_acpi_associate(struct ata_host *host);
|
||||
extern int ata_acpi_on_suspend(struct ata_port *ap);
|
||||
extern void ata_acpi_on_resume(struct ata_port *ap);
|
||||
extern int ata_acpi_on_devcfg(struct ata_device *adev);
|
||||
#else
|
||||
static inline int ata_acpi_exec_tfs(struct ata_port *ap)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int ata_acpi_push_id(struct ata_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void ata_acpi_associate(struct ata_host *host) { }
|
||||
static inline int ata_acpi_on_suspend(struct ata_port *ap) { return 0; }
|
||||
static inline void ata_acpi_on_resume(struct ata_port *ap) { }
|
||||
static inline int ata_acpi_on_devcfg(struct ata_device *adev) { return 0; }
|
||||
#endif
|
||||
|
||||
/* libata-scsi.c */
|
||||
|
|
|
@ -520,14 +520,14 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info_early = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &ali_early_port_ops
|
||||
};
|
||||
/* Revision 0x20 added DMA */
|
||||
static const struct ata_port_info info_20 = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &ali_20_port_ops
|
||||
|
@ -535,7 +535,7 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
/* Revision 0x20 with support logic added UDMA */
|
||||
static const struct ata_port_info info_20_udma = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07, /* UDMA33 */
|
||||
|
@ -544,37 +544,37 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
/* Revision 0xC2 adds UDMA66 */
|
||||
static const struct ata_port_info info_c2 = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &ali_c2_port_ops
|
||||
};
|
||||
/* Revision 0xC3 is UDMA66 for now */
|
||||
static const struct ata_port_info info_c3 = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &ali_c2_port_ops
|
||||
};
|
||||
/* Revision 0xC4 is UDMA100 */
|
||||
static const struct ata_port_info info_c4 = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &ali_c2_port_ops
|
||||
};
|
||||
/* Revision 0xC5 is UDMA133 with LBA48 DMA */
|
||||
static const struct ata_port_info info_c5 = {
|
||||
.sht = &ali_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &ali_c5_port_ops
|
||||
};
|
||||
|
||||
|
|
|
@ -541,7 +541,7 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
static const struct ata_port_info info[10] = {
|
||||
{ /* 0: AMD 7401 */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07, /* No SWDMA */
|
||||
.udma_mask = 0x07, /* UDMA 33 */
|
||||
|
@ -549,74 +549,74 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
},
|
||||
{ /* 1: Early AMD7409 - no swdma */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f, /* UDMA 66 */
|
||||
.udma_mask = ATA_UDMA4, /* UDMA 66 */
|
||||
.port_ops = &amd66_port_ops
|
||||
},
|
||||
{ /* 2: AMD 7409, no swdma errata */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f, /* UDMA 66 */
|
||||
.udma_mask = ATA_UDMA4, /* UDMA 66 */
|
||||
.port_ops = &amd66_port_ops
|
||||
},
|
||||
{ /* 3: AMD 7411 */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f, /* UDMA 100 */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 100 */
|
||||
.port_ops = &amd100_port_ops
|
||||
},
|
||||
{ /* 4: AMD 7441 */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f, /* UDMA 100 */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 100 */
|
||||
.port_ops = &amd100_port_ops
|
||||
},
|
||||
{ /* 5: AMD 8111*/
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f, /* UDMA 133, no swdma */
|
||||
.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
|
||||
.port_ops = &amd133_port_ops
|
||||
},
|
||||
{ /* 6: AMD 8111 UDMA 100 (Serenade) */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f, /* UDMA 100, no swdma */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
|
||||
.port_ops = &amd133_port_ops
|
||||
},
|
||||
{ /* 7: Nvidia Nforce */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f, /* UDMA 100 */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 100 */
|
||||
.port_ops = &nv100_port_ops
|
||||
},
|
||||
{ /* 8: Nvidia Nforce2 and later */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f, /* UDMA 133, no swdma */
|
||||
.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
|
||||
.port_ops = &nv133_port_ops
|
||||
},
|
||||
{ /* 9: AMD CS5536 (Geode companion) */
|
||||
.sht = &amd_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f, /* UDMA 100 */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 100 */
|
||||
.port_ops = &amd100_port_ops
|
||||
}
|
||||
};
|
||||
|
|
|
@ -416,7 +416,7 @@ static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info_6210 = {
|
||||
.sht = &artop_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = ATA_UDMA2,
|
||||
|
@ -424,7 +424,7 @@ static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
};
|
||||
static const struct ata_port_info info_626x = {
|
||||
.sht = &artop_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = ATA_UDMA4,
|
||||
|
@ -432,7 +432,7 @@ static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
};
|
||||
static const struct ata_port_info info_626x_fast = {
|
||||
.sht = &artop_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
|
|
|
@ -270,7 +270,7 @@ static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &atiixp_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x06, /* No MWDMA0 support */
|
||||
.udma_mask = 0x3F,
|
||||
|
@ -285,6 +285,7 @@ static const struct pci_device_id atiixp[] = {
|
|||
{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
|
||||
{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
|
||||
{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
|
||||
{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
|
||||
|
||||
{ },
|
||||
};
|
||||
|
|
|
@ -251,7 +251,7 @@ static int cmd640_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &cmd640_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &cmd640_port_ops
|
||||
};
|
||||
|
|
|
@ -380,21 +380,21 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
static const struct ata_port_info cmd_info[6] = {
|
||||
{ /* CMD 643 - no UDMA */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &cmd64x_port_ops
|
||||
},
|
||||
{ /* CMD 646 with broken UDMA */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &cmd64x_port_ops
|
||||
},
|
||||
{ /* CMD 646 with working UDMA */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA1,
|
||||
|
@ -402,14 +402,14 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
},
|
||||
{ /* CMD 646 rev 1 */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &cmd646r1_port_ops
|
||||
},
|
||||
{ /* CMD 648 */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA2,
|
||||
|
@ -417,7 +417,7 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
},
|
||||
{ /* CMD 649 */
|
||||
.sht = &cmd64x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA3,
|
||||
|
|
|
@ -146,7 +146,7 @@ static struct scsi_host_template cs5520_sht = {
|
|||
.queuecommand = ata_scsi_queuecmd,
|
||||
.can_queue = ATA_DEF_QUEUE,
|
||||
.this_id = ATA_SHT_THIS_ID,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.sg_tablesize = LIBATA_DUMB_MAX_PRD,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
||||
|
@ -178,7 +178,7 @@ static struct ata_port_operations cs5520_port_ops = {
|
|||
.bmdma_start = ata_bmdma_start,
|
||||
.bmdma_stop = ata_bmdma_stop,
|
||||
.bmdma_status = ata_bmdma_status,
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_prep = ata_dumb_qc_prep,
|
||||
.qc_issue = ata_qc_issue_prot,
|
||||
.data_xfer = ata_data_xfer,
|
||||
|
||||
|
|
|
@ -167,7 +167,7 @@ static struct scsi_host_template cs5530_sht = {
|
|||
.queuecommand = ata_scsi_queuecmd,
|
||||
.can_queue = ATA_DEF_QUEUE,
|
||||
.this_id = ATA_SHT_THIS_ID,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.sg_tablesize = LIBATA_DUMB_MAX_PRD,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
||||
|
@ -201,7 +201,7 @@ static struct ata_port_operations cs5530_port_ops = {
|
|||
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
||||
.cable_detect = ata_cable_40wire,
|
||||
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_prep = ata_dumb_qc_prep,
|
||||
.qc_issue = cs5530_qc_issue_prot,
|
||||
|
||||
.data_xfer = ata_data_xfer,
|
||||
|
@ -337,7 +337,7 @@ static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &cs5530_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07,
|
||||
|
@ -346,7 +346,7 @@ static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
/* The docking connector doesn't do UDMA, and it seems not MWDMA */
|
||||
static const struct ata_port_info info_palmax_secondary = {
|
||||
.sht = &cs5530_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &cs5530_port_ops
|
||||
};
|
||||
|
|
|
@ -225,10 +225,10 @@ static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &cs5535_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &cs5535_port_ops
|
||||
};
|
||||
const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
|
||||
|
|
|
@ -167,7 +167,7 @@ static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *i
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &cy82c693_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &cy82c693_port_ops
|
||||
|
|
|
@ -303,7 +303,7 @@ static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &efar_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma1-2 */
|
||||
.udma_mask = 0x0f, /* UDMA 66 */
|
||||
|
|
|
@ -393,10 +393,10 @@ static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info_hpt366 = {
|
||||
.sht = &hpt36x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &hpt366_port_ops
|
||||
};
|
||||
struct ata_port_info info = info_hpt366;
|
||||
|
|
|
@ -889,25 +889,25 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
/* HPT370 - UDMA100 */
|
||||
static const struct ata_port_info info_hpt370 = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &hpt370_port_ops
|
||||
};
|
||||
/* HPT370A - UDMA100 */
|
||||
static const struct ata_port_info info_hpt370a = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &hpt370a_port_ops
|
||||
};
|
||||
/* HPT370 - UDMA100 */
|
||||
static const struct ata_port_info info_hpt370_33 = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x0f,
|
||||
|
@ -916,7 +916,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
/* HPT370A - UDMA100 */
|
||||
static const struct ata_port_info info_hpt370a_33 = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x0f,
|
||||
|
@ -925,19 +925,19 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
/* HPT371, 372 and friends - UDMA133 */
|
||||
static const struct ata_port_info info_hpt372 = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &hpt372_port_ops
|
||||
};
|
||||
/* HPT374 - UDMA100 */
|
||||
static const struct ata_port_info info_hpt374 = {
|
||||
.sht = &hpt37x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &hpt374_port_ops
|
||||
};
|
||||
|
||||
|
|
|
@ -490,10 +490,10 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
/* HPT372N and friends - UDMA133 */
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &hpt3x2n_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &hpt3x2n_port_ops
|
||||
};
|
||||
struct ata_port_info port = info;
|
||||
|
|
|
@ -173,7 +173,7 @@ static int hpt3x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &hpt3x3_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07,
|
||||
|
|
|
@ -530,7 +530,7 @@ static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
|
|||
|
||||
ap->pio_mask = 0x1f;
|
||||
ap->mwdma_mask = info->mwdma_mask;
|
||||
ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
|
||||
ap->flags |= ATA_FLAG_SLAVE_POSS;
|
||||
ap->ops = &pata_icside_port_ops;
|
||||
|
||||
pata_icside_setup_ioaddr(&ap->ioaddr, info->base, info->port[i]);
|
||||
|
|
|
@ -313,10 +313,10 @@ static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *en
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &it8213_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x1f, /* UDMA 100 */
|
||||
.udma_mask = ATA_UDMA4, /* FIXME: want UDMA 100? */
|
||||
.port_ops = &it8213_ops,
|
||||
};
|
||||
/* Current IT8213 stuff is single port */
|
||||
|
|
|
@ -714,17 +714,17 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
|
||||
static const struct ata_port_info info_smart = {
|
||||
.sht = &it821x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &it821x_smart_port_ops
|
||||
};
|
||||
static const struct ata_port_info info_passthru = {
|
||||
.sht = &it821x_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &it821x_passthru_port_ops
|
||||
};
|
||||
|
||||
|
|
|
@ -1,13 +1,14 @@
|
|||
/*
|
||||
* ixp4xx PATA/Compact Flash driver
|
||||
* Copyright (c) 2006 Tower Technologies
|
||||
* Copyright (C) 2006-07 Tower Technologies
|
||||
* Author: Alessandro Zummo <a.zummo@towertech.it>
|
||||
*
|
||||
* An ATA driver to handle a Compact Flash connected
|
||||
* to the ixp4xx expansion bus in TrueIDE mode. The CF
|
||||
* must have it chip selects connected to two CS lines
|
||||
* on the ixp4xx. The interrupt line is optional, if not
|
||||
* specified the driver will run in polling mode.
|
||||
* on the ixp4xx. In the irq is not available, you might
|
||||
* want to modify both this driver and libata to run in
|
||||
* polling mode.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -23,7 +24,7 @@
|
|||
#include <scsi/scsi_host.h>
|
||||
|
||||
#define DRV_NAME "pata_ixp4xx_cf"
|
||||
#define DRV_VERSION "0.1.3"
|
||||
#define DRV_VERSION "0.2"
|
||||
|
||||
static int ixp4xx_set_mode(struct ata_port *ap, struct ata_device **error)
|
||||
{
|
||||
|
@ -42,13 +43,6 @@ static int ixp4xx_set_mode(struct ata_port *ap, struct ata_device **error)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void ixp4xx_phy_reset(struct ata_port *ap)
|
||||
{
|
||||
ap->cbl = ATA_CBL_PATA40;
|
||||
ata_port_probe(ap);
|
||||
ata_bus_reset(ap);
|
||||
}
|
||||
|
||||
static void ixp4xx_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
|
||||
unsigned int buflen, int write_data)
|
||||
{
|
||||
|
@ -56,7 +50,7 @@ static void ixp4xx_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
|
|||
unsigned int words = buflen >> 1;
|
||||
u16 *buf16 = (u16 *) buf;
|
||||
struct ata_port *ap = adev->ap;
|
||||
void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
|
||||
void __iomem *mmio = ap->ioaddr.data_addr;
|
||||
struct ixp4xx_pata_data *data = ap->host->dev->platform_data;
|
||||
|
||||
/* set the expansion bus in 16bit mode and restore
|
||||
|
@ -92,10 +86,6 @@ static void ixp4xx_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
|
|||
*data->cs0_cfg |= 0x01;
|
||||
}
|
||||
|
||||
static void ixp4xx_irq_clear(struct ata_port *ap)
|
||||
{
|
||||
}
|
||||
|
||||
static struct scsi_host_template ixp4xx_sht = {
|
||||
.module = THIS_MODULE,
|
||||
.name = DRV_NAME,
|
||||
|
@ -115,29 +105,32 @@ static struct scsi_host_template ixp4xx_sht = {
|
|||
};
|
||||
|
||||
static struct ata_port_operations ixp4xx_port_ops = {
|
||||
.set_mode = ixp4xx_set_mode,
|
||||
.mode_filter = ata_pci_default_filter,
|
||||
.set_mode = ixp4xx_set_mode,
|
||||
.mode_filter = ata_pci_default_filter,
|
||||
|
||||
.port_disable = ata_port_disable,
|
||||
.tf_load = ata_tf_load,
|
||||
.tf_read = ata_tf_read,
|
||||
.check_status = ata_check_status,
|
||||
.exec_command = ata_exec_command,
|
||||
.dev_select = ata_std_dev_select,
|
||||
.port_disable = ata_port_disable,
|
||||
.tf_load = ata_tf_load,
|
||||
.tf_read = ata_tf_read,
|
||||
.exec_command = ata_exec_command,
|
||||
.check_status = ata_check_status,
|
||||
.dev_select = ata_std_dev_select,
|
||||
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_issue = ata_qc_issue_prot,
|
||||
.eng_timeout = ata_eng_timeout,
|
||||
.data_xfer = ixp4xx_mmio_data_xfer,
|
||||
.cable_detect = ata_cable_40wire,
|
||||
.freeze = ata_bmdma_freeze,
|
||||
.thaw = ata_bmdma_thaw,
|
||||
.error_handler = ata_bmdma_error_handler,
|
||||
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
||||
|
||||
.irq_clear = ixp4xx_irq_clear,
|
||||
.irq_on = ata_irq_on,
|
||||
.irq_ack = ata_irq_ack,
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_issue = ata_qc_issue_prot,
|
||||
.data_xfer = ixp4xx_mmio_data_xfer,
|
||||
.cable_detect = ata_cable_40wire,
|
||||
|
||||
.port_start = ata_port_start,
|
||||
.irq_handler = ata_interrupt,
|
||||
.irq_clear = ata_bmdma_irq_clear,
|
||||
.irq_on = ata_irq_on,
|
||||
.irq_ack = ata_dummy_irq_ack,
|
||||
|
||||
.phy_reset = ixp4xx_phy_reset,
|
||||
.port_start = ata_port_start,
|
||||
};
|
||||
|
||||
static void ixp4xx_setup_port(struct ata_ioports *ioaddr,
|
||||
|
@ -178,7 +171,6 @@ static __devinit int ixp4xx_pata_probe(struct platform_device *pdev)
|
|||
struct ata_host *host;
|
||||
struct ata_port *ap;
|
||||
struct ixp4xx_pata_data *data = pdev->dev.platform_data;
|
||||
int rc;
|
||||
|
||||
cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
|
@ -211,10 +203,6 @@ static __devinit int ixp4xx_pata_probe(struct platform_device *pdev)
|
|||
ap->pio_mask = 0x1f; /* PIO4 */
|
||||
ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY | ATA_FLAG_NO_ATAPI;
|
||||
|
||||
/* run in polling mode if no irq has been assigned */
|
||||
if (!irq)
|
||||
ap->flags |= ATA_FLAG_PIO_POLLING;
|
||||
|
||||
ixp4xx_setup_port(&ap->ioaddr, data);
|
||||
|
||||
dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
|
||||
|
|
|
@ -193,11 +193,11 @@ static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *i
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &jmicron_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
|
||||
.port_ops = &jmicron_ops,
|
||||
};
|
||||
|
|
|
@ -163,22 +163,22 @@ static int marvell_init_one (struct pci_dev *pdev, const struct pci_device_id *i
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &marvell_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
|
||||
.port_ops = &marvell_ops,
|
||||
};
|
||||
static const struct ata_port_info info_sata = {
|
||||
.sht = &marvell_sht,
|
||||
/* Slave possible as its magically mapped not real */
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
|
||||
.port_ops = &marvell_ops,
|
||||
};
|
||||
|
|
|
@ -94,12 +94,12 @@ static int netcell_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &netcell_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
/* Actually we don't really care about these as the
|
||||
firmware deals with it */
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* UDMA 133 */
|
||||
.udma_mask = ATA_UDMA5, /* UDMA 133 */
|
||||
.port_ops = &netcell_ops,
|
||||
};
|
||||
const struct ata_port_info *port_info[] = { &info, NULL };
|
||||
|
|
|
@ -193,7 +193,7 @@ static int ns87410_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &ns87410_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x0F,
|
||||
.port_ops = &ns87410_port_ops
|
||||
};
|
||||
|
|
|
@ -291,7 +291,7 @@ static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &oldpiix_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma1-2 */
|
||||
.port_ops = &oldpiix_pata_ops,
|
||||
|
|
|
@ -218,7 +218,7 @@ static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &opti_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &opti_port_ops
|
||||
};
|
||||
|
|
|
@ -484,14 +484,14 @@ static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info_82c700 = {
|
||||
.sht = &optidma_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &optidma_port_ops
|
||||
};
|
||||
static const struct ata_port_info info_82c700_udma = {
|
||||
.sht = &optidma_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07,
|
||||
|
|
|
@ -320,7 +320,7 @@ static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id
|
|||
static const struct ata_port_info info[3] = {
|
||||
{
|
||||
.sht = &pdc202xx_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA2,
|
||||
|
@ -328,7 +328,7 @@ static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id
|
|||
},
|
||||
{
|
||||
.sht = &pdc202xx_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
|
@ -336,7 +336,7 @@ static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id
|
|||
},
|
||||
{
|
||||
.sht = &pdc202xx_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
|
|
|
@ -139,6 +139,7 @@ static int __devinit pata_platform_probe(struct platform_device *pdev)
|
|||
struct resource *io_res, *ctl_res;
|
||||
struct ata_host *host;
|
||||
struct ata_port *ap;
|
||||
struct pata_platform_info *pp_info;
|
||||
unsigned int mmio;
|
||||
|
||||
/*
|
||||
|
@ -208,11 +209,12 @@ static int __devinit pata_platform_probe(struct platform_device *pdev)
|
|||
|
||||
ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
|
||||
|
||||
pata_platform_setup_port(&ap->ioaddr, pdev->dev.platform_data);
|
||||
pp_info = (struct pata_platform_info *)(pdev->dev.platform_data);
|
||||
pata_platform_setup_port(&ap->ioaddr, pp_info);
|
||||
|
||||
/* activate */
|
||||
return ata_host_activate(host, platform_get_irq(pdev, 0), ata_interrupt,
|
||||
0, &pata_platform_sht);
|
||||
pp_info->irq_flags, &pata_platform_sht);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -257,7 +257,7 @@ static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &radisys_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma1-2 */
|
||||
.udma_mask = 0x14, /* UDMA33/66 only */
|
||||
|
|
|
@ -133,7 +133,7 @@ static int rz1000_init_one (struct pci_dev *pdev, const struct pci_device_id *en
|
|||
static int printed_version;
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &rz1000_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &rz1000_port_ops
|
||||
};
|
||||
|
|
|
@ -185,7 +185,7 @@ static struct scsi_host_template sc1200_sht = {
|
|||
.queuecommand = ata_scsi_queuecmd,
|
||||
.can_queue = ATA_DEF_QUEUE,
|
||||
.this_id = ATA_SHT_THIS_ID,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.sg_tablesize = LIBATA_DUMB_MAX_PRD,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
.use_clustering = ATA_SHT_USE_CLUSTERING,
|
||||
|
@ -219,7 +219,7 @@ static struct ata_port_operations sc1200_port_ops = {
|
|||
.bmdma_stop = ata_bmdma_stop,
|
||||
.bmdma_status = ata_bmdma_status,
|
||||
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_prep = ata_dumb_qc_prep,
|
||||
.qc_issue = sc1200_qc_issue_prot,
|
||||
|
||||
.data_xfer = ata_data_xfer,
|
||||
|
@ -245,7 +245,7 @@ static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &sc1200_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07,
|
||||
|
|
|
@ -478,31 +478,31 @@ static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id
|
|||
static const struct ata_port_info info[4] = {
|
||||
{ /* OSB4 */
|
||||
.sht = &serverworks_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x07,
|
||||
.port_ops = &serverworks_osb4_port_ops
|
||||
}, { /* OSB4 no UDMA */
|
||||
.sht = &serverworks_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x00,
|
||||
.port_ops = &serverworks_osb4_port_ops
|
||||
}, { /* CSB5 */
|
||||
.sht = &serverworks_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &serverworks_csb_port_ops
|
||||
}, { /* CSB5 - later revisions*/
|
||||
.sht = &serverworks_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &serverworks_csb_port_ops
|
||||
}
|
||||
};
|
||||
|
|
|
@ -35,6 +35,8 @@
|
|||
#define DRV_NAME "pata_sil680"
|
||||
#define DRV_VERSION "0.4.6"
|
||||
|
||||
#define SIL680_MMIO_BAR 5
|
||||
|
||||
/**
|
||||
* sil680_selreg - return register base
|
||||
* @hwif: interface
|
||||
|
@ -293,8 +295,8 @@ static u8 sil680_init_chip(struct pci_dev *pdev)
|
|||
|
||||
pci_read_config_byte(pdev, 0x8A, &tmpbyte);
|
||||
|
||||
printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
|
||||
tmpbyte & 1, tmpbyte & 0x30);
|
||||
dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
|
||||
tmpbyte & 1, tmpbyte & 0x30);
|
||||
|
||||
switch(tmpbyte & 0x30) {
|
||||
case 0x00:
|
||||
|
@ -315,8 +317,8 @@ static u8 sil680_init_chip(struct pci_dev *pdev)
|
|||
}
|
||||
|
||||
pci_read_config_byte(pdev, 0x8A, &tmpbyte);
|
||||
printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
|
||||
tmpbyte & 1, tmpbyte & 0x30);
|
||||
dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
|
||||
tmpbyte & 1, tmpbyte & 0x30);
|
||||
|
||||
pci_write_config_byte(pdev, 0xA1, 0x72);
|
||||
pci_write_config_word(pdev, 0xA2, 0x328A);
|
||||
|
@ -339,22 +341,23 @@ static u8 sil680_init_chip(struct pci_dev *pdev)
|
|||
return tmpbyte & 0x30;
|
||||
}
|
||||
|
||||
static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
static int __devinit sil680_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &sil680_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &sil680_port_ops
|
||||
};
|
||||
static const struct ata_port_info info_slow = {
|
||||
.sht = &sil680_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sil680_port_ops
|
||||
};
|
||||
const struct ata_port_info *ppi[] = { &info, NULL };
|
||||
|
|
|
@ -732,7 +732,7 @@ static const struct ata_port_operations sis_old_ops = {
|
|||
|
||||
static const struct ata_port_info sis_info = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0,
|
||||
|
@ -740,7 +740,7 @@ static const struct ata_port_info sis_info = {
|
|||
};
|
||||
static const struct ata_port_info sis_info33 = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = ATA_UDMA2, /* UDMA 33 */
|
||||
|
@ -748,28 +748,28 @@ static const struct ata_port_info sis_info33 = {
|
|||
};
|
||||
static const struct ata_port_info sis_info66 = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = ATA_UDMA4, /* UDMA 66 */
|
||||
.port_ops = &sis_66_ops,
|
||||
};
|
||||
static const struct ata_port_info sis_info100 = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sis_100_ops,
|
||||
};
|
||||
static const struct ata_port_info sis_info100_early = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.port_ops = &sis_66_ops,
|
||||
};
|
||||
static const struct ata_port_info sis_info133 = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &sis_133_ops,
|
||||
|
@ -783,7 +783,7 @@ const struct ata_port_info sis_info133_for_sata = {
|
|||
};
|
||||
static const struct ata_port_info sis_info133_early = {
|
||||
.sht = &sis_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &sis_133_early_ops,
|
||||
|
|
|
@ -303,14 +303,14 @@ static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id
|
|||
{
|
||||
static const struct ata_port_info info_dma = {
|
||||
.sht = &sl82c105_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &sl82c105_port_ops
|
||||
};
|
||||
static const struct ata_port_info info_early = {
|
||||
.sht = &sl82c105_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.port_ops = &sl82c105_port_ops
|
||||
};
|
||||
|
|
|
@ -235,7 +235,7 @@ static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
{
|
||||
static const struct ata_port_info info = {
|
||||
.sht = &triflex_sht,
|
||||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.port_ops = &triflex_port_ops
|
||||
|
|
|
@ -471,7 +471,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7,
|
||||
.udma_mask = ATA_UDMA2,
|
||||
.port_ops = &via_port_ops
|
||||
};
|
||||
/* VIA UDMA 66 devices */
|
||||
|
@ -480,7 +480,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x1f,
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &via_port_ops
|
||||
};
|
||||
/* VIA UDMA 100 devices */
|
||||
|
@ -489,7 +489,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x3f,
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &via_port_ops
|
||||
};
|
||||
/* UDMA133 with bad AST (All current 133) */
|
||||
|
@ -498,7 +498,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f, /* FIXME: should check north bridge */
|
||||
.udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
|
||||
.port_ops = &via_port_ops
|
||||
};
|
||||
struct ata_port_info type;
|
||||
|
|
|
@ -145,32 +145,32 @@ static struct scsi_host_template adma_ata_sht = {
|
|||
.name = DRV_NAME,
|
||||
.ioctl = ata_scsi_ioctl,
|
||||
.queuecommand = ata_scsi_queuecmd,
|
||||
.can_queue = ATA_DEF_QUEUE,
|
||||
.this_id = ATA_SHT_THIS_ID,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.proc_name = DRV_NAME,
|
||||
.dma_boundary = ADMA_DMA_BOUNDARY,
|
||||
.slave_configure = ata_scsi_slave_config,
|
||||
.slave_destroy = ata_scsi_slave_destroy,
|
||||
.bios_param = ata_std_bios_param,
|
||||
.proc_name = DRV_NAME,
|
||||
.can_queue = ATA_DEF_QUEUE,
|
||||
.this_id = ATA_SHT_THIS_ID,
|
||||
.sg_tablesize = LIBATA_MAX_PRD,
|
||||
.dma_boundary = ADMA_DMA_BOUNDARY,
|
||||
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.emulated = ATA_SHT_EMULATED,
|
||||
};
|
||||
|
||||
static const struct ata_port_operations adma_ata_ops = {
|
||||
.port_disable = ata_port_disable,
|
||||
.tf_load = ata_tf_load,
|
||||
.tf_read = ata_tf_read,
|
||||
.check_status = ata_check_status,
|
||||
.check_atapi_dma = adma_check_atapi_dma,
|
||||
.exec_command = ata_exec_command,
|
||||
.check_status = ata_check_status,
|
||||
.dev_select = ata_std_dev_select,
|
||||
.phy_reset = adma_phy_reset,
|
||||
.check_atapi_dma = adma_check_atapi_dma,
|
||||
.data_xfer = ata_data_xfer,
|
||||
.qc_prep = adma_qc_prep,
|
||||
.qc_issue = adma_qc_issue,
|
||||
.eng_timeout = adma_eng_timeout,
|
||||
.data_xfer = ata_data_xfer,
|
||||
.irq_clear = adma_irq_clear,
|
||||
.irq_on = ata_irq_on,
|
||||
.irq_ack = ata_irq_ack,
|
||||
|
@ -188,7 +188,7 @@ static struct ata_port_info adma_port_info[] = {
|
|||
ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
|
||||
ATA_FLAG_PIO_POLLING,
|
||||
.pio_mask = 0x10, /* pio4 */
|
||||
.udma_mask = 0x1f, /* udma0-4 */
|
||||
.udma_mask = ATA_UDMA4,
|
||||
.port_ops = &adma_ata_ops,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -192,7 +192,7 @@ static void inic_reset_port(void __iomem *port_base)
|
|||
|
||||
static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg)
|
||||
{
|
||||
void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
|
||||
void __iomem *scr_addr = ap->ioaddr.scr_addr;
|
||||
void __iomem *addr;
|
||||
u32 val;
|
||||
|
||||
|
@ -210,7 +210,7 @@ static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg)
|
|||
|
||||
static void inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
|
||||
{
|
||||
void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
|
||||
void __iomem *scr_addr = ap->ioaddr.scr_addr;
|
||||
void __iomem *addr;
|
||||
|
||||
if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
|
||||
|
@ -594,7 +594,7 @@ static struct ata_port_info inic_port_info = {
|
|||
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &inic_port_ops
|
||||
};
|
||||
|
||||
|
|
|
@ -526,44 +526,44 @@ static const struct ata_port_info mv_port_info[] = {
|
|||
{ /* chip_504x */
|
||||
.flags = MV_COMMON_FLAGS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv5_ops,
|
||||
},
|
||||
{ /* chip_508x */
|
||||
.flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv5_ops,
|
||||
},
|
||||
{ /* chip_5080 */
|
||||
.flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv5_ops,
|
||||
},
|
||||
{ /* chip_604x */
|
||||
.flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv6_ops,
|
||||
},
|
||||
{ /* chip_608x */
|
||||
.flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
|
||||
MV_FLAG_DUAL_HC),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv6_ops,
|
||||
},
|
||||
{ /* chip_6042 */
|
||||
.flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv_iie_ops,
|
||||
},
|
||||
{ /* chip_7042 */
|
||||
.flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &mv_iie_ops,
|
||||
},
|
||||
};
|
||||
|
@ -2338,7 +2338,7 @@ static void mv_print_info(struct ata_host *host)
|
|||
struct pci_dev *pdev = to_pci_dev(host->dev);
|
||||
struct mv_host_priv *hpriv = host->private_data;
|
||||
u8 rev_id, scc;
|
||||
const char *scc_s;
|
||||
const char *scc_s, *gen;
|
||||
|
||||
/* Use this to determine the HW stepping of the chip so we know
|
||||
* what errata to workaround
|
||||
|
@ -2351,11 +2351,20 @@ static void mv_print_info(struct ata_host *host)
|
|||
else if (scc == 0x01)
|
||||
scc_s = "RAID";
|
||||
else
|
||||
scc_s = "unknown";
|
||||
scc_s = "?";
|
||||
|
||||
if (IS_GEN_I(hpriv))
|
||||
gen = "I";
|
||||
else if (IS_GEN_II(hpriv))
|
||||
gen = "II";
|
||||
else if (IS_GEN_IIE(hpriv))
|
||||
gen = "IIE";
|
||||
else
|
||||
gen = "?";
|
||||
|
||||
dev_printk(KERN_INFO, &pdev->dev,
|
||||
"%u slots %u ports %s mode IRQ via %s\n",
|
||||
(unsigned)MV_MAX_Q_DEPTH, host->n_ports,
|
||||
"Gen-%s %u slots %u ports %s mode IRQ via %s\n",
|
||||
gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
|
||||
scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
|
||||
}
|
||||
|
||||
|
|
|
@ -45,8 +45,7 @@
|
|||
#include "sata_promise.h"
|
||||
|
||||
#define DRV_NAME "sata_promise"
|
||||
#define DRV_VERSION "2.07"
|
||||
|
||||
#define DRV_VERSION "2.08"
|
||||
|
||||
enum {
|
||||
PDC_MAX_PORTS = 4,
|
||||
|
@ -94,7 +93,7 @@ enum {
|
|||
board_20319 = 2, /* FastTrak S150 TX4 */
|
||||
board_20619 = 3, /* FastTrak TX4000 */
|
||||
board_2057x = 4, /* SATAII150 Tx2plus */
|
||||
board_2057x_pata = 5, /* SATAII150 Tx2plus */
|
||||
board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
|
||||
board_40518 = 6, /* SATAII150 Tx4 */
|
||||
|
||||
PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
|
||||
|
@ -124,7 +123,6 @@ enum {
|
|||
PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
|
||||
};
|
||||
|
||||
|
||||
struct pdc_port_priv {
|
||||
u8 *pkt;
|
||||
dma_addr_t pkt_dma;
|
||||
|
@ -252,7 +250,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_SATA_PATA,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_old_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -261,7 +259,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_pata_ops,
|
||||
},
|
||||
|
||||
|
@ -271,7 +269,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_4_PORTS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_old_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -281,7 +279,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_4_PORTS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_pata_ops,
|
||||
},
|
||||
|
||||
|
@ -291,7 +289,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_sata_ops,
|
||||
},
|
||||
|
||||
|
@ -301,7 +299,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_GEN_II,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_pata_ops,
|
||||
},
|
||||
|
||||
|
@ -311,7 +309,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_sata_ops,
|
||||
},
|
||||
};
|
||||
|
@ -340,7 +338,6 @@ static const struct pci_device_id pdc_ata_pci_tbl[] = {
|
|||
{ } /* terminate list */
|
||||
};
|
||||
|
||||
|
||||
static struct pci_driver pdc_ata_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = pdc_ata_pci_tbl,
|
||||
|
@ -348,7 +345,6 @@ static struct pci_driver pdc_ata_pci_driver = {
|
|||
.remove = ata_pci_remove_one,
|
||||
};
|
||||
|
||||
|
||||
static int pdc_common_port_start(struct ata_port *ap)
|
||||
{
|
||||
struct device *dev = ap->host->dev;
|
||||
|
@ -382,7 +378,7 @@ static int pdc_sata_port_start(struct ata_port *ap)
|
|||
|
||||
/* fix up PHYMODE4 align timing */
|
||||
if (ap->flags & PDC_FLAG_GEN_II) {
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
|
||||
void __iomem *mmio = ap->ioaddr.scr_addr;
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = readl(mmio + 0x014);
|
||||
|
@ -418,7 +414,7 @@ static void pdc_reset_port(struct ata_port *ap)
|
|||
static int pdc_pata_cable_detect(struct ata_port *ap)
|
||||
{
|
||||
u8 tmp;
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
|
||||
|
||||
tmp = readb(mmio);
|
||||
if (tmp & 0x01)
|
||||
|
@ -438,7 +434,6 @@ static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
|
|||
return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
}
|
||||
|
||||
|
||||
static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
|
||||
u32 val)
|
||||
{
|
||||
|
@ -573,7 +568,7 @@ static void pdc_qc_prep(struct ata_queued_cmd *qc)
|
|||
|
||||
static void pdc_freeze(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(mmio + PDC_CTLSTAT);
|
||||
|
@ -585,7 +580,7 @@ static void pdc_freeze(struct ata_port *ap)
|
|||
|
||||
static void pdc_thaw(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr;
|
||||
u32 tmp;
|
||||
|
||||
/* clear IRQ */
|
||||
|
@ -657,8 +652,8 @@ static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
|
|||
ata_port_abort(ap);
|
||||
}
|
||||
|
||||
static inline unsigned int pdc_host_intr( struct ata_port *ap,
|
||||
struct ata_queued_cmd *qc)
|
||||
static inline unsigned int pdc_host_intr(struct ata_port *ap,
|
||||
struct ata_queued_cmd *qc)
|
||||
{
|
||||
unsigned int handled = 0;
|
||||
void __iomem *port_mmio = ap->ioaddr.cmd_addr;
|
||||
|
@ -685,10 +680,10 @@ static inline unsigned int pdc_host_intr( struct ata_port *ap,
|
|||
handled = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
default:
|
||||
ap->stats.idle_irq++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
@ -701,6 +696,18 @@ static void pdc_irq_clear(struct ata_port *ap)
|
|||
readl(mmio + PDC_INT_SEQMASK);
|
||||
}
|
||||
|
||||
static inline int pdc_is_sataii_tx4(unsigned long flags)
|
||||
{
|
||||
const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
|
||||
return (flags & mask) == mask;
|
||||
}
|
||||
|
||||
static inline unsigned int pdc_port_no_to_ata_no(unsigned int port_no, int is_sataii_tx4)
|
||||
{
|
||||
static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
|
||||
return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
|
||||
}
|
||||
|
||||
static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
|
||||
{
|
||||
struct ata_host *host = dev_instance;
|
||||
|
@ -807,7 +814,6 @@ static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
|||
ata_tf_load(ap, tf);
|
||||
}
|
||||
|
||||
|
||||
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
||||
|
@ -867,7 +873,6 @@ static void pdc_ata_setup_port(struct ata_port *ap,
|
|||
ap->ioaddr.scr_addr = scr_addr;
|
||||
}
|
||||
|
||||
|
||||
static void pdc_host_init(struct ata_host *host)
|
||||
{
|
||||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
|
@ -955,10 +960,8 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
|
||||
if (pi->flags & PDC_FLAG_SATA_PATA) {
|
||||
u8 tmp = readb(base + PDC_FLASH_CTL+1);
|
||||
if (!(tmp & 0x80)) {
|
||||
if (!(tmp & 0x80))
|
||||
ppi[n_ports++] = pi + 1;
|
||||
dev_printk(KERN_INFO, &pdev->dev, "PATA port found\n");
|
||||
}
|
||||
}
|
||||
|
||||
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
|
||||
|
@ -968,22 +971,12 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
}
|
||||
host->iomap = pcim_iomap_table(pdev);
|
||||
|
||||
is_sataii_tx4 = 0;
|
||||
if ((pi->flags & (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) == (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) {
|
||||
is_sataii_tx4 = 1;
|
||||
dev_printk(KERN_INFO, &pdev->dev, "applying SATAII TX4 port numbering workaround\n");
|
||||
}
|
||||
is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
|
||||
for (i = 0; i < host->n_ports; i++) {
|
||||
static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
|
||||
int ata_nr;
|
||||
|
||||
ata_nr = i;
|
||||
if (is_sataii_tx4)
|
||||
ata_nr = sataii_tx4_port_remap[i];
|
||||
|
||||
unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
|
||||
pdc_ata_setup_port(host->ports[i],
|
||||
base + 0x200 + ata_nr * 0x80,
|
||||
base + 0x400 + ata_nr * 0x100);
|
||||
base + 0x200 + ata_no * 0x80,
|
||||
base + 0x400 + ata_no * 0x100);
|
||||
}
|
||||
|
||||
/* initialize adapter */
|
||||
|
@ -1002,19 +995,16 @@ static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
|
|||
&pdc_ata_sht);
|
||||
}
|
||||
|
||||
|
||||
static int __init pdc_ata_init(void)
|
||||
{
|
||||
return pci_register_driver(&pdc_ata_pci_driver);
|
||||
}
|
||||
|
||||
|
||||
static void __exit pdc_ata_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&pdc_ata_pci_driver);
|
||||
}
|
||||
|
||||
|
||||
MODULE_AUTHOR("Jeff Garzik");
|
||||
MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
@ -176,7 +176,7 @@ static const struct ata_port_info qs_port_info[] = {
|
|||
//FIXME ATA_FLAG_SRST |
|
||||
ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
|
||||
.pio_mask = 0x10, /* pio4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &qs_ata_ops,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -218,7 +218,7 @@ static const struct ata_port_info sil_port_info[] = {
|
|||
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sil_ops,
|
||||
},
|
||||
/* sil_3112_no_sata_irq */
|
||||
|
@ -227,7 +227,7 @@ static const struct ata_port_info sil_port_info[] = {
|
|||
SIL_FLAG_NO_SATA_IRQ,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sil_ops,
|
||||
},
|
||||
/* sil_3512 */
|
||||
|
@ -235,7 +235,7 @@ static const struct ata_port_info sil_port_info[] = {
|
|||
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sil_ops,
|
||||
},
|
||||
/* sil_3114 */
|
||||
|
@ -243,7 +243,7 @@ static const struct ata_port_info sil_port_info[] = {
|
|||
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5,
|
||||
.port_ops = &sil_ops,
|
||||
},
|
||||
};
|
||||
|
@ -262,8 +262,9 @@ static const struct {
|
|||
unsigned long sfis_cfg; /* SATA FIS reception config register */
|
||||
} sil_port[] = {
|
||||
/* port 0 ... */
|
||||
{ 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
|
||||
{ 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
|
||||
/* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
|
||||
{ 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
|
||||
{ 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
|
||||
{ 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
|
||||
{ 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
|
||||
/* ... port 3 */
|
||||
|
|
|
@ -426,7 +426,7 @@ static const struct ata_port_info sil24_port_info[] = {
|
|||
SIL24_FLAG_PCIX_IRQ_WOC,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
||||
.port_ops = &sil24_ops,
|
||||
},
|
||||
/* sil_3132 */
|
||||
|
@ -434,7 +434,7 @@ static const struct ata_port_info sil24_port_info[] = {
|
|||
.flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
||||
.port_ops = &sil24_ops,
|
||||
},
|
||||
/* sil_3131/sil_3531 */
|
||||
|
@ -442,7 +442,7 @@ static const struct ata_port_info sil24_port_info[] = {
|
|||
.flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x3f, /* udma0-5 */
|
||||
.udma_mask = ATA_UDMA5, /* udma0-5 */
|
||||
.port_ops = &sil24_ops,
|
||||
},
|
||||
};
|
||||
|
@ -888,7 +888,7 @@ static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
|
|||
if (status & (1 << i)) {
|
||||
struct ata_port *ap = host->ports[i];
|
||||
if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
|
||||
sil24_host_intr(host->ports[i]);
|
||||
sil24_host_intr(ap);
|
||||
handled++;
|
||||
} else
|
||||
printk(KERN_ERR DRV_NAME
|
||||
|
|
|
@ -133,7 +133,7 @@ static const struct ata_port_info sis_port_info = {
|
|||
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x7,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &sis_ops,
|
||||
};
|
||||
|
||||
|
|
|
@ -107,7 +107,7 @@ static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
|
|||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return 0xffffffffU;
|
||||
return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
}
|
||||
|
||||
|
||||
|
@ -116,7 +116,7 @@ static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
|
|||
{
|
||||
if (sc_reg > SCR_CONTROL)
|
||||
return;
|
||||
writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
||||
}
|
||||
|
||||
|
||||
|
@ -197,7 +197,8 @@ static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
|
|||
struct ata_port *ap = qc->ap;
|
||||
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
||||
u8 dmactl;
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
|
||||
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
||||
|
||||
/* load PRD table addr. */
|
||||
mb(); /* make sure PRD table writes are visible to controller */
|
||||
writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
|
||||
|
@ -225,7 +226,7 @@ static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
|
|||
static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
|
||||
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
||||
u8 dmactl;
|
||||
|
||||
/* start host DMA transaction */
|
||||
|
@ -253,7 +254,7 @@ static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
|
|||
|
||||
static u8 k2_stat_check_status(struct ata_port *ap)
|
||||
{
|
||||
return readl((void __iomem *) ap->ioaddr.status_addr);
|
||||
return readl(ap->ioaddr.status_addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_OF
|
||||
|
@ -360,7 +361,7 @@ static const struct ata_port_info k2_port_info[] = {
|
|||
ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &k2_sata_ops,
|
||||
},
|
||||
/* board_svw8 */
|
||||
|
@ -370,7 +371,7 @@ static const struct ata_port_info k2_port_info[] = {
|
|||
K2_FLAG_SATA_8_PORTS,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &k2_sata_ops,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -30,6 +30,54 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
Theory of operation
|
||||
-------------------
|
||||
|
||||
The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
|
||||
engine, DIMM memory, and four ATA engines (one per SATA port).
|
||||
Data is copied to/from DIMM memory by the HDMA engine, before
|
||||
handing off to one (or more) of the ATA engines. The ATA
|
||||
engines operate solely on DIMM memory.
|
||||
|
||||
The SX4 behaves like a PATA chip, with no SATA controls or
|
||||
knowledge whatsoever, leading to the presumption that
|
||||
PATA<->SATA bridges exist on SX4 boards, external to the
|
||||
PDC20621 chip itself.
|
||||
|
||||
The chip is quite capable, supporting an XOR engine and linked
|
||||
hardware commands (permits a string to transactions to be
|
||||
submitted and waited-on as a single unit), and an optional
|
||||
microprocessor.
|
||||
|
||||
The limiting factor is largely software. This Linux driver was
|
||||
written to multiplex the single HDMA engine to copy disk
|
||||
transactions into a fixed DIMM memory space, from where an ATA
|
||||
engine takes over. As a result, each WRITE looks like this:
|
||||
|
||||
submit HDMA packet to hardware
|
||||
hardware copies data from system memory to DIMM
|
||||
hardware raises interrupt
|
||||
|
||||
submit ATA packet to hardware
|
||||
hardware executes ATA WRITE command, w/ data in DIMM
|
||||
hardware raises interrupt
|
||||
|
||||
and each READ looks like this:
|
||||
|
||||
submit ATA packet to hardware
|
||||
hardware executes ATA READ command, w/ data in DIMM
|
||||
hardware raises interrupt
|
||||
|
||||
submit HDMA packet to hardware
|
||||
hardware copies data from DIMM to system memory
|
||||
hardware raises interrupt
|
||||
|
||||
This is a very slow, lock-step way of doing things that can
|
||||
certainly be improved by motivated kernel hackers.
|
||||
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
|
@ -58,6 +106,8 @@ enum {
|
|||
PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
|
||||
PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
|
||||
|
||||
PDC_CTLSTAT = 0x60, /* IDEn control / status */
|
||||
|
||||
PDC_20621_SEQCTL = 0x400,
|
||||
PDC_20621_SEQMASK = 0x480,
|
||||
PDC_20621_GENERAL_CTL = 0x484,
|
||||
|
@ -87,48 +137,60 @@ enum {
|
|||
|
||||
board_20621 = 0, /* FastTrak S150 SX4 */
|
||||
|
||||
PDC_RESET = (1 << 11), /* HDMA reset */
|
||||
PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
|
||||
PDC_RESET = (1 << 11), /* HDMA/ATA reset */
|
||||
PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
|
||||
|
||||
PDC_MAX_HDMA = 32,
|
||||
PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
|
||||
|
||||
PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
|
||||
PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
|
||||
PDC_MAX_DIMM_MODULE = 0x02,
|
||||
PDC_I2C_CONTROL_OFFSET = 0x48,
|
||||
PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
|
||||
PDC_DIMM0_CONTROL_OFFSET = 0x80,
|
||||
PDC_DIMM1_CONTROL_OFFSET = 0x84,
|
||||
PDC_SDRAM_CONTROL_OFFSET = 0x88,
|
||||
PDC_I2C_WRITE = 0x00000000,
|
||||
PDC_I2C_READ = 0x00000040,
|
||||
PDC_I2C_START = 0x00000080,
|
||||
PDC_I2C_MASK_INT = 0x00000020,
|
||||
PDC_I2C_COMPLETE = 0x00010000,
|
||||
PDC_I2C_NO_ACK = 0x00100000,
|
||||
PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
|
||||
PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
|
||||
PDC_DIMM_SPD_ROW_NUM = 3,
|
||||
PDC_DIMM_SPD_COLUMN_NUM = 4,
|
||||
PDC_DIMM_SPD_MODULE_ROW = 5,
|
||||
PDC_DIMM_SPD_TYPE = 11,
|
||||
PDC_DIMM_SPD_FRESH_RATE = 12,
|
||||
PDC_DIMM_SPD_BANK_NUM = 17,
|
||||
PDC_DIMM_SPD_CAS_LATENCY = 18,
|
||||
PDC_DIMM_SPD_ATTRIBUTE = 21,
|
||||
PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
|
||||
PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
|
||||
PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
|
||||
PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
|
||||
PDC_DIMM_SPD_SYSTEM_FREQ = 126,
|
||||
PDC_CTL_STATUS = 0x08,
|
||||
PDC_DIMM_WINDOW_CTLR = 0x0C,
|
||||
PDC_TIME_CONTROL = 0x3C,
|
||||
PDC_TIME_PERIOD = 0x40,
|
||||
PDC_TIME_COUNTER = 0x44,
|
||||
PDC_GENERAL_CTLR = 0x484,
|
||||
PCI_PLL_INIT = 0x8A531824,
|
||||
PCI_X_TCOUNT = 0xEE1E5CFF
|
||||
PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
|
||||
PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
|
||||
PDC_I2C_CONTROL = 0x48,
|
||||
PDC_I2C_ADDR_DATA = 0x4C,
|
||||
PDC_DIMM0_CONTROL = 0x80,
|
||||
PDC_DIMM1_CONTROL = 0x84,
|
||||
PDC_SDRAM_CONTROL = 0x88,
|
||||
PDC_I2C_WRITE = 0, /* master -> slave */
|
||||
PDC_I2C_READ = (1 << 6), /* master <- slave */
|
||||
PDC_I2C_START = (1 << 7), /* start I2C proto */
|
||||
PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
|
||||
PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
|
||||
PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
|
||||
PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
|
||||
PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
|
||||
PDC_DIMM_SPD_ROW_NUM = 3,
|
||||
PDC_DIMM_SPD_COLUMN_NUM = 4,
|
||||
PDC_DIMM_SPD_MODULE_ROW = 5,
|
||||
PDC_DIMM_SPD_TYPE = 11,
|
||||
PDC_DIMM_SPD_FRESH_RATE = 12,
|
||||
PDC_DIMM_SPD_BANK_NUM = 17,
|
||||
PDC_DIMM_SPD_CAS_LATENCY = 18,
|
||||
PDC_DIMM_SPD_ATTRIBUTE = 21,
|
||||
PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
|
||||
PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
|
||||
PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
|
||||
PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
|
||||
PDC_DIMM_SPD_SYSTEM_FREQ = 126,
|
||||
PDC_CTL_STATUS = 0x08,
|
||||
PDC_DIMM_WINDOW_CTLR = 0x0C,
|
||||
PDC_TIME_CONTROL = 0x3C,
|
||||
PDC_TIME_PERIOD = 0x40,
|
||||
PDC_TIME_COUNTER = 0x44,
|
||||
PDC_GENERAL_CTLR = 0x484,
|
||||
PCI_PLL_INIT = 0x8A531824,
|
||||
PCI_X_TCOUNT = 0xEE1E5CFF,
|
||||
|
||||
/* PDC_TIME_CONTROL bits */
|
||||
PDC_TIMER_BUZZER = (1 << 10),
|
||||
PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
|
||||
PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
|
||||
PDC_TIMER_ENABLE = (1 << 7),
|
||||
PDC_TIMER_MASK_INT = (1 << 5),
|
||||
PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
|
||||
PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
|
||||
PDC_TIMER_ENABLE |
|
||||
PDC_TIMER_MASK_INT,
|
||||
};
|
||||
|
||||
|
||||
|
@ -217,7 +279,7 @@ static const struct ata_port_info pdc_port_info[] = {
|
|||
ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &pdc_20621_ops,
|
||||
},
|
||||
|
||||
|
@ -999,17 +1061,17 @@ static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
|
|||
i2creg |= subaddr << 16;
|
||||
|
||||
/* Set the device and subaddress */
|
||||
writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
||||
readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
||||
writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
|
||||
readl(mmio + PDC_I2C_ADDR_DATA);
|
||||
|
||||
/* Write Control to perform read operation, mask int */
|
||||
writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
|
||||
mmio + PDC_I2C_CONTROL_OFFSET);
|
||||
mmio + PDC_I2C_CONTROL);
|
||||
|
||||
for (count = 0; count <= 1000; count ++) {
|
||||
status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
|
||||
status = readl(mmio + PDC_I2C_CONTROL);
|
||||
if (status & PDC_I2C_COMPLETE) {
|
||||
status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
||||
status = readl(mmio + PDC_I2C_ADDR_DATA);
|
||||
break;
|
||||
} else if (count == 1000)
|
||||
return 0;
|
||||
|
@ -1099,8 +1161,8 @@ static int pdc20621_prog_dimm0(struct ata_host *host)
|
|||
data |= (((size / 16) - 1) << 16);
|
||||
data |= (0 << 23);
|
||||
data |= 8;
|
||||
writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
|
||||
readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
|
||||
writel(data, mmio + PDC_DIMM0_CONTROL);
|
||||
readl(mmio + PDC_DIMM0_CONTROL);
|
||||
return size;
|
||||
}
|
||||
|
||||
|
@ -1122,27 +1184,27 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
|
|||
*/
|
||||
|
||||
data = 0x022259F1;
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
readl(mmio + PDC_SDRAM_CONTROL);
|
||||
|
||||
/* Turn on for ECC */
|
||||
pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
|
||||
PDC_DIMM_SPD_TYPE, &spd0);
|
||||
if (spd0 == 0x02) {
|
||||
data |= (0x01 << 16);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
readl(mmio + PDC_SDRAM_CONTROL);
|
||||
printk(KERN_ERR "Local DIMM ECC Enabled\n");
|
||||
}
|
||||
|
||||
/* DIMM Initialization Select/Enable (bit 18/19) */
|
||||
data &= (~(1<<18));
|
||||
data |= (1<<19);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
writel(data, mmio + PDC_SDRAM_CONTROL);
|
||||
|
||||
error = 1;
|
||||
for (i = 1; i <= 10; i++) { /* polling ~5 secs */
|
||||
data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
||||
data = readl(mmio + PDC_SDRAM_CONTROL);
|
||||
if (!(data & (1<<19))) {
|
||||
error = 0;
|
||||
break;
|
||||
|
@ -1176,7 +1238,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
|
|||
VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
|
||||
|
||||
/* Enable timer */
|
||||
writel(0x00001a0, mmio + PDC_TIME_CONTROL);
|
||||
writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
|
||||
readl(mmio + PDC_TIME_CONTROL);
|
||||
|
||||
/* Wait 3 seconds */
|
||||
|
|
|
@ -129,7 +129,7 @@ static const struct ata_port_info uli_port_info = {
|
|||
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
|
||||
ATA_FLAG_IGN_SIMPLEX,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &uli_ops,
|
||||
};
|
||||
|
||||
|
|
|
@ -223,7 +223,7 @@ static const struct ata_port_info vt6420_port_info = {
|
|||
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &vt6420_sata_ops,
|
||||
};
|
||||
|
||||
|
@ -231,7 +231,7 @@ static struct ata_port_info vt6421_sport_info = {
|
|||
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &vt6421_sata_ops,
|
||||
};
|
||||
|
||||
|
@ -239,7 +239,7 @@ static struct ata_port_info vt6421_pport_info = {
|
|||
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &vt6421_pata_ops,
|
||||
};
|
||||
|
||||
|
@ -303,9 +303,7 @@ static int vt6420_prereset(struct ata_port *ap, unsigned long deadline)
|
|||
if (!(ap->pflags & ATA_PFLAG_LOADING))
|
||||
goto skip_scr;
|
||||
|
||||
/* Resume phy. This is the old resume sequence from
|
||||
* __sata_phy_reset().
|
||||
*/
|
||||
/* Resume phy. This is the old SATA resume sequence */
|
||||
svia_scr_write(ap, SCR_CONTROL, 0x300);
|
||||
svia_scr_read(ap, SCR_CONTROL); /* flush */
|
||||
|
||||
|
|
|
@ -371,7 +371,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
|
|||
ATA_FLAG_MMIO,
|
||||
.pio_mask = 0x1f,
|
||||
.mwdma_mask = 0x07,
|
||||
.udma_mask = 0x7f,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &vsc_sata_ops,
|
||||
};
|
||||
const struct ata_port_info *ppi[] = { &pi, NULL };
|
||||
|
|
|
@ -126,6 +126,7 @@ enum {
|
|||
ATA_REG_IRQ = ATA_REG_NSECT,
|
||||
|
||||
/* ATA device commands */
|
||||
ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */
|
||||
ATA_CMD_CHK_POWER = 0xE5, /* check power mode */
|
||||
ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */
|
||||
ATA_CMD_IDLE = 0xE3, /* place in idle power mode */
|
||||
|
|
|
@ -116,6 +116,7 @@ static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
|
|||
enum {
|
||||
/* various global constants */
|
||||
LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
|
||||
LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4, /* Worst case */
|
||||
ATA_MAX_PORTS = 8,
|
||||
ATA_DEF_QUEUE = 1,
|
||||
/* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
|
||||
|
@ -136,6 +137,8 @@ enum {
|
|||
ATA_DFLAG_CDB_INTR = (1 << 2), /* device asserts INTRQ when ready for CDB */
|
||||
ATA_DFLAG_NCQ = (1 << 3), /* device supports NCQ */
|
||||
ATA_DFLAG_FLUSH_EXT = (1 << 4), /* do FLUSH_EXT instead of FLUSH */
|
||||
ATA_DFLAG_ACPI_PENDING = (1 << 5), /* ACPI resume action pending */
|
||||
ATA_DFLAG_ACPI_FAILED = (1 << 6), /* ACPI on devcfg has failed */
|
||||
ATA_DFLAG_CFG_MASK = (1 << 8) - 1,
|
||||
|
||||
ATA_DFLAG_PIO = (1 << 8), /* device limited to PIO mode */
|
||||
|
@ -196,6 +199,7 @@ enum {
|
|||
ATA_PFLAG_FLUSH_PORT_TASK = (1 << 16), /* flush port task */
|
||||
ATA_PFLAG_SUSPENDED = (1 << 17), /* port is suspended (power) */
|
||||
ATA_PFLAG_PM_PENDING = (1 << 18), /* PM operation pending */
|
||||
ATA_PFLAG_GTM_VALID = (1 << 19), /* acpi_gtm data valid */
|
||||
|
||||
/* struct ata_queued_cmd flags */
|
||||
ATA_QCFLAG_ACTIVE = (1 << 0), /* cmd not yet ack'd to scsi lyer */
|
||||
|
@ -363,6 +367,9 @@ struct ata_host {
|
|||
void *private_data;
|
||||
const struct ata_port_operations *ops;
|
||||
unsigned long flags;
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
acpi_handle acpi_handle;
|
||||
#endif
|
||||
struct ata_port *simplex_claimed; /* channel owning the DMA */
|
||||
struct ata_port *ports[0];
|
||||
};
|
||||
|
@ -429,6 +436,9 @@ struct ata_device {
|
|||
unsigned int devno; /* 0 or 1 */
|
||||
unsigned long flags; /* ATA_DFLAG_xxx */
|
||||
struct scsi_device *sdev; /* attached SCSI device */
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
acpi_handle acpi_handle;
|
||||
#endif
|
||||
/* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
|
||||
u64 n_sectors; /* size of device, if ATA */
|
||||
unsigned int class; /* ATA_DEV_xxx */
|
||||
|
@ -457,10 +467,6 @@ struct ata_device {
|
|||
struct ata_ering ering;
|
||||
int spdn_cnt;
|
||||
unsigned int horkage; /* List of broken features */
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
/* ACPI objects info */
|
||||
acpi_handle obj_handle;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Offset into struct ata_device. Fields above it are maintained
|
||||
|
@ -489,6 +495,17 @@ struct ata_eh_context {
|
|||
unsigned int did_probe_mask;
|
||||
};
|
||||
|
||||
struct ata_acpi_drive
|
||||
{
|
||||
u32 pio;
|
||||
u32 dma;
|
||||
} __packed;
|
||||
|
||||
struct ata_acpi_gtm {
|
||||
struct ata_acpi_drive drive[2];
|
||||
u32 flags;
|
||||
} __packed;
|
||||
|
||||
struct ata_port {
|
||||
struct Scsi_Host *scsi_host; /* our co-allocated scsi host */
|
||||
const struct ata_port_operations *ops;
|
||||
|
@ -549,6 +566,10 @@ struct ata_port {
|
|||
|
||||
void *private_data;
|
||||
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
acpi_handle acpi_handle;
|
||||
struct ata_acpi_gtm acpi_gtm;
|
||||
#endif
|
||||
u8 sector_buf[ATA_SECT_SIZE]; /* owned by EH */
|
||||
};
|
||||
|
||||
|
@ -758,6 +779,7 @@ extern void ata_data_xfer(struct ata_device *adev, unsigned char *buf,
|
|||
unsigned int buflen, int write_data);
|
||||
extern void ata_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
|
||||
unsigned int buflen, int write_data);
|
||||
extern void ata_dumb_qc_prep(struct ata_queued_cmd *qc);
|
||||
extern void ata_qc_prep(struct ata_queued_cmd *qc);
|
||||
extern void ata_noop_qc_prep(struct ata_queued_cmd *qc);
|
||||
extern unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
|
||||
|
|
|
@ -8,6 +8,11 @@ struct pata_platform_info {
|
|||
* spacing used by ata_std_ports().
|
||||
*/
|
||||
unsigned int ioport_shift;
|
||||
/*
|
||||
* Indicate platform specific irq types and initial
|
||||
* IRQ flags when call request_irq()
|
||||
*/
|
||||
unsigned int irq_flags;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_PATA_PLATFORM_H */
|
||||
|
|
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