agp/intel: Rename intel-gtt symbols
Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377 ("drm/i915/gt: Split
intel-gtt functions by arch") moved way too much
inside gt/intel_gt_gmch.c, even the functions that don't callout to this
module. Rename the symbols to make the separation clear.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617230559.2109427-1-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi
Родитель
0dc987b699
Коммит
64e06652e3
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@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
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writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
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}
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bool intel_enable_gtt(void)
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bool intel_gmch_enable_gtt(void)
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{
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u8 __iomem *reg;
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@ -787,7 +787,7 @@ bool intel_enable_gtt(void)
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return true;
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}
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EXPORT_SYMBOL(intel_enable_gtt);
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EXPORT_SYMBOL(intel_gmch_enable_gtt);
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static int i830_setup(void)
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{
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@ -821,8 +821,8 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
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static int intel_fake_agp_configure(void)
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{
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if (!intel_enable_gtt())
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return -EIO;
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if (!intel_gmch_enable_gtt())
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return -EIO;
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intel_private.clear_fake_agp = true;
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agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
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@ -844,20 +844,20 @@ static bool i830_check_flags(unsigned int flags)
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return false;
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}
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void intel_gtt_insert_page(dma_addr_t addr,
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unsigned int pg,
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unsigned int flags)
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void intel_gmch_gtt_insert_page(dma_addr_t addr,
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unsigned int pg,
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unsigned int flags)
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{
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intel_private.driver->write_entry(addr, pg, flags);
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readl(intel_private.gtt + pg);
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if (intel_private.driver->chipset_flush)
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intel_private.driver->chipset_flush();
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}
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EXPORT_SYMBOL(intel_gtt_insert_page);
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EXPORT_SYMBOL(intel_gmch_gtt_insert_page);
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void intel_gtt_insert_sg_entries(struct sg_table *st,
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unsigned int pg_start,
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unsigned int flags)
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void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
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unsigned int pg_start,
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unsigned int flags)
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{
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struct scatterlist *sg;
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unsigned int len, m;
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@ -879,13 +879,13 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
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if (intel_private.driver->chipset_flush)
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intel_private.driver->chipset_flush();
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}
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EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
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EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static void intel_gtt_insert_pages(unsigned int first_entry,
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unsigned int num_entries,
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struct page **pages,
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unsigned int flags)
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static void intel_gmch_gtt_insert_pages(unsigned int first_entry,
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unsigned int num_entries,
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struct page **pages,
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unsigned int flags)
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{
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int i, j;
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@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
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if (intel_private.clear_fake_agp) {
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int start = intel_private.stolen_size / PAGE_SIZE;
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int end = intel_private.gtt_mappable_entries;
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intel_gtt_clear_range(start, end - start);
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intel_gmch_gtt_clear_range(start, end - start);
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intel_private.clear_fake_agp = false;
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}
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@ -934,12 +934,12 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
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if (ret != 0)
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return ret;
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intel_gtt_insert_sg_entries(&st, pg_start, type);
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intel_gmch_gtt_insert_sg_entries(&st, pg_start, type);
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mem->sg_list = st.sgl;
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mem->num_sg = st.nents;
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} else
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intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
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type);
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intel_gmch_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
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type);
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out:
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ret = 0;
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@ -949,7 +949,7 @@ out_err:
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}
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#endif
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
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void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
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{
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unsigned int i;
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@ -959,7 +959,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
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}
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wmb();
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}
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EXPORT_SYMBOL(intel_gtt_clear_range);
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EXPORT_SYMBOL(intel_gmch_gtt_clear_range);
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int intel_fake_agp_remove_entries(struct agp_memory *mem,
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@ -968,7 +968,7 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem,
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if (mem->page_count == 0)
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return 0;
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intel_gtt_clear_range(pg_start, mem->page_count);
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intel_gmch_gtt_clear_range(pg_start, mem->page_count);
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if (intel_private.needs_dmar) {
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intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
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@ -1431,22 +1431,22 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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}
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EXPORT_SYMBOL(intel_gmch_probe);
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void intel_gtt_get(u64 *gtt_total,
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phys_addr_t *mappable_base,
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resource_size_t *mappable_end)
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void intel_gmch_gtt_get(u64 *gtt_total,
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phys_addr_t *mappable_base,
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resource_size_t *mappable_end)
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{
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*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
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*mappable_base = intel_private.gma_bus_addr;
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*mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
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}
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EXPORT_SYMBOL(intel_gtt_get);
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EXPORT_SYMBOL(intel_gmch_gtt_get);
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void intel_gtt_chipset_flush(void)
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void intel_gmch_gtt_flush(void)
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{
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if (intel_private.driver->chipset_flush)
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intel_private.driver->chipset_flush();
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}
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EXPORT_SYMBOL(intel_gtt_chipset_flush);
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EXPORT_SYMBOL(intel_gmch_gtt_flush);
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void intel_gmch_remove(void)
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{
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@ -134,7 +134,7 @@ static void gen5_ggtt_insert_page(struct i915_address_space *vm,
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unsigned int flags = (cache_level == I915_CACHE_NONE) ?
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
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intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
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}
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static void gen6_ggtt_insert_page(struct i915_address_space *vm,
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@ -175,8 +175,8 @@ static void gen5_ggtt_insert_entries(struct i915_address_space *vm,
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unsigned int flags = (cache_level == I915_CACHE_NONE) ?
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
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flags);
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intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
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flags);
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}
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/*
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@ -306,18 +306,18 @@ static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
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void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt)
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{
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intel_gtt_chipset_flush();
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intel_gmch_gtt_flush();
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}
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static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
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{
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intel_gtt_chipset_flush();
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intel_gmch_gtt_flush();
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}
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static void gen5_ggtt_clear_range(struct i915_address_space *vm,
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u64 start, u64 length)
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{
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intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
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intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
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}
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static void gen6_ggtt_clear_range(struct i915_address_space *vm,
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@ -494,7 +494,7 @@ int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
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return -EIO;
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}
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intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
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intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
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ggtt->gmadr =
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(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
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@ -647,7 +647,7 @@ int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
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int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
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{
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if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
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if (GRAPHICS_VER(i915) < 6 && !intel_gmch_enable_gtt())
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return -EIO;
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return 0;
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@ -10,24 +10,24 @@ struct agp_bridge_data;
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struct pci_dev;
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struct sg_table;
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void intel_gtt_get(u64 *gtt_total,
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phys_addr_t *mappable_base,
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resource_size_t *mappable_end);
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void intel_gmch_gtt_get(u64 *gtt_total,
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phys_addr_t *mappable_base,
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resource_size_t *mappable_end);
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int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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struct agp_bridge_data *bridge);
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void intel_gmch_remove(void);
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bool intel_enable_gtt(void);
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bool intel_gmch_enable_gtt(void);
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void intel_gtt_chipset_flush(void);
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void intel_gtt_insert_page(dma_addr_t addr,
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unsigned int pg,
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unsigned int flags);
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void intel_gtt_insert_sg_entries(struct sg_table *st,
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unsigned int pg_start,
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unsigned int flags);
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
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void intel_gmch_gtt_flush(void);
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void intel_gmch_gtt_insert_page(dma_addr_t addr,
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unsigned int pg,
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unsigned int flags);
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void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,
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unsigned int pg_start,
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unsigned int flags);
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void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
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/* Special gtt memory types */
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#define AGP_DCACHE_MEMORY 1
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