From 9e9622d1a064705181bea0600ea9eacd95adab7f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 11:47:44 +0900 Subject: [PATCH 01/27] serial: sh-sci: remove SCIF code in sci_rxd_in() Since sci_rxd_in() is used by SCI only, clean up the header file by killing off code dealing with SCIF ports and their register definitions. Also introduce a default sci_rxd_in() function which can be shared by all SCIF-only processors. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/serial/sh-sci.h | 220 +--------------------------------------- 1 file changed, 1 insertion(+), 219 deletions(-) diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 0efcded59ae6..f7d2589926d2 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -518,34 +518,6 @@ static inline int sci_rxd_in(struct uart_port *port) { if (port->mapbase == 0xfffffe80) return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ - if (port->mapbase == 0xa4000150) - return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xa4000140) - return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7705) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == SCIF0) - return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ - if (port->mapbase == SCIF2) - return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) -static inline int sci_rxd_in(struct uart_port *port) -{ - return sci_in(port,SCxSR)&0x0010 ? 1 : 0; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xa4430000) - return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; - else if (port->mapbase == 0xa4438000) - return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; return 1; } #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ @@ -558,207 +530,17 @@ static inline int sci_rxd_in(struct uart_port *port) { if (port->mapbase == 0xffe00000) return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ - if (port->mapbase == 0xffe80000) - return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ return 1; } -#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe80000) - return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7757) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xfe4b0000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; - if (port->mapbase == 0xfe4c0000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; - if (port->mapbase == 0xfe4d0000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7760) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xfe600000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfe610000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfe620000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7343) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe00000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe10000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe20000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe30000) - return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7366) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe00000) - return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7722) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe00000) - return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ - if (port->mapbase == 0xffe10000) - return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ - if (port->mapbase == 0xffe20000) - return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ - - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7723) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe00000) - return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ - if (port->mapbase == 0xffe10000) - return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ - if (port->mapbase == 0xffe20000) - return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ - if (port->mapbase == 0xa4e30000) - return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ - if (port->mapbase == 0xa4e40000) - return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ - if (port->mapbase == 0xa4e50000) - return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7724) -# define SCFSR 0x0010 -# define SCASSR 0x0014 -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->type == PORT_SCIF) - return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; - if (port->type == PORT_SCIFA) - return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) -static inline int sci_rxd_in(struct uart_port *port) -{ - return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ -} #elif defined(__H8300H__) || defined(__H8300S__) static inline int sci_rxd_in(struct uart_port *port) { int ch = (port->mapbase - SMR0) >> 3; return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; } -#elif defined(CONFIG_CPU_SUBTYPE_SH7763) +#else /* default case for non-SCI processors */ static inline int sci_rxd_in(struct uart_port *port) { - if (port->mapbase == 0xffe00000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe08000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe10000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ - - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7770) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xff923000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xff924000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xff925000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffe00000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffe10000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ - defined(CONFIG_CPU_SUBTYPE_SH7786) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffea0000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffeb0000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffec0000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffed0000) - return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffee0000) - return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffef0000) - return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ - defined(CONFIG_CPU_SUBTYPE_SH7203) || \ - defined(CONFIG_CPU_SUBTYPE_SH7206) || \ - defined(CONFIG_CPU_SUBTYPE_SH7263) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xfffe8000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffe8800) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffe9000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffe9800) - return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ -#if defined(CONFIG_CPU_SUBTYPE_SH7201) - if (port->mapbase == 0xfffeA000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffeA800) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffeB000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xfffeB800) - return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ -#endif - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SH7619) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xf8400000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xf8410000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xf8420000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - return 1; -} -#elif defined(CONFIG_CPU_SUBTYPE_SHX3) -static inline int sci_rxd_in(struct uart_port *port) -{ - if (port->mapbase == 0xffc30000) - return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffc40000) - return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffc50000) - return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ - if (port->mapbase == 0xffc60000) - return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ return 1; } #endif From c793c1b0c8ea11b46caf5a532752214b27a2df42 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:14:49 +0000 Subject: [PATCH 02/27] ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/Kconfig | 7 + arch/arm/Makefile | 1 + arch/arm/mach-shmobile/Kconfig | 53 ++++ arch/arm/mach-shmobile/Makefile | 12 + arch/arm/mach-shmobile/Makefile.boot | 9 + arch/arm/mach-shmobile/board-g3evm.c | 127 +++++++++ arch/arm/mach-shmobile/clock-sh7367.c | 89 +++++++ arch/arm/mach-shmobile/include/mach/clkdev.h | 7 + arch/arm/mach-shmobile/include/mach/common.h | 11 + arch/arm/mach-shmobile/include/mach/dma.h | 1 + .../mach-shmobile/include/mach/entry-macro.S | 39 +++ arch/arm/mach-shmobile/include/mach/gpio.h | 1 + .../arm/mach-shmobile/include/mach/hardware.h | 7 + arch/arm/mach-shmobile/include/mach/io.h | 9 + arch/arm/mach-shmobile/include/mach/irqs.h | 10 + arch/arm/mach-shmobile/include/mach/memory.h | 7 + arch/arm/mach-shmobile/include/mach/system.h | 14 + arch/arm/mach-shmobile/include/mach/timex.h | 6 + .../mach-shmobile/include/mach/uncompress.h | 21 ++ arch/arm/mach-shmobile/include/mach/vmalloc.h | 6 + arch/arm/mach-shmobile/setup-sh7367.c | 241 ++++++++++++++++++ arch/arm/mach-shmobile/timer.c | 46 ++++ 22 files changed, 724 insertions(+) create mode 100644 arch/arm/mach-shmobile/Kconfig create mode 100644 arch/arm/mach-shmobile/Makefile create mode 100644 arch/arm/mach-shmobile/Makefile.boot create mode 100644 arch/arm/mach-shmobile/board-g3evm.c create mode 100644 arch/arm/mach-shmobile/clock-sh7367.c create mode 100644 arch/arm/mach-shmobile/include/mach/clkdev.h create mode 100644 arch/arm/mach-shmobile/include/mach/common.h create mode 100644 arch/arm/mach-shmobile/include/mach/dma.h create mode 100644 arch/arm/mach-shmobile/include/mach/entry-macro.S create mode 100644 arch/arm/mach-shmobile/include/mach/gpio.h create mode 100644 arch/arm/mach-shmobile/include/mach/hardware.h create mode 100644 arch/arm/mach-shmobile/include/mach/io.h create mode 100644 arch/arm/mach-shmobile/include/mach/irqs.h create mode 100644 arch/arm/mach-shmobile/include/mach/memory.h create mode 100644 arch/arm/mach-shmobile/include/mach/system.h create mode 100644 arch/arm/mach-shmobile/include/mach/timex.h create mode 100644 arch/arm/mach-shmobile/include/mach/uncompress.h create mode 100644 arch/arm/mach-shmobile/include/mach/vmalloc.h create mode 100644 arch/arm/mach-shmobile/setup-sh7367.c create mode 100644 arch/arm/mach-shmobile/timer.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 184a6bd54825..55764a1c8763 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -584,6 +584,11 @@ config ARCH_MSM interface to the ARM9 modem processor which runs the baseband stack and controls some vital subsystems (clock and power control, etc). +config ARCH_SHMOBILE + bool "Renesas SH-Mobile" + help + Support for Renesas's SH-Mobile ARM platforms + config ARCH_RPC bool "RiscPC" select ARCH_ACORN @@ -822,6 +827,8 @@ source "arch/arm/mach-s3c6400/Kconfig" source "arch/arm/mach-s3c6410/Kconfig" endif +source "arch/arm/mach-shmobile/Kconfig" + source "arch/arm/plat-stmp3xxx/Kconfig" if ARCH_S5PC1XX diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 356d702c0808..177775fe514d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -165,6 +165,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark +machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_U300) := u300 diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig new file mode 100644 index 000000000000..8f4eb13b5869 --- /dev/null +++ b/arch/arm/mach-shmobile/Kconfig @@ -0,0 +1,53 @@ +if ARCH_SHMOBILE + +comment "SH-Mobile System Type" + +config ARCH_SH7367 + bool "SH-Mobile G3 (SH7367)" + select CPU_V6 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + +comment "SH-Mobile Board Type" + +config MACH_G3EVM + bool "G3EVM board" + depends on ARCH_SH7367 + +comment "SH-Mobile System Configuration" + +menu "Memory configuration" + +config MEMORY_START + hex "Physical memory start address" + default "0x50000000" if MACH_G3EVM + default "0x00000000" + ---help--- + Tweak this only when porting to a new machine which does not + already have a defconfig. Changing it from the known correct + value on any of the known systems will only lead to disaster. + +config MEMORY_SIZE + hex "Physical memory size" + default "0x08000000" if MACH_G3EVM + default "0x04000000" + help + This sets the default memory size assumed by your kernel. It can + be overridden as normal by the 'mem=' argument on the kernel command + line. + +endmenu + +menu "Timer and clock configuration" + +config SH_TIMER_CMT + bool "CMT timer driver" + default y + help + This enables build of the CMT timer driver. + +endmenu + +endif diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile new file mode 100644 index 000000000000..3eca521853d2 --- /dev/null +++ b/arch/arm/mach-shmobile/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for the linux kernel. +# + +# Common objects +obj-y := timer.o + +# CPU objects +obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o + +# Board objects +obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot new file mode 100644 index 000000000000..1c08ee9de86a --- /dev/null +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -0,0 +1,9 @@ +__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ + $$[$(CONFIG_MEMORY_START) + 0x8000]') + + zreladdr-y := $(__ZRELADDR) + +# Unsupported legacy stuff +# +#params_phys-y (Instead: Pass atags pointer in r2) +#initrd_phys-y (Instead: Use compiled-in initramfs) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c new file mode 100644 index 000000000000..b4b202718e4d --- /dev/null +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -0,0 +1,127 @@ +/* + * G3EVM board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *g3evm_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc g3evm_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init g3evm_map_io(void) +{ + iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); + + /* setup early devices and clocks here as well */ + sh7367_add_early_devices(); + sh7367_clock_init(); +} + +static void __init g3evm_init(void) +{ + sh7367_add_standard_devices(); + + platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); +} + +MACHINE_START(G3EVM, "g3evm") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = g3evm_map_io, + .init_irq = sh7367_init_irq, + .init_machine = g3evm_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c new file mode 100644 index 000000000000..3b2e3f2fc7ea --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -0,0 +1,89 @@ +/* + * Preliminary clock framework support for sh7367 + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +struct clk { + const char *name; + unsigned long rate; +}; + +#include + +int __clk_get(struct clk *clk) +{ + return 1; +} +EXPORT_SYMBOL(__clk_get); + +void __clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(__clk_put); + + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk ? clk->rate : 0; +} +EXPORT_SYMBOL(clk_get_rate); + +/* a static peripheral clock for now - enough to get sh-sci working */ +static struct clk peripheral_clk = { + .name = "peripheral_clk", + .rate = 48000000, +}; + +/* a static rclk for now - enough to get sh_cmt working */ +static struct clk r_clk = { + .name = "r_clk", + .rate = 32768, +}; + +static struct clk_lookup lookups[] = { + { + .clk = &peripheral_clk, + }, { + .clk = &r_clk, + } +}; + +void __init sh7367_clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + lookups[i].con_id = lookups[i].clk->name; + clkdev_add(&lookups[i]); + } +} diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h new file mode 100644 index 000000000000..36d0163a857a --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +int __clk_get(struct clk *clk); +void __clk_put(struct clk *clk); + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h new file mode 100644 index 000000000000..d771afa79eb6 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -0,0 +1,11 @@ +#ifndef __ARCH_MACH_COMMON_H +#define __ARCH_MACH_COMMON_H + +extern struct sys_timer shmobile_timer; + +extern void sh7367_init_irq(void); +extern void sh7367_add_early_devices(void); +extern void sh7367_add_standard_devices(void); +extern void sh7367_clock_init(void); + +#endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S new file mode 100644 index 000000000000..796b304050cc --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =INTFLGA + ldr \irqnr, [\base] + cmp \irqnr, #0 + beq 1000f + /* intevt to irq number */ + lsr \irqnr, \irqnr, #0x5 + subs \irqnr, \irqnr, #16 + +1000: + .endm diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h new file mode 100644 index 000000000000..3f0ef194603e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/hardware.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_HARDWARE_H +#define __ASM_MACH_HARDWARE_H + +/* INTFLGA register - used by low level interrupt code in entry-macro.S */ +#define INTFLGA 0xe6980018 + +#endif /* __ASM_MACH_HARDWARE_H */ diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h new file mode 100644 index 000000000000..7339fe46cb7c --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/io.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_IO_H +#define __ASM_MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif /* __ASM_MACH_IO_H */ diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h new file mode 100644 index 000000000000..5179b72e1ee3 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -0,0 +1,10 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#define NR_IRQS 512 +#define NR_IRQS_LEGACY 8 + +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h new file mode 100644 index 000000000000..e188183f4dce --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_MEMORY_H +#define __ASM_MACH_MEMORY_H + +#define PHYS_OFFSET UL(CONFIG_MEMORY_START) +#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) + +#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h new file mode 100644 index 000000000000..76a687eeaa22 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/system.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + cpu_reset(0); +} + +#endif diff --git a/arch/arm/mach-shmobile/include/mach/timex.h b/arch/arm/mach-shmobile/include/mach/timex.h new file mode 100644 index 000000000000..ae0d8d825c23 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/timex.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MACH_TIMEX_H +#define __ASM_MACH_TIMEX_H + +#define CLOCK_TICK_RATE 1193180 /* unused i8253 PIT value */ + +#endif /* __ASM_MACH_TIMEX_H */ diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h new file mode 100644 index 000000000000..0bd7556b1387 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/uncompress.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_UNCOMPRESS_H +#define __ASM_MACH_UNCOMPRESS_H + +/* + * This does not append a newline + */ +static void putc(int c) +{ +} + +static inline void flush(void) +{ +} + +static void arch_decomp_setup(void) +{ +} + +#define arch_decomp_wdog() + +#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h new file mode 100644 index 000000000000..fb3c4f1ab252 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MACH_VMALLOC_H +#define __ASM_MACH_VMALLOC_H + +#define VMALLOC_END (PAGE_OFFSET + 0x24000000) + +#endif /* __ASM_MACH_VMALLOC_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c new file mode 100644 index 000000000000..840e5bcf2d68 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -0,0 +1,241 @@ +/* + * sh7367 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7367_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &cmt10_device, +}; + +void __init sh7367_add_standard_devices(void) +{ + platform_add_devices(sh7367_early_devices, + ARRAY_SIZE(sh7367_early_devices)); +} + +#define SYMSTPCR2 0xe6158048 +#define SYMSTPCR2_CMT1 (1 << 29) + +void __init sh7367_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2); + + early_platform_add_devices(sh7367_early_devices, + ARRAY_SIZE(sh7367_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7367", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7367_init_irq(void) +{ + register_intc_controller(&intc_desc); +} diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c new file mode 100644 index 000000000000..895794b543cd --- /dev/null +++ b/arch/arm/mach-shmobile/timer.c @@ -0,0 +1,46 @@ +/* + * SH-Mobile Timer + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2002 - 2009 Paul Mundt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ +#include +#include + +static void __init shmobile_late_time_init(void) +{ + /* + * Make sure all compiled-in early timers register themselves. + * + * Run probe() for two "earlytimer" devices, these will be the + * clockevents and clocksource devices respectively. In the event + * that only a clockevents device is available, we -ENODEV on the + * clocksource and the jiffies clocksource is used transparently + * instead. No error handling is necessary here. + */ + early_platform_driver_register_all("earlytimer"); + early_platform_driver_probe("earlytimer", 2, 0); +} + +static void __init shmobile_timer_init(void) +{ + late_time_init = shmobile_late_time_init; +} + +struct sys_timer shmobile_timer = { + .init = shmobile_timer_init, +}; From f2aaf66df0858116b2fcdbbfe8126d4ff925ac61 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:07 +0000 Subject: [PATCH 03/27] ARM: mach-shmobile: SH-Mobile G4 support. This adds preliminary support for the SH7377 (SH-Mobile G4) CPU and the G4EVM reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 14 + arch/arm/mach-shmobile/Makefile | 2 + arch/arm/mach-shmobile/board-g4evm.c | 127 +++++++++ arch/arm/mach-shmobile/include/mach/common.h | 4 + arch/arm/mach-shmobile/setup-sh7377.c | 260 +++++++++++++++++++ 5 files changed, 407 insertions(+) create mode 100644 arch/arm/mach-shmobile/board-g4evm.c create mode 100644 arch/arm/mach-shmobile/setup-sh7377.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 8f4eb13b5869..160b2eef6d81 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -10,12 +10,24 @@ config ARCH_SH7367 select GENERIC_TIME select GENERIC_CLOCKEVENTS +config ARCH_SH7377 + bool "SH-Mobile G4 (SH7377)" + select CPU_V7 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + comment "SH-Mobile Board Type" config MACH_G3EVM bool "G3EVM board" depends on ARCH_SH7367 +config MACH_G4EVM + bool "G4EVM board" + depends on ARCH_SH7377 + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -23,6 +35,7 @@ menu "Memory configuration" config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM + default "0x40000000" if MACH_G4EVM default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -32,6 +45,7 @@ config MEMORY_START config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM + default "0x08000000" if MACH_G4EVM default "0x04000000" help This sets the default memory size assumed by your kernel. It can diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3eca521853d2..3f91268705a3 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -7,6 +7,8 @@ obj-y := timer.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o +obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c new file mode 100644 index 000000000000..0d2948f17766 --- /dev/null +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -0,0 +1,127 @@ +/* + * G4EVM board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *g4evm_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc g4evm_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init g4evm_map_io(void) +{ + iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); + + /* setup early devices and clocks here as well */ + sh7377_add_early_devices(); + sh7367_clock_init(); /* use g3 clocks for now */ +} + +static void __init g4evm_init(void) +{ + sh7377_add_standard_devices(); + + platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); +} + +MACHINE_START(G4EVM, "g4evm") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = g4evm_map_io, + .init_irq = sh7377_init_irq, + .init_machine = g4evm_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d771afa79eb6..3595d24b7c8b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,4 +8,8 @@ extern void sh7367_add_early_devices(void); extern void sh7367_add_standard_devices(void); extern void sh7367_clock_init(void); +extern void sh7377_init_irq(void); +extern void sh7377_add_early_devices(void); +extern void sh7377_add_standard_devices(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c new file mode 100644 index 000000000000..e568124ce197 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -0,0 +1,260 @@ +/* + * sh7377 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6cc0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 196, 196, 196, 196 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7377_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &cmt10_device, +}; + +void __init sh7377_add_standard_devices(void) +{ + platform_add_devices(sh7377_early_devices, + ARRAY_SIZE(sh7377_early_devices)); +} + +#define SMSTPCR3 0xe615013c +#define SMSTPCR3_CMT1 (1 << 29) + +void __init sh7377_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); + + early_platform_add_devices(sh7377_early_devices, + ARRAY_SIZE(sh7377_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, SCIFA6, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), INTC_VECT(SCIFA6, 0x1a80), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { 0, 0, 0, 0, SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, + { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7377", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7377_init_irq(void) +{ + register_intc_controller(&intc_desc); +} From 2b7eda63e489a43575f776a1a32bcfbcd75b9476 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:14:58 +0000 Subject: [PATCH 04/27] ARM: mach-shmobile: SH-Mobile AP4 support. This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and the AP4EVB reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 14 ++ arch/arm/mach-shmobile/Makefile | 2 + arch/arm/mach-shmobile/board-ap4evb.c | 127 ++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 4 + arch/arm/mach-shmobile/setup-sh7372.c | 241 +++++++++++++++++++ 5 files changed, 388 insertions(+) create mode 100644 arch/arm/mach-shmobile/board-ap4evb.c create mode 100644 arch/arm/mach-shmobile/setup-sh7372.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 160b2eef6d81..06b3b6162ff7 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -18,6 +18,14 @@ config ARCH_SH7377 select GENERIC_TIME select GENERIC_CLOCKEVENTS +config ARCH_SH7372 + bool "SH-Mobile AP4 (SH7372)" + select CPU_V7 + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + comment "SH-Mobile Board Type" config MACH_G3EVM @@ -28,6 +36,10 @@ config MACH_G4EVM bool "G4EVM board" depends on ARCH_SH7377 +config MACH_AP4EVB + bool "AP4EVB board" + depends on ARCH_SH7372 + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -36,6 +48,7 @@ config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM default "0x40000000" if MACH_G4EVM + default "0x40000000" if MACH_AP4EVB default "0x00000000" ---help--- Tweak this only when porting to a new machine which does not @@ -46,6 +59,7 @@ config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM default "0x08000000" if MACH_G4EVM + default "0x10000000" if MACH_AP4EVB default "0x04000000" help This sets the default memory size assumed by your kernel. It can diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3f91268705a3..88893dbf7107 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,7 +8,9 @@ obj-y := timer.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o +obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c new file mode 100644 index 000000000000..a8d815c96232 --- /dev/null +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -0,0 +1,127 @@ +/* + * AP4EVB board support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel_ro", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x08000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + + +static struct platform_device *ap4evb_devices[] __initdata = { + &nor_flash_device, +}; + +static struct map_desc ap4evb_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init ap4evb_map_io(void) +{ + iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); + + /* setup early devices and clocks here as well */ + sh7372_add_early_devices(); + sh7367_clock_init(); /* use g3 clocks for now */ +} + +static void __init ap4evb_init(void) +{ + sh7372_add_standard_devices(); + + platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); +} + +MACHINE_START(AP4EVB, "ap4evb") + .phys_io = 0xe6000000, + .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, + .map_io = ap4evb_map_io, + .init_irq = sh7372_init_irq, + .init_machine = ap4evb_init, + .timer = &shmobile_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 3595d24b7c8b..a12eb4d75f63 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -12,4 +12,8 @@ extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); extern void sh7377_add_standard_devices(void); +extern void sh7372_init_irq(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c new file mode 100644 index 000000000000..db972e61c071 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -0,0 +1,241 @@ +/* + * sh7372 processor support + * + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 89, 89, 89, 89 }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 90, 90, 90, 90 }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 91, 91, 91, 91 }, +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clk = "r_clk", + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 72, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *sh7372_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &cmt10_device, +}; + +void __init sh7372_add_standard_devices(void) +{ + platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); +} + +#define SMSTPCR3 0xe615013c +#define SMSTPCR3_CMT1 (1 << 29) + +void __init sh7372_add_early_devices(void) +{ + /* enable clock to CMT1 */ + __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); + + early_platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); +} + +enum { + UNUSED = 0, + + /* interrupt sources INTCA */ + + SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, + CMT10, +}; + +static struct intc_vect vectors[] = { + INTC_VECT(CMT10, 0xb00), + INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), + INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), + INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), + INTC_VECT(SCIFB, 0xd60), +}; + +static struct intc_mask_reg mask_registers[] = { + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] = { + { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7372", vectors, NULL, mask_registers, + prio_registers, NULL); + +void __init sh7372_init_irq(void) +{ + register_intc_controller(&intc_desc); +} From 13d605de2ece8c8f7c17a88747d90b7931350ee5 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:15 +0000 Subject: [PATCH 05/27] sh: Build drivers/sh for ARM-based SH-Mobile CPUs. Build drivers/sh in the case of ARM-based SH-Mobile CPUs. Shared code for the interrupt controller (INTC) and the gpio/pinmux (PFC) is located there. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/Makefile b/drivers/Makefile index 6ee53c7a57a1..e94cb1b79633 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_SGI_SN) += sn/ obj-y += firmware/ obj-$(CONFIG_CRYPTO) += crypto/ obj-$(CONFIG_SUPERH) += sh/ +obj-$(CONFIG_ARCH_SHMOBILE) += sh/ obj-$(CONFIG_GENERIC_TIME) += clocksource/ obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ From 65a5b28f0af00dddd785b516914739460562638f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:25 +0000 Subject: [PATCH 06/27] sh: Let INTC set IRQF_VALID on ARM platforms. Reuse the SuperH INTC code on ARM by using set_irq_flags() to set IRQF_VALID on ARM platforms. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/intc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index d5d7f23c19a5..926013bece12 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c @@ -658,6 +658,10 @@ static void __init intc_register_irq(struct intc_desc *desc, if (desc->ack_regs) ack_handle[irq] = intc_ack_data(desc, d, enum_id); + +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif } static unsigned int __init save_reg(struct intc_desc_int *d, @@ -902,8 +906,12 @@ static unsigned int create_irq_on_node(unsigned int irq_want, int node) out_unlock: spin_unlock_irqrestore(&vector_lock, flags); - if (irq > 0) + if (irq > 0) { dynamic_irq_init(irq); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif + } return irq; } From 8a77b8d0744ab21b59a9413c41c6a3d6cb9b0b4f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:33 +0000 Subject: [PATCH 07/27] serial: sh-sci: Support ARM-based SH-Mobile CPUs. Add support for ARM-based SH-Mobile CPUs to the sh-sci driver. Also remove the SCLSR register that is missing on sh772x, sh7705 and SH-Mobile. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/serial/Kconfig | 2 +- drivers/serial/sh-sci.h | 22 ++++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9ff47db0b2ce..406ad918cbac 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -996,7 +996,7 @@ config SERIAL_IP22_ZILOG_CONSOLE config SERIAL_SH_SCI tristate "SuperH SCI(F) serial port support" - depends on HAVE_CLK && (SUPERH || H8300) + depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) select SERIAL_CORE config SERIAL_SH_SCI_NR_UARTS diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index f7d2589926d2..fad67d33b0bd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -30,7 +30,8 @@ */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define PORT_PTCR 0xA405011EUL # define PORT_PVCR 0xA4050122UL @@ -228,7 +229,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCIF_ORER 0x0200 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) # define SCIF_RFDC_MASK 0x007f @@ -261,7 +263,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) @@ -356,7 +359,7 @@ SCI_OUT(sci_size, sci_offset, value); \ } -#ifdef CONFIG_CPU_SH3 +#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ @@ -366,7 +369,8 @@ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -401,7 +405,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCxTDR, 0x20, 8) SCIF_FNS(SCxRDR, 0x24, 8) -SCIF_FNS(SCLSR, 0x24, 16) +SCIF_FNS(SCLSR, 0x00, 0) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) @@ -583,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) From d48d38e87c2ce56dcee030a8bcd5e9e1090c232f Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 8 Feb 2010 12:50:24 +0900 Subject: [PATCH 08/27] MAINTAINERS: Add entry for ARM-based SH-Mobile architecture. Signed-off-by: Paul Mundt --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 03f38c18f323..9d7e056cb14c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -935,6 +935,16 @@ W: http://www.fluff.org/ben/linux/ S: Maintained F: arch/arm/mach-s3c6410/ +ARM/SHMOBILE ARM ARCHITECTURE +M: Paul Mundt +M: Magnus Damm +L: linux-sh@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git +W: http://oss.renesas.com +S: Supported +F: arch/arm/mach-shmobile/ +F: drivers/sh/ + ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From 34bf0fc54a4634ebb0a992e8562191a01233e240 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 03:35:46 +0000 Subject: [PATCH 09/27] ARM: mach-shmobile: G3EVM, G4EVM and AP4EVB defconfigs Add defconfigs for G3EVM, G4EVM and AP4EVB. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/configs/ap4evb_defconfig | 779 ++++++++++++++++++++++++++++++ arch/arm/configs/g3evm_defconfig | 774 +++++++++++++++++++++++++++++ arch/arm/configs/g4evm_defconfig | 779 ++++++++++++++++++++++++++++++ 3 files changed, 2332 insertions(+) create mode 100644 arch/arm/configs/ap4evb_defconfig create mode 100644 arch/arm/configs/g3evm_defconfig create mode 100644 arch/arm/configs/g4evm_defconfig diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig new file mode 100644 index 000000000000..261913d05b4a --- /dev/null +++ b/arch/arm/configs/ap4evb_defconfig @@ -0,0 +1,779 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:25:36 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +# CONFIG_ARCH_SH7367 is not set +# CONFIG_ARCH_SH7377 is not set +CONFIG_ARCH_SH7372=y + +# +# SH-Mobile Board Type +# +CONFIG_MACH_AP4EVB=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x10000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC0,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig new file mode 100644 index 000000000000..d323ff7efa25 --- /dev/null +++ b/arch/arm/configs/g3evm_defconfig @@ -0,0 +1,774 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:20:01 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +CONFIG_ARCH_SH7367=y +# CONFIG_ARCH_SH7377 is not set +# CONFIG_ARCH_SH7372 is not set + +# +# SH-Mobile Board Type +# +CONFIG_MACH_G3EVM=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x50000000 +CONFIG_MEMORY_SIZE=0x08000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC1,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig new file mode 100644 index 000000000000..ce8e05fe1a10 --- /dev/null +++ b/arch/arm/configs/g4evm_defconfig @@ -0,0 +1,779 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Mon Feb 8 12:21:35 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_SHMOBILE=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# SH-Mobile System Type +# +# CONFIG_ARCH_SH7367 is not set +CONFIG_ARCH_SH7377=y +# CONFIG_ARCH_SH7372 is not set + +# +# SH-Mobile Board Type +# +CONFIG_MACH_G4EVM=y + +# +# SH-Mobile System Configuration +# + +# +# Memory configuration +# +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x08000000 + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_CMT=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC4,115200" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y From 62f60d6a37910501814c6281e6c21b485434a7f1 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 10:53:13 +0000 Subject: [PATCH 10/27] ARM: mach-shmobile: optimize get_irqnr_preamble/and_base macros Optimize the SH-Mobile interrupt assembly macros to avoid reloading the INTFLGA register address in case of multiple pending interrupts. Kindly pointed out by Russell King. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/include/mach/entry-macro.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S index 796b304050cc..a285d13c7416 100644 --- a/arch/arm/mach-shmobile/include/mach/entry-macro.S +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S @@ -21,13 +21,13 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =INTFLGA .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =INTFLGA ldr \irqnr, [\base] cmp \irqnr, #0 beq 1000f From 4ae04acb81256719a71125c0f0280e2a3ad68e25 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 8 Feb 2010 11:02:54 +0000 Subject: [PATCH 11/27] ARM: mach-shmobile: early console support using earlyprintk Add support for early console to the SH-Mobile boards. Simply perform an early platform probe for "earlyprintk" to trigger the early serial console code in sh-sci.c. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/configs/ap4evb_defconfig | 2 +- arch/arm/configs/g3evm_defconfig | 2 +- arch/arm/configs/g4evm_defconfig | 2 +- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/board-ap4evb.c | 3 +- arch/arm/mach-shmobile/board-g3evm.c | 3 +- arch/arm/mach-shmobile/board-g4evm.c | 3 +- arch/arm/mach-shmobile/console.c | 31 ++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/common.h | 1 + 9 files changed, 42 insertions(+), 7 deletions(-) create mode 100644 arch/arm/mach-shmobile/console.c diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig index 261913d05b4a..e14229be7676 100644 --- a/arch/arm/configs/ap4evb_defconfig +++ b/arch/arm/configs/ap4evb_defconfig @@ -322,7 +322,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC0,115200" +CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig index d323ff7efa25..3c19031961db 100644 --- a/arch/arm/configs/g3evm_defconfig +++ b/arch/arm/configs/g3evm_defconfig @@ -317,7 +317,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC1,115200" +CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig index ce8e05fe1a10..8ee79a537134 100644 --- a/arch/arm/configs/g4evm_defconfig +++ b/arch/arm/configs/g4evm_defconfig @@ -322,7 +322,7 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC4,115200" +CONFIG_CMDLINE="console=ttySC4,115200 earlyprintk=sh-sci.4,115200" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 88893dbf7107..800e7dd9e9d1 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -3,7 +3,7 @@ # # Common objects -obj-y := timer.o +obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a8d815c96232..94b545b3fe82 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -105,9 +105,10 @@ static void __init ap4evb_map_io(void) { iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7372_add_early_devices(); sh7367_clock_init(); /* use g3 clocks for now */ + shmobile_setup_console(); } static void __init ap4evb_init(void) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index b4b202718e4d..eba2311beba2 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -105,9 +105,10 @@ static void __init g3evm_map_io(void) { iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7367_add_early_devices(); sh7367_clock_init(); + shmobile_setup_console(); } static void __init g3evm_init(void) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 0d2948f17766..0ddde038588e 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -105,9 +105,10 @@ static void __init g4evm_map_io(void) { iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); - /* setup early devices and clocks here as well */ + /* setup early devices, clocks and console here as well */ sh7377_add_early_devices(); sh7367_clock_init(); /* use g3 clocks for now */ + shmobile_setup_console(); } static void __init g4evm_init(void) diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c new file mode 100644 index 000000000000..9411a5bf4fd6 --- /dev/null +++ b/arch/arm/mach-shmobile/console.c @@ -0,0 +1,31 @@ +/* + * SH-Mobile Console + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +void __init shmobile_setup_console(void) +{ + parse_early_param(); + + /* Let earlyprintk output early console messages */ + early_platform_driver_probe("earlyprintk", 1, 1); +} diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index a12eb4d75f63..f5986ea561f3 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -2,6 +2,7 @@ #define __ARCH_MACH_COMMON_H extern struct sys_timer shmobile_timer; +extern void shmobile_setup_console(void); extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); From f8eef1305b33438dd7a3a01e43b94e57ca87fc9b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:35:42 +0000 Subject: [PATCH 12/27] ARM: mach-shmobile: sh7367 INTCA support Add support for the sh7367 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7367.c | 270 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7367.c | 43 ---- 3 files changed, 271 insertions(+), 44 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7367.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 800e7dd9e9d1..1ae3633c8ab3 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -6,7 +6,7 @@ obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c new file mode 100644 index 000000000000..6a547b47aabb --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -0,0 +1,270 @@ +/* + * sh7367 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + DIRC, + CRYPT1_ERR, CRYPT2_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX, + ETM11_ACQCMP, ETM11_FULL, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, + MSU_MSU, MSU_MSU2, + IREM, + SIU, + SPU, + IRDA, + TPU0, TPU1, TPU2, TPU3, TPU4, + LCRC, + PINT1, PINT2, + TTI20, + MISTY, + DDM, + SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, + RWDT0, RWDT1, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, + ETM11, ARM11, USBHS, FLCTL, IIC1, SDHI0, SDHI1, SDHI2, +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(CRYPT1_ERR, 0x05e0), + INTC_VECT(CRYPT2_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840), + INTC_VECT(ARM11_COMMRX, 0x0860), + INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), + INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), + INTC_VECT(IREM, 0x0f60), + INTC_VECT(SIU, 0x0fa0), + INTC_VECT(SPU, 0x0fc0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), + INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), + INTC_VECT(TPU4, 0x0520), + INTC_VECT(LCRC, 0x0540), + INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(MISTY, 0x1120), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), + INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), + INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL), + INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2, SDHI1_SDHI1I3), + INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, + SDHI2_SDHI2I2, SDHI2_SDHI2I3), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { CRYPT1_ERR, CRYPT2_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { PINT1, PINT2, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, ETM11_FULL, ETM11_ACQCMP } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBDMAC_USHDMI, SPU, SIU } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, USBHS_USHI1, USBHS_USHI0, 0 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + LCRC, MSU_MSU2, IREM, MSU_MSU } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, TPU1, + TPU2, TPU3, TPU4, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, + MISTY, CMT3, RWDT1, RWDT0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, + CMT1_CMT11, ARM11 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2, + CMT1_CMT12, TPU4 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, USBHS } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + 0, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7367-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7367_init_irq(void) +{ + /* INTCA */ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index 840e5bcf2d68..eca90716140e 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -197,45 +196,3 @@ void __init sh7367_add_early_devices(void) early_platform_add_devices(sh7367_early_devices, ARRAY_SIZE(sh7367_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7367", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7367_init_irq(void) -{ - register_intc_controller(&intc_desc); -} From 6673be73809c8aa1ca5255c83f4fc85c43fdbfab Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:35:53 +0000 Subject: [PATCH 13/27] ARM: mach-shmobile: sh7377 INTCA support Add support for the sh7377 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7377.c | 350 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7377.c | 45 ---- 3 files changed, 351 insertions(+), 46 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7377.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 1ae3633c8ab3..7864f6299af7 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -7,7 +7,7 @@ obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o -obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o # Board objects diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c new file mode 100644 index 000000000000..125021cfba5c --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -0,0 +1,350 @@ +/* + * sh7377 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, + IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, + DIRC, + _2DG, + CRYPT_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + _3DG_SGX540, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, + MSU_MSU, MSU_MSU2, + IRREM, + MSUG, + IRDA, + TPU0, TPU1, TPU2, TPU3, TPU4, + LCRC, + PINTCA_PINT1, PINTCA_PINT2, + TTI20, + MISTY, + DDM, + RWDT0, RWDT1, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + ICUSB_ICUSB0, ICUSB_ICUSB1, + ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, + SPU2_SPU0, SPU2_SPU1, + FSI, + FMSI, + SCUV, + IPMMU_IPMMUB, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + SCIFA6, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, + ICUSB, ICUDMC +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), + INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), + INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), + INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), + INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), + INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), + INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), + INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(_2DG, 0x05e0), + INTC_VECT(CRYPT_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(_3DG_SGX540, 0x0a60), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), + INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), + INTC_VECT(IRREM, 0x0f60), + INTC_VECT(MSUG, 0x0fa0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), + INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), + INTC_VECT(TPU4, 0x0520), + INTC_VECT(LCRC, 0x0540), + INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(MISTY, 0x1120), + INTC_VECT(DDM, 0x1140), + INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720), + INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0), + INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(SCUV, 0x1880), + INTC_VECT(IPMMU_IPMMUB, 0x1900), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), + INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), + INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), + INTC_VECT(MFIS2, 0x1a00), + INTC_VECT(CPORTR2S, 0x1a20), + INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), + INTC_VECT(SCIFA6, 0x1a80), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2, SDHI1_SDHI1I3), + INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), + INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1), + INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { _2DG, CRYPT_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { PINTCA_PINT1, PINTCA_PINT2, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBDMAC_USHDMI, 0, MSUG } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + LCRC, MSU_MSU2, IRREM, MSU_MSU } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, TPU1, + TPU2, TPU3, TPU4, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { 0, 0, 0, 0, + MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ + { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0, + ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } }, + { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ + { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, + SCUV, 0, 0, 0 } }, + { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ + { IPMMU_IPMMUB, 0, 0, 0, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { MFIS2, CPORTR2S, CMT14, CMT15, + SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690001c, 0, 32, 4, /* INTPRI30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, + CMT1_CMT11, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2, + CMT1_CMT12, TPU4 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, USBHS } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + _3DG_SGX540, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } }, + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } }, + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900008, 16, 2, /* ICR3A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690000c, 16, 2, /* ICR4A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900028, 0, 8, /* INTREQ20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690002c, 0, 8, /* INTREQ30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7377-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7377_init_irq(void) +{ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index e568124ce197..60e37774c35c 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -213,48 +213,3 @@ void __init sh7377_add_early_devices(void) early_platform_add_devices(sh7377_early_devices, ARRAY_SIZE(sh7377_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, SCIFA6, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), INTC_VECT(SCIFA6, 0x1a80), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, - { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ - { 0, 0, 0, 0, SCIFA6, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, - { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7377", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7377_init_irq(void) -{ - register_intc_controller(&intc_desc); -} From e4e430c611db75f58d3ca33869e182a530859426 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 9 Feb 2010 03:36:03 +0000 Subject: [PATCH 14/27] ARM: mach-shmobile: sh7372 INTCA support Add support for the sh7372 INTCA hardware block. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/intc-sh7372.c | 367 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7372.c | 42 --- 3 files changed, 368 insertions(+), 43 deletions(-) create mode 100644 arch/arm/mach-shmobile/intc-sh7372.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 7864f6299af7..89ea4b0ea52d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -8,7 +8,7 @@ obj-y := timer.o console.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o -obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c new file mode 100644 index 000000000000..c6e747f92462 --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -0,0 +1,367 @@ +/* + * sh7372 processor support - INTC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, + IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, + IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, + IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, + DIRC, + CRYPT_STD, + IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, + AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI_MFIM, MFI_MFIS, + BBIF1, BBIF2, + USBHSDMAC_USHDMI, + USBHS_USHI0, USBHS_USHI1, + _3DG_SGX540, + CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, + KEYSC_KEY, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, + SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, + IRREM, + IRDA, + TPU0, + TTI20, + DDM, + SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, + RWDT0, + DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, + DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + HDMI, + SPU2_SPU0, SPU2_SPU1, + FSI, FMSI, + MIPI_HSI, + IPMMU_IPMMUD, + CEC_CEC_1, CEC_CEC_2, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + MMC_MMC_ERR, MMC_MMC_NOR, + IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, + IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, + USB0_USB0I1, USB0_USB0I0, + USB1_USB1I1, USB1_USB1I0, + USHSDMI, + + /* interrupt groups INTCA */ + DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 +}; + +static struct intc_vect intca_vectors[] = { + INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), + INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), + INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), + INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), + INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), + INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), + INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), + INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), + INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), + INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), + INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0), + INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), + INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), + INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), + INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), + INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), + INTC_VECT(DIRC, 0x0560), + INTC_VECT(CRYPT_STD, 0x0700), + INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), + INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), + INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBHSDMAC_USHDMI, 0x0a00), + INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(_3DG_SGX540, 0x0a60), + INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), + INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), + INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), + INTC_VECT(KEYSC_KEY, 0x0be0), + INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), + INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), + INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), + INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), + INTC_VECT(SCIFB, 0x0d60), + INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), + INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), + INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), + INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), + INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), + INTC_VECT(IRREM, 0x0f60), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04a0), + INTC_VECT(TTI20, 0x1100), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), + INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), + INTC_VECT(RWDT0, 0x1280), + INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), + INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), + INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), + INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), + INTC_VECT(DMAC2_2_DADERR, 0x21c0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), + INTC_VECT(DMAC3_2_DADERR, 0x22c0), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(HDMI, 0x17e0), + INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(MIPI_HSI, 0x18e0), + INTC_VECT(IPMMU_IPMMUD, 0x1920), + INTC_VECT(CEC_CEC_1, 0x1940), INTC_VECT(CEC_CEC_2, 0x1960), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), + INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), + INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), + INTC_VECT(MFIS2, 0x1a00), + INTC_VECT(CPORTR2S, 0x1a20), + INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), + INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0), + INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20), + INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60), + INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0), + INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), + INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), + INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), + INTC_VECT(USHSDMI, 0x1d00), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC_1, DMAC_1_DEI0, + DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), + INTC_GROUP(DMAC_2, DMAC_2_DEI4, + DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, + DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, + DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, + DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, + DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), + INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, + FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), + INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, + SDHI0_SDHI0I2, SDHI0_SDHI0I3), + INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, + SDHI1_SDHI1I2), + INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, + SDHI2_SDHI2I2, SDHI2_SDHI2I3), + INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), +}; + +static struct intc_mask_reg intca_mask_registers[] = { + { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ + { 0, CRYPT_STD, DIRC, 0, + DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ + { 0, 0, 0, 0, + BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, + { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ + { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ + { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ + { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, + TTI20, USBHSDMAC_USHDMI, 0, 0 } }, + { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ + { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, + CMT2, 0, 0, _3DG_SGX540 } }, + { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ + { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, + 0, 0, IRREM, 0 } }, + { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ + { 0, 0, TPU0, 0, + 0, 0, 0, 0 } }, + { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ + { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, + 0, CMT3, 0, RWDT0 } }, + { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ + { 0, 0, 0, 0, + 0, 0, 0, HDMI } }, + { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ + { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, + 0, 0, 0, MIPI_HSI } }, + { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ + { 0, IPMMU_IPMMUD, CEC_CEC_1, CEC_CEC_2, + AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, + { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ + { MFIS2, CPORTR2S, CMT14, CMT15, + 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } }, + { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */ + { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, + IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, + { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */ + { 0, 0, 0, 0, + USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, + { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ + { USBHSDMAC_USHDMI, 0, 0, 0, + 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] = { + { 0xe6900010, 0, 32, 4, /* INTPRI00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900014, 0, 32, 4, /* INTPRI10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690001c, 0, 32, 4, /* INTPRI30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, + + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, + CMT1_CMT11, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, + CMT1_CMT12, 0 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + MFI_MFIM, 0 } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + _3DG_SGX540, CMT1_CMT10 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC_USHDMI, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, 0, TTI20 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, + CEC_CEC_1, CEC_CEC_2 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, + MMC_MMC_ERR, MMC_MMC_NOR } }, + { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, + IIC4_WAITI4, IIC4_DTEI4 } }, + { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, + IIC3_WAITI3, IIC3_DTEI3 } }, + { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0, 0, 0, 0 } }, + { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, + USB1_USB1I1, USB1_USB1I0 } }, + { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC_USHDMI, 0, 0, 0 } }, +}; + +static struct intc_sense_reg intca_sense_registers[] __initdata = { + { 0xe6900000, 16, 2, /* ICR1A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900004, 16, 2, /* ICR2A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900008, 16, 2, /* ICR3A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690000c, 16, 2, /* ICR4A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static struct intc_mask_reg intca_ack_registers[] __initdata = { + { 0xe6900020, 0, 8, /* INTREQ00A */ + { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, + { 0xe6900024, 0, 8, /* INTREQ10A */ + { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, + { 0xe6900028, 0, 8, /* INTREQ20A */ + { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, + { 0xe690002c, 0, 8, /* INTREQ30A */ + { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, +}; + +static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + intca_sense_registers, intca_ack_registers); + +void __init sh7372_init_irq(void) +{ + register_intc_controller(&intca_desc); +} diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index db972e61c071..1d1153290f59 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -197,45 +197,3 @@ void __init sh7372_add_early_devices(void) early_platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); } - -enum { - UNUSED = 0, - - /* interrupt sources INTCA */ - - SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB, - CMT10, -}; - -static struct intc_vect vectors[] = { - INTC_VECT(CMT10, 0xb00), - INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20), - INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60), - INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40), - INTC_VECT(SCIFB, 0xd60), -}; - -static struct intc_mask_reg mask_registers[] = { - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { 0, 0, 0, CMT10, 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg prio_registers[] = { - { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intc_desc, "sh7372", vectors, NULL, mask_registers, - prio_registers, NULL); - -void __init sh7372_init_irq(void) -{ - register_intc_controller(&intc_desc); -} From 7fdda6780aaa21c7a94e09975649649bb0f4a932 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 10 Feb 2010 20:10:55 +0900 Subject: [PATCH 15/27] ARM: mach-shmobile: sh7367 and G3EVM pinmux support Add support for the sh7367 pinmux using drivers/sh/pfc.c and select serial console pins and some LEDs on G3EVM. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 4 + arch/arm/mach-shmobile/board-g3evm.c | 25 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/gpio.h | 49 +- arch/arm/mach-shmobile/include/mach/sh7367.h | 332 ++++ arch/arm/mach-shmobile/pfc-sh7367.c | 1801 ++++++++++++++++++ 7 files changed, 2212 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7367.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7367.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 06b3b6162ff7..639df5ffbcef 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -31,6 +31,7 @@ comment "SH-Mobile Board Type" config MACH_G3EVM bool "G3EVM board" depends on ARCH_SH7367 + select ARCH_REQUIRE_GPIOLIB config MACH_G4EVM bool "G4EVM board" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 89ea4b0ea52d..9ef2630d1432 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -10,6 +10,10 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o +# Pinmux setup +pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o +obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) + # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index eba2311beba2..28ee589caba6 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -113,6 +115,29 @@ static void __init g3evm_map_io(void) static void __init g3evm_init(void) { + sh7367_pinmux_init(); + + /* Lit DS4 LED */ + gpio_request(GPIO_PORT22, NULL); + gpio_direction_output(GPIO_PORT22, 1); + gpio_export(GPIO_PORT22, 0); + + /* Lit DS8 LED */ + gpio_request(GPIO_PORT23, NULL); + gpio_direction_output(GPIO_PORT23, 1); + gpio_export(GPIO_PORT23, 0); + + /* Lit DS3 LED */ + gpio_request(GPIO_PORT24, NULL); + gpio_direction_output(GPIO_PORT24, 1); + gpio_export(GPIO_PORT24, 0); + + /* SCIFA1 */ + gpio_request(GPIO_FN_SCIFA1_TXD, NULL); + gpio_request(GPIO_FN_SCIFA1_RXD, NULL); + gpio_request(GPIO_FN_SCIFA1_CTS, NULL); + gpio_request(GPIO_FN_SCIFA1_RTS, NULL); + sh7367_add_standard_devices(); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index f5986ea561f3..a4846001e89a 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -8,6 +8,7 @@ extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); extern void sh7367_add_standard_devices(void); extern void sh7367_clock_init(void); +extern void sh7367_pinmux_init(void); extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h index 40a8c178f10d..5bc6bd444d72 100644 --- a/arch/arm/mach-shmobile/include/mach/gpio.h +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -1 +1,48 @@ -/* empty */ +/* + * Generic GPIO API and pinmux table support + * + * Copyright (c) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include +#include + +#define ARCH_NR_GPIOS 1024 +#include + +#ifdef CONFIG_GPIOLIB + +static inline int gpio_get_value(unsigned gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return -ENOSYS; +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return -EINVAL; +} + +#endif /* CONFIG_GPIOLIB */ + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h new file mode 100644 index 000000000000..52d0de686f68 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7367.h @@ -0,0 +1,332 @@ +#ifndef __ASM_SH7367_H__ +#define __ASM_SH7367_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* 49-1 -> 49-6 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU, + GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU, + GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU, + GPIO_FN_PORT58_KEYIN6_PU, + + /* 49-1 (FN) */ + GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2, + GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6, + GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10, + GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2, + GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5, + GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2, + GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20, + GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22, + GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7, + GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2, + GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK, + GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, + GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK, + GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS, + + /* 49-2 (FN) */ + GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0, + GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1, + GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2, + GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3, + GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4, + GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5, + GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0, + GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1, + GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2, + GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC, + GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK, + GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD, + GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD, + GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3, + GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4, + GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5, + GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6, + GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1, + GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2, + GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A, + GPIO_FN_XTALB1L, + GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS, + GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK, + GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD, + GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD, + GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS, + GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS, + GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0, + GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1, + GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2, + GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3, + GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0, + GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1, + GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2, + GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3, + GPIO_FN_NMI, GPIO_FN_TPU4TO0, + GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3, + GPIO_FN_IRQ_TMPB, + GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1, + GPIO_FN_OVCN, GPIO_FN_MFG1_IN1, + GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2, + + /* 49-3 (FN) */ + GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2, + GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN, + GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1, + GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2, + GPIO_FN_SCIFA5_RXD, + GPIO_FN_SCIFA5_TXD, + GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1, + GPIO_FN_A0_EA0, GPIO_FN_BS, + GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0, + GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL, + GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2, + GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3, + GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4, + GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5, + GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0, + GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1, + GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2, + GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3, + GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4, + GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5, + GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL, + GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2, + GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5, + GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8, + GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11, + GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13, + GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15, + GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1, + GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A, + GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD, + GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE, + GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO, + GPIO_FN_NBRSTOUT, GPIO_FN_NBRST, + + /* 49-4 (FN) */ + GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD, + GPIO_FN_VIO_VD, GPIO_FN_VIO_HD, + GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, + GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, + GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, + GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, + GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, + GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, + GPIO_FN_VIO_CKO, + GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2, + GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0, + GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1, + GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2, + GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3, + GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0, + GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2, + GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1, + GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2, + GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3, + GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4, + GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2, + GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5, + GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2, + GPIO_FN_LCDD6, GPIO_FN_DV_D6, + GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2, + GPIO_FN_LCDD7, GPIO_FN_DV_D7, + GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3, + GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16, + GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17, + GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18, + GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19, + GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20, + GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21, + GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22, + GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23, + GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24, + GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK, + GPIO_FN_D26, GPIO_FN_ED26, + GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC, + GPIO_FN_D27, GPIO_FN_ED27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, + GPIO_FN_D28, GPIO_FN_ED28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, + GPIO_FN_D29, GPIO_FN_ED29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1, + GPIO_FN_D30, GPIO_FN_ED30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2, + GPIO_FN_D31, GPIO_FN_ED31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD, + GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC, + + + /* 49-5 (FN) */ + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK, + GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD, + GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3, + GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7, + GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR, + GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR, + GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0, + GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1, + GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3, + GPIO_FN_MSIOF1_SS2, + GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT, + GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, + GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3, + GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1, + GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK, + GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC, + GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD, + GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW, + GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, + GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, + GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2, + GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD, + GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_SDHICLK0, GPIO_FN_TCK2, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, GPIO_FN_TMS2, + GPIO_FN_SDHID0_1, GPIO_FN_TDO2, + GPIO_FN_SDHID0_2, GPIO_FN_TDI2, + GPIO_FN_SDHID0_3, GPIO_FN_RTCK2, + + /* 49-6 (FN) */ + GPIO_FN_SDHICMD0, GPIO_FN_TRST2, + GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2, + GPIO_FN_SDHICLK1, GPIO_FN_TCK3, + GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, + GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3, + GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2, + GPIO_FN_TS_SDAT2, GPIO_FN_TDO3, + GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, + GPIO_FN_TS_SDEN2, GPIO_FN_TDI3, + GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, + GPIO_FN_TS_SCK2, GPIO_FN_RTCK3, + GPIO_FN_SDHICMD1, GPIO_FN_TRST3, + GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK, + GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD, + GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS, + GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD, + GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS, + GPIO_FN_SDHICMD2, + GPIO_FN_RESETOUTS, + GPIO_FN_DIVLOCK, +}; + +#endif /* __ASM_SH7367_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c new file mode 100644 index 000000000000..128555e76e43 --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7367.c @@ -0,0 +1,1801 @@ +/* + * sh7367 processor support - PFC hardware block + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _90(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \ + _10(fn, pfx##9, sfx) + +#define _273(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _90(fn, pfx, sfx), \ + _10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \ + _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ + _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ + _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ + _10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \ + _1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_273(str) _273(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_273(IN), /* PORT0_IN -> PORT272_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */ + PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */ + PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */ + PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */ + PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */ + PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */ + PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */ + PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */ + PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */ + PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */ + + MSELBCR_MSEL2_1, MSELBCR_MSEL2_0, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Special Pull-up / Pull-down Functions */ + PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK, + PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK, + PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK, + PORT58_KEYIN6_PU_MARK, + + /* 49-1 */ + VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK, + CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK, + CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK, + CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK, + CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK, + CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK, + CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK, + RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK, + STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK, + MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK, + XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK, + IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK, + M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK, + XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK, + XCTS1_MARK, SCIFA4_CTS_MARK, + + /* 49-2 */ + HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK, + HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK, + HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK, + HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK, + HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK, + HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK, + HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK, + HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK, + HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK, + HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK, + HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK, + HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK, + HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK, + HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK, + HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK, + HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK, + B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK, + HSU_SDI_MARK, PORT55_KEYIN3_MARK, + HSU_SCO_MARK, PORT56_KEYIN4_MARK, + HSU_DREQ_MARK, PORT57_KEYIN5_MARK, + HSU_DACK_MARK, PORT58_KEYIN6_MARK, + HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK, + HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK, + PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK, + XTALB1L_MARK, + GPS_AGC1_MARK, SCIFA0_RTS_MARK, + GPS_AGC2_MARK, SCIFA0_SCK_MARK, + GPS_AGC3_MARK, SCIFA0_TXD_MARK, + GPS_AGC4_MARK, SCIFA0_RXD_MARK, + GPS_PWRD_MARK, SCIFA0_CTS_MARK, + GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK, + SIUBOMC_MARK, TPU2TO0_MARK, + SIUCKB_MARK, TPU2TO1_MARK, + SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK, + SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK, + SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK, + SIUBILR_MARK, TPU3TO1_MARK, + SIUBIBT_MARK, TPU3TO2_MARK, + SIUBISLD_MARK, TPU3TO3_MARK, + NMI_MARK, TPU4TO0_MARK, + DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK, + IRQ_TMPB_MARK, + PWEN_MARK, MFG1_OUT1_MARK, + OVCN_MARK, MFG1_IN1_MARK, + OVCN2_MARK, MFG1_IN2_MARK, + + /* 49-3 */ + RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK, + USBTERM_MARK, EXTLP_MARK, IDIN_MARK, + SCIFA5_CTS_MARK, MFG0_IN1_MARK, + SCIFA5_RTS_MARK, MFG0_IN2_MARK, + SCIFA5_RXD_MARK, + SCIFA5_TXD_MARK, + SCIFA5_SCK_MARK, MFG0_OUT1_MARK, + A0_EA0_MARK, BS_MARK, + A14_EA14_MARK, PORT102_KEYOUT0_MARK, + A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK, + A16_EA16_MARK, PORT104_KEYOUT2_MARK, + DV_VSYNCL_MARK, MSIOF0_SS1_MARK, + A17_EA17_MARK, PORT105_KEYOUT3_MARK, + DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK, + A18_EA18_MARK, PORT106_KEYOUT4_MARK, + DV_DL0_MARK, MSIOF0_TSCK_MARK, + A19_EA19_MARK, PORT107_KEYOUT5_MARK, + DV_DL1_MARK, MSIOF0_TXD_MARK, + A20_EA20_MARK, PORT108_KEYIN0_MARK, + DV_DL2_MARK, MSIOF0_RSCK_MARK, + A21_EA21_MARK, PORT109_KEYIN1_MARK, + DV_DL3_MARK, MSIOF0_RSYNC_MARK, + A22_EA22_MARK, PORT110_KEYIN2_MARK, + DV_DL4_MARK, MSIOF0_MCK0_MARK, + A23_EA23_MARK, PORT111_KEYIN3_MARK, + DV_DL5_MARK, MSIOF0_MCK1_MARK, + A24_EA24_MARK, PORT112_KEYIN4_MARK, + DV_DL6_MARK, MSIOF0_RXD_MARK, + A25_EA25_MARK, PORT113_KEYIN5_MARK, + DV_DL7_MARK, MSIOF0_SS2_MARK, + A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK, + D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK, + D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK, + D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK, + D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK, + D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK, + D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK, + CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK, + CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK, + DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK, + A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK, + WE1_XWR1_MARK, FRB_MARK, CKO_MARK, + NBRSTOUT_MARK, NBRST_MARK, + + /* 49-4 */ + RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK, + VIO_VD_MARK, VIO_HD_MARK, + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, + VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK, + VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK, + VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, + VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK, + VIO_CKO_MARK, + MFG3_IN1_MARK, MFG3_IN2_MARK, + M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK, + M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK, + M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK, + M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK, + LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK, + SIUCKA_MARK, MFG0_OUT2_MARK, + LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK, + SIUAOLR_MARK, BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK, + SIUAOBT_MARK, BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK, + SIUAOSLD_MARK, BBIF2_TXD1_MARK, + LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK, + SIUAISPD_MARK, MFG1_OUT2_MARK, + LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK, + SIUAILR_MARK, MFG2_OUT2_MARK, + LCDD6_MARK, DV_D6_MARK, + SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK, + LCDD7_MARK, DV_D7_MARK, + SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK, + LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK, + LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK, + LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK, + LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK, + LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK, + LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK, + LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK, + LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK, + LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK, + LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK, + LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK, + D26_MARK, ED26_MARK, + LCDD19_MARK, MSIOF0L_TSYNC_MARK, + D27_MARK, ED27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, + D28_MARK, ED28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, + D29_MARK, ED29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK, + D30_MARK, ED30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK, + D31_MARK, ED31_MARK, + LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK, + LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK, + + /* 49-5 */ + LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK, + LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK, + LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK, + LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK, + VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK, + VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK, + VIO_VDR_MARK, VIO_HDR_MARK, + VIO_CLKR_MARK, VIO_CKOR_MARK, + SCIFA1_TXD_MARK, GPS_PGFA0_MARK, + SCIFA1_SCK_MARK, GPS_PGFA1_MARK, + SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK, + SCIFA1_RXD_MARK, SCIFA1_CTS_MARK, + MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK, + MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK, + MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK, + MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK, + MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK, + MSIOF1_RSYNC_MARK, I2C_SCL2_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + MSIOF1_SS1_MARK, EDBGREQ3_MARK, + MSIOF1_SS2_MARK, + PORT236_IROUT_MARK, IRDA_OUT_MARK, + IRDA_IN_MARK, IRDA_FIRSEL_MARK, + TPU1TO0_MARK, TS_SPSYNC3_MARK, + TPU1TO1_MARK, TS_SDAT3_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK, + TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK, + M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK, + M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK, + PORT245_IROUT_MARK, M15_RSW_MARK, + SOUT3_MARK, SCIFA2_TXD1_MARK, + SIN3_MARK, SCIFA2_RXD1_MARK, + XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK, + XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK, + DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + SDHICLK0_MARK, TCK2_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, TMS2_MARK, + SDHID0_1_MARK, TDO2_MARK, + SDHID0_2_MARK, TDI2_MARK, + SDHID0_3_MARK, RTCK2_MARK, + + /* 49-6 */ + SDHICMD0_MARK, TRST2_MARK, + SDHIWP0_MARK, EDBGREQ2_MARK, + SDHICLK1_MARK, TCK3_MARK, + SDHID1_0_MARK, M11_SLCD_SO2_MARK, + TS_SPSYNC2_MARK, TMS3_MARK, + SDHID1_1_MARK, M9_SLCD_AO2_MARK, + TS_SDAT2_MARK, TDO3_MARK, + SDHID1_2_MARK, M10_SLCD_CK2_MARK, + TS_SDEN2_MARK, TDI3_MARK, + SDHID1_3_MARK, M12_SLCD_CE2_MARK, + TS_SCK2_MARK, RTCK3_MARK, + SDHICMD1_MARK, TRST3_MARK, + SDHICLK2_MARK, SCIFB_SCK_MARK, + SDHID2_0_MARK, SCIFB_TXD_MARK, + SDHID2_1_MARK, SCIFB_CTS_MARK, + SDHID2_2_MARK, SCIFB_RXD_MARK, + SDHID2_3_MARK, SCIFB_RTS_MARK, + SDHICMD2_MARK, + RESETOUTS_MARK, + DIVLOCK_MARK, + PINMUX_MARK_END, +}; + +#define PORT_DATA_I(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) + +#define PORT_DATA_I_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_I_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_I_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +#define PORT_DATA_O(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) + +#define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) + +#define PORT_DATA_IO_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_IO_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_IO_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + + +static pinmux_enum_t pinmux_data[] = { + + /* specify valid pin states for each pin in GPIO mode */ + + /* 49-1 (GPIO) */ + PORT_DATA_I_PD(0), + PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6), + PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9), + PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12), + PORT_DATA_I_PU(13), + PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), + PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19), + PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23), + PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26), + PORT_DATA_I_PD(27), PORT_DATA_I_PD(28), + PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32), + PORT_DATA_IO_PU(33), + PORT_DATA_O(34), + PORT_DATA_I_PU(35), + PORT_DATA_O(36), + PORT_DATA_I_PU_PD(37), + + /* 49-2 (GPIO) */ + PORT_DATA_IO_PU_PD(38), + PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41), + PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45), + PORT_DATA_O(46), PORT_DATA_O(47), + PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50), + PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52), + PORT_DATA_O(53), + PORT_DATA_IO_PD(54), + PORT_DATA_I_PU_PD(55), + PORT_DATA_IO_PU_PD(56), + PORT_DATA_I_PU_PD(57), + PORT_DATA_IO_PU_PD(58), + PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62), + PORT_DATA_O(63), + PORT_DATA_I_PU(64), + PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68), + PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70), + PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73), + PORT_DATA_I_PD(74), + PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76), + PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78), + PORT_DATA_O(79), + PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82), + PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84), + PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86), + PORT_DATA_I_PD(87), + PORT_DATA_IO_PU_PD(88), + PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90), + + /* 49-3 (GPIO) */ + PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98), + PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100), + PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103), + PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106), + PORT_DATA_IO_PD(107), + PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109), + PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PU_PD(114), + PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), + PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120), + PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123), + PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126), + PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129), + PORT_DATA_IO_PU(130), + PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133), + PORT_DATA_IO_PU(134), + PORT_DATA_O(135), PORT_DATA_O(136), + PORT_DATA_I_PU_PD(137), + PORT_DATA_IO(138), + PORT_DATA_IO_PU_PD(139), + PORT_DATA_IO(140), PORT_DATA_IO(141), + PORT_DATA_I_PU(142), + PORT_DATA_O(143), PORT_DATA_O(144), + PORT_DATA_I_PU(145), + + /* 49-4 (GPIO) */ + PORT_DATA_O(146), + PORT_DATA_I_PU_PD(147), + PORT_DATA_I_PD(148), PORT_DATA_I_PD(149), + PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152), + PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155), + PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158), + PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161), + PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164), + PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166), + PORT_DATA_IO_PU_PD(167), + PORT_DATA_O(168), + PORT_DATA_I_PD(169), PORT_DATA_I_PD(170), + PORT_DATA_O(171), + PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), + PORT_DATA_O(174), + PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177), + PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180), + PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183), + PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186), + PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), + PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192), + PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198), + PORT_DATA_O(199), + PORT_DATA_IO_PD(200), + + /* 49-5 (GPIO) */ + PORT_DATA_O(201), + PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203), + PORT_DATA_I(204), + PORT_DATA_O(205), + PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208), + PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214), + PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216), + PORT_DATA_O(217), + PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219), + PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222), + PORT_DATA_I_PD(223), + PORT_DATA_I_PU_PD(224), + PORT_DATA_O(225), + PORT_DATA_IO_PD(226), + PORT_DATA_IO_PU_PD(227), + PORT_DATA_I_PD(228), + PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230), + PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232), + PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234), + PORT_DATA_I_PU_PD(235), + PORT_DATA_O(236), + PORT_DATA_I_PD(237), + PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239), + PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241), + PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243), + PORT_DATA_O(244), + PORT_DATA_IO_PU_PD(245), + PORT_DATA_O(246), + PORT_DATA_I_PD(247), + PORT_DATA_IO_PU_PD(248), + PORT_DATA_I_PU_PD(249), + PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251), + PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253), + PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255), + PORT_DATA_IO_PU_PD(256), + + /* 49-6 (GPIO) */ + PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258), + PORT_DATA_IO_PD(259), + PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262), + PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264), + PORT_DATA_O(265), + PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268), + PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270), + PORT_DATA_O(271), + PORT_DATA_I_PD(272), + + /* Special Pull-up / Pull-down Functions */ + PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1, + PORT48_FN2, PORT48_IN_PU), + PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1, + PORT49_FN2, PORT49_IN_PU), + PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1, + PORT50_FN2, PORT50_IN_PU), + PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1, + PORT55_FN2, PORT55_IN_PU), + PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1, + PORT56_FN2, PORT56_IN_PU), + PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1, + PORT57_FN2, PORT57_IN_PU), + PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1, + PORT58_FN2, PORT58_IN_PU), + + /* 49-1 (FN) */ + PINMUX_DATA(VBUS0_MARK, PORT0_FN1), + PINMUX_DATA(CPORT0_MARK, PORT1_FN1), + PINMUX_DATA(CPORT1_MARK, PORT2_FN1), + PINMUX_DATA(CPORT2_MARK, PORT3_FN1), + PINMUX_DATA(CPORT3_MARK, PORT4_FN1), + PINMUX_DATA(CPORT4_MARK, PORT5_FN1), + PINMUX_DATA(CPORT5_MARK, PORT6_FN1), + PINMUX_DATA(CPORT6_MARK, PORT7_FN1), + PINMUX_DATA(CPORT7_MARK, PORT8_FN1), + PINMUX_DATA(CPORT8_MARK, PORT9_FN1), + PINMUX_DATA(CPORT9_MARK, PORT10_FN1), + PINMUX_DATA(CPORT10_MARK, PORT11_FN1), + PINMUX_DATA(CPORT11_MARK, PORT12_FN1), + PINMUX_DATA(SIN2_MARK, PORT12_FN2), + PINMUX_DATA(CPORT12_MARK, PORT13_FN1), + PINMUX_DATA(XCTS2_MARK, PORT13_FN2), + PINMUX_DATA(CPORT13_MARK, PORT14_FN1), + PINMUX_DATA(RFSPO4_MARK, PORT14_FN2), + PINMUX_DATA(CPORT14_MARK, PORT15_FN1), + PINMUX_DATA(RFSPO5_MARK, PORT15_FN2), + PINMUX_DATA(CPORT15_MARK, PORT16_FN1), + PINMUX_DATA(CPORT16_MARK, PORT17_FN1), + PINMUX_DATA(CPORT17_MARK, PORT18_FN1), + PINMUX_DATA(SOUT2_MARK, PORT18_FN2), + PINMUX_DATA(CPORT18_MARK, PORT19_FN1), + PINMUX_DATA(XRTS2_MARK, PORT19_FN1), + PINMUX_DATA(CPORT19_MARK, PORT20_FN1), + PINMUX_DATA(CPORT20_MARK, PORT21_FN1), + PINMUX_DATA(RFSPO6_MARK, PORT21_FN2), + PINMUX_DATA(CPORT21_MARK, PORT22_FN1), + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(CPORT22_MARK, PORT23_FN1), + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(CPORT23_MARK, PORT24_FN1), + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(RFSPO7_MARK, PORT24_FN3), + PINMUX_DATA(MPORT0_MARK, PORT25_FN1), + PINMUX_DATA(MPORT1_MARK, PORT26_FN1), + PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1), + PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1), + PINMUX_DATA(XMAINPS_MARK, PORT29_FN1), + PINMUX_DATA(XDIVPS_MARK, PORT30_FN1), + PINMUX_DATA(XIDRST_MARK, PORT31_FN1), + PINMUX_DATA(IDCLK_MARK, PORT32_FN1), + PINMUX_DATA(IDIO_MARK, PORT33_FN1), + PINMUX_DATA(SOUT1_MARK, PORT34_FN1), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2), + PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3), + PINMUX_DATA(SIN1_MARK, PORT35_FN1), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2), + PINMUX_DATA(XWUP_MARK, PORT35_FN3), + PINMUX_DATA(XRTS1_MARK, PORT36_FN1), + PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2), + PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3), + PINMUX_DATA(XCTS1_MARK, PORT37_FN1), + PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2), + + /* 49-2 (FN) */ + PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1), + PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3), + PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1), + PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3), + PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3), + PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1), + PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3), + PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1), + PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2), + PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1), + PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2), + PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1), + PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2), + PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1), + PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2), + PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1), + PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2), + PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1), + PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2), + PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1), + PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2), + PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1), + PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2), + PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1), + PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2), + PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1), + PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2), + PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1), + PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2), + PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1), + PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2), + PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1), + PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2), + PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1), + PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2), + PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1), + PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2), + PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1), + PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2), + PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1), + PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2), + PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1), + PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2), + PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1), + PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2), + PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1), + PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1), + PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1), + PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1), + PINMUX_DATA(XTALB1L_MARK, PORT65_FN1), + PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2), + PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2), + PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2), + PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2), + PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2), + PINMUX_DATA(GPS_IM_MARK, PORT71_FN1), + PINMUX_DATA(GPS_IS_MARK, PORT72_FN1), + PINMUX_DATA(GPS_QM_MARK, PORT73_FN1), + PINMUX_DATA(GPS_QS_MARK, PORT74_FN1), + PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1), + PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3), + PINMUX_DATA(SIUCKB_MARK, PORT76_FN1), + PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3), + PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1), + PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2), + PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3), + PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1), + PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2), + PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3), + PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1), + PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2), + PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3), + PINMUX_DATA(SIUBILR_MARK, PORT80_FN1), + PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3), + PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1), + PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3), + PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1), + PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3), + PINMUX_DATA(NMI_MARK, PORT83_FN1), + PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3), + PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1), + PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3), + PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3), + PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3), + PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1), + PINMUX_DATA(PWEN_MARK, PORT88_FN1), + PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2), + PINMUX_DATA(OVCN_MARK, PORT89_FN1), + PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2), + PINMUX_DATA(OVCN2_MARK, PORT90_FN1), + PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2), + + /* 49-3 (FN) */ + PINMUX_DATA(RFSPO1_MARK, PORT91_FN1), + PINMUX_DATA(RFSPO2_MARK, PORT92_FN1), + PINMUX_DATA(RFSPO3_MARK, PORT93_FN1), + PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2), + PINMUX_DATA(USBTERM_MARK, PORT94_FN1), + PINMUX_DATA(EXTLP_MARK, PORT94_FN2), + PINMUX_DATA(IDIN_MARK, PORT95_FN1), + PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1), + PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2), + PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1), + PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2), + PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1), + PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1), + PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1), + PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2), + PINMUX_DATA(A0_EA0_MARK, PORT101_FN1), + PINMUX_DATA(BS_MARK, PORT101_FN2), + PINMUX_DATA(A14_EA14_MARK, PORT102_FN1), + PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2), + PINMUX_DATA(A15_EA15_MARK, PORT103_FN1), + PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2), + PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3), + PINMUX_DATA(A16_EA16_MARK, PORT104_FN1), + PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2), + PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4), + PINMUX_DATA(A17_EA17_MARK, PORT105_FN1), + PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2), + PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4), + PINMUX_DATA(A18_EA18_MARK, PORT106_FN1), + PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2), + PINMUX_DATA(DV_DL0_MARK, PORT106_FN3), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4), + PINMUX_DATA(A19_EA19_MARK, PORT107_FN1), + PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2), + PINMUX_DATA(DV_DL1_MARK, PORT107_FN3), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4), + PINMUX_DATA(A20_EA20_MARK, PORT108_FN1), + PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2), + PINMUX_DATA(DV_DL2_MARK, PORT108_FN3), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4), + PINMUX_DATA(A21_EA21_MARK, PORT109_FN1), + PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2), + PINMUX_DATA(DV_DL3_MARK, PORT109_FN3), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4), + PINMUX_DATA(A22_EA22_MARK, PORT110_FN1), + PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2), + PINMUX_DATA(DV_DL4_MARK, PORT110_FN3), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4), + PINMUX_DATA(A23_EA23_MARK, PORT111_FN1), + PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2), + PINMUX_DATA(DV_DL5_MARK, PORT111_FN3), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4), + PINMUX_DATA(A24_EA24_MARK, PORT112_FN1), + PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2), + PINMUX_DATA(DV_DL6_MARK, PORT112_FN3), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4), + PINMUX_DATA(A25_EA25_MARK, PORT113_FN1), + PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2), + PINMUX_DATA(DV_DL7_MARK, PORT113_FN3), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4), + PINMUX_DATA(A26_MARK, PORT114_FN1), + PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2), + PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3), + PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1), + PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1), + PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1), + PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1), + PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1), + PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1), + PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1), + PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1), + PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1), + PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1), + PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1), + PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1), + PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1), + PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1), + PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1), + PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1), + PINMUX_DATA(CS4_MARK, PORT131_FN1), + PINMUX_DATA(CS5A_MARK, PORT132_FN1), + PINMUX_DATA(CS5B_MARK, PORT133_FN1), + PINMUX_DATA(FCE1_MARK, PORT133_FN2), + PINMUX_DATA(CS6B_MARK, PORT134_FN1), + PINMUX_DATA(XCS2_MARK, PORT134_FN2), + PINMUX_DATA(FCE0_MARK, PORT135_FN1), + PINMUX_DATA(CS6A_MARK, PORT136_FN1), + PINMUX_DATA(DACK0_MARK, PORT136_FN2), + PINMUX_DATA(WAIT_MARK, PORT137_FN1), + PINMUX_DATA(DREQ0_MARK, PORT137_FN2), + PINMUX_DATA(RD_XRD_MARK, PORT138_FN1), + PINMUX_DATA(A27_MARK, PORT139_FN1), + PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2), + PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1), + PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1), + PINMUX_DATA(FRB_MARK, PORT142_FN1), + PINMUX_DATA(CKO_MARK, PORT143_FN1), + PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1), + PINMUX_DATA(NBRST_MARK, PORT145_FN1), + + /* 49-4 (FN) */ + PINMUX_DATA(RFSPO0_MARK, PORT146_FN1), + PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2), + PINMUX_DATA(TSTMD_MARK, PORT147_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT148_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT149_FN1), + PINMUX_DATA(VIO_D0_MARK, PORT150_FN1), + PINMUX_DATA(VIO_D1_MARK, PORT151_FN1), + PINMUX_DATA(VIO_D2_MARK, PORT152_FN1), + PINMUX_DATA(VIO_D3_MARK, PORT153_FN1), + PINMUX_DATA(VIO_D4_MARK, PORT154_FN1), + PINMUX_DATA(VIO_D5_MARK, PORT155_FN1), + PINMUX_DATA(VIO_D6_MARK, PORT156_FN1), + PINMUX_DATA(VIO_D7_MARK, PORT157_FN1), + PINMUX_DATA(VIO_D8_MARK, PORT158_FN1), + PINMUX_DATA(VIO_D9_MARK, PORT159_FN1), + PINMUX_DATA(VIO_D10_MARK, PORT160_FN1), + PINMUX_DATA(VIO_D11_MARK, PORT161_FN1), + PINMUX_DATA(VIO_D12_MARK, PORT162_FN1), + PINMUX_DATA(VIO_D13_MARK, PORT163_FN1), + PINMUX_DATA(VIO_D14_MARK, PORT164_FN1), + PINMUX_DATA(VIO_D15_MARK, PORT165_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1), + PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1), + PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2), + PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2), + PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1), + PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2), + PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3), + PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1), + PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2), + PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3), + PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1), + PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2), + PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3), + PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1), + PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2), + PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3), + PINMUX_DATA(LCDD0_MARK, PORT175_FN1), + PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2), + PINMUX_DATA(DV_D0_MARK, PORT175_FN3), + PINMUX_DATA(SIUCKA_MARK, PORT175_FN4), + PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5), + PINMUX_DATA(LCDD1_MARK, PORT176_FN1), + PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2), + PINMUX_DATA(DV_D1_MARK, PORT176_FN3), + PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5), + PINMUX_DATA(LCDD2_MARK, PORT177_FN1), + PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2), + PINMUX_DATA(DV_D2_MARK, PORT177_FN3), + PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4), + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5), + PINMUX_DATA(LCDD3_MARK, PORT178_FN1), + PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2), + PINMUX_DATA(DV_D3_MARK, PORT178_FN3), + PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5), + PINMUX_DATA(LCDD4_MARK, PORT179_FN1), + PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2), + PINMUX_DATA(DV_D4_MARK, PORT179_FN3), + PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4), + PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5), + PINMUX_DATA(LCDD5_MARK, PORT180_FN1), + PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2), + PINMUX_DATA(DV_D5_MARK, PORT180_FN3), + PINMUX_DATA(SIUAILR_MARK, PORT180_FN4), + PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5), + PINMUX_DATA(LCDD6_MARK, PORT181_FN1), + PINMUX_DATA(DV_D6_MARK, PORT181_FN3), + PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4), + PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5), + PINMUX_DATA(XWR2_MARK, PORT181_FN7), + PINMUX_DATA(LCDD7_MARK, PORT182_FN1), + PINMUX_DATA(DV_D7_MARK, PORT182_FN3), + PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4), + PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5), + PINMUX_DATA(XWR3_MARK, PORT182_FN7), + PINMUX_DATA(LCDD8_MARK, PORT183_FN1), + PINMUX_DATA(DV_D8_MARK, PORT183_FN3), + PINMUX_DATA(D16_MARK, PORT183_FN6), + PINMUX_DATA(ED16_MARK, PORT183_FN7), + PINMUX_DATA(LCDD9_MARK, PORT184_FN1), + PINMUX_DATA(DV_D9_MARK, PORT184_FN3), + PINMUX_DATA(D17_MARK, PORT184_FN6), + PINMUX_DATA(ED17_MARK, PORT184_FN7), + PINMUX_DATA(LCDD10_MARK, PORT185_FN1), + PINMUX_DATA(DV_D10_MARK, PORT185_FN3), + PINMUX_DATA(D18_MARK, PORT185_FN6), + PINMUX_DATA(ED18_MARK, PORT185_FN7), + PINMUX_DATA(LCDD11_MARK, PORT186_FN1), + PINMUX_DATA(DV_D11_MARK, PORT186_FN3), + PINMUX_DATA(D19_MARK, PORT186_FN6), + PINMUX_DATA(ED19_MARK, PORT186_FN7), + PINMUX_DATA(LCDD12_MARK, PORT187_FN1), + PINMUX_DATA(DV_D12_MARK, PORT187_FN3), + PINMUX_DATA(D20_MARK, PORT187_FN6), + PINMUX_DATA(ED20_MARK, PORT187_FN7), + PINMUX_DATA(LCDD13_MARK, PORT188_FN1), + PINMUX_DATA(DV_D13_MARK, PORT188_FN3), + PINMUX_DATA(D21_MARK, PORT188_FN6), + PINMUX_DATA(ED21_MARK, PORT188_FN7), + PINMUX_DATA(LCDD14_MARK, PORT189_FN1), + PINMUX_DATA(DV_D14_MARK, PORT189_FN3), + PINMUX_DATA(D22_MARK, PORT189_FN6), + PINMUX_DATA(ED22_MARK, PORT189_FN7), + PINMUX_DATA(LCDD15_MARK, PORT190_FN1), + PINMUX_DATA(DV_D15_MARK, PORT190_FN3), + PINMUX_DATA(D23_MARK, PORT190_FN6), + PINMUX_DATA(ED23_MARK, PORT190_FN7), + PINMUX_DATA(LCDD16_MARK, PORT191_FN1), + PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3), + PINMUX_DATA(D24_MARK, PORT191_FN6), + PINMUX_DATA(ED24_MARK, PORT191_FN7), + PINMUX_DATA(LCDD17_MARK, PORT192_FN1), + PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3), + PINMUX_DATA(D25_MARK, PORT192_FN6), + PINMUX_DATA(ED25_MARK, PORT192_FN7), + PINMUX_DATA(LCDD18_MARK, PORT193_FN1), + PINMUX_DATA(DREQ2_MARK, PORT193_FN2), + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5), + PINMUX_DATA(D26_MARK, PORT193_FN6), + PINMUX_DATA(ED26_MARK, PORT193_FN7), + PINMUX_DATA(LCDD19_MARK, PORT194_FN1), + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5), + PINMUX_DATA(D27_MARK, PORT194_FN6), + PINMUX_DATA(ED27_MARK, PORT194_FN7), + PINMUX_DATA(LCDD20_MARK, PORT195_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2), + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5), + PINMUX_DATA(D28_MARK, PORT195_FN6), + PINMUX_DATA(ED28_MARK, PORT195_FN7), + PINMUX_DATA(LCDD21_MARK, PORT196_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2), + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5), + PINMUX_DATA(D29_MARK, PORT196_FN6), + PINMUX_DATA(ED29_MARK, PORT196_FN7), + PINMUX_DATA(LCDD22_MARK, PORT197_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2), + PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5), + PINMUX_DATA(D30_MARK, PORT197_FN6), + PINMUX_DATA(ED30_MARK, PORT197_FN7), + PINMUX_DATA(LCDD23_MARK, PORT198_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2), + PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5), + PINMUX_DATA(D31_MARK, PORT198_FN6), + PINMUX_DATA(ED31_MARK, PORT198_FN7), + PINMUX_DATA(LCDDCK_MARK, PORT199_FN1), + PINMUX_DATA(LCDWR_MARK, PORT199_FN2), + PINMUX_DATA(DV_CKO_MARK, PORT199_FN3), + PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4), + PINMUX_DATA(LCDRD_MARK, PORT200_FN1), + PINMUX_DATA(DACK2_MARK, PORT200_FN2), + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5), + + /* 49-5 (FN) */ + PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1), + PINMUX_DATA(LCDCS_MARK, PORT201_FN2), + PINMUX_DATA(LCDCS2_MARK, PORT201_FN3), + PINMUX_DATA(DACK3_MARK, PORT201_FN4), + PINMUX_DATA(LCDDISP_MARK, PORT202_FN1), + PINMUX_DATA(LCDRS_MARK, PORT202_FN2), + PINMUX_DATA(DREQ3_MARK, PORT202_FN4), + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5), + PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1), + PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2), + PINMUX_DATA(DV_CKI_MARK, PORT203_FN3), + PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1), + PINMUX_DATA(DREQ1_MARK, PORT204_FN3), + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5), + PINMUX_DATA(LCDDON_MARK, PORT205_FN1), + PINMUX_DATA(LCDDON2_MARK, PORT205_FN2), + PINMUX_DATA(DACK1_MARK, PORT205_FN3), + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5), + PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1), + PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1), + PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1), + PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1), + PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1), + PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1), + PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1), + PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1), + PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1), + PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1), + PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1), + PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2), + PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2), + PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2), + PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1), + PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2), + PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1), + PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2), + PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1), + PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1), + PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2), + PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1), + PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1), + PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1), + PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2), + PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1), + PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1), + PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2), + PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1), + PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4), + PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3), + PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4), + PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3), + PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4), + PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5), + PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3), + PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5), + PINMUX_DATA(M13_BSW_MARK, PORT243_FN2), + PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5), + PINMUX_DATA(M14_GSW_MARK, PORT244_FN2), + PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5), + PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1), + PINMUX_DATA(M15_RSW_MARK, PORT245_FN2), + PINMUX_DATA(SOUT3_MARK, PORT246_FN1), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2), + PINMUX_DATA(SIN3_MARK, PORT247_FN1), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2), + PINMUX_DATA(XRTS3_MARK, PORT248_FN1), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2), + PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5), + PINMUX_DATA(XCTS3_MARK, PORT249_FN1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2), + PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5), + PINMUX_DATA(DINT_MARK, PORT250_FN1), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2), + PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4), + PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1), + PINMUX_DATA(TCK2_MARK, PORT251_FN2), + PINMUX_DATA(SDHICD0_MARK, PORT252_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1), + PINMUX_DATA(TMS2_MARK, PORT253_FN2), + PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1), + PINMUX_DATA(TDO2_MARK, PORT254_FN2), + PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1), + PINMUX_DATA(TDI2_MARK, PORT255_FN2), + PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1), + PINMUX_DATA(RTCK2_MARK, PORT256_FN2), + + /* 49-6 (FN) */ + PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1), + PINMUX_DATA(TRST2_MARK, PORT257_FN2), + PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1), + PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2), + PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1), + PINMUX_DATA(TCK3_MARK, PORT259_FN4), + PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1), + PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3), + PINMUX_DATA(TMS3_MARK, PORT260_FN4), + PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1), + PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2), + PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3), + PINMUX_DATA(TDO3_MARK, PORT261_FN4), + PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1), + PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2), + PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3), + PINMUX_DATA(TDI3_MARK, PORT262_FN4), + PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1), + PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2), + PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3), + PINMUX_DATA(RTCK3_MARK, PORT263_FN4), + PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1), + PINMUX_DATA(TRST3_MARK, PORT264_FN4), + PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1), + PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2), + PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1), + PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2), + PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1), + PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2), + PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1), + PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2), + PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1), + PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2), + PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1), + PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1), + PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_273() _273(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + /* 49-1 -> 49-6 (GPIO) */ + GPIO_PORT_273(), + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU), + GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU), + GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU), + GPIO_FN(PORT58_KEYIN6_PU), + + /* 49-1 (FN) */ + GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2), + GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6), + GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10), + GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2), + GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5), + GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2), + GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20), + GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22), + GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7), + GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2), + GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK), + GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), + GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP), + GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK), + GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS), + + /* 49-2 (FN) */ + GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1), + GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK), + GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0), + GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1), + GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2), + GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3), + GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4), + GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5), + GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0), + GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1), + GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2), + GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC), + GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK), + GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD), + GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD), + GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3), + GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4), + GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5), + GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6), + GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1), + GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2), + GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A), + GPIO_FN(XTALB1L), + GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS), + GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK), + GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD), + GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD), + GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS), + GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS), + GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0), + GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1), + GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2), + GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3), + GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0), + GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1), + GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2), + GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3), + GPIO_FN(NMI), GPIO_FN(TPU4TO0), + GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3), + GPIO_FN(IRQ_TMPB), + GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1), + GPIO_FN(OVCN), GPIO_FN(MFG1_IN1), + GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2), + + /* 49-3 (FN) */ + GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3), + GPIO_FN(PORT93_VIO_CKO2), + GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN), + GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1), + GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2), + GPIO_FN(SCIFA5_RXD), + GPIO_FN(SCIFA5_TXD), + GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1), + GPIO_FN(A0_EA0), GPIO_FN(BS), + GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0), + GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL), + GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2), + GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3), + GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4), + GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5), + GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0), + GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1), + GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2), + GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3), + GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4), + GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5), + GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL), + GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2), + GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5), + GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8), + GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11), + GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13), + GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15), + GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1), + GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A), + GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD), + GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE), + GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO), + GPIO_FN(NBRSTOUT), GPIO_FN(NBRST), + + /* 49-4 (FN) */ + GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD), + GPIO_FN(VIO_VD), GPIO_FN(VIO_HD), + GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2), + GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5), + GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8), + GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11), + GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14), + GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), + GPIO_FN(VIO_CKO), + GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2), + GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0), + GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1), + GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2), + GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3), + GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0), + GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2), + GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1), + GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2), + GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3), + GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4), + GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2), + GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5), + GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2), + GPIO_FN(LCDD6), GPIO_FN(DV_D6), + GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2), + GPIO_FN(LCDD7), GPIO_FN(DV_D7), + GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3), + GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16), + GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17), + GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18), + GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19), + GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20), + GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21), + GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22), + GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23), + GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24), + GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25), + GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK), + GPIO_FN(D26), GPIO_FN(ED26), + GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC), + GPIO_FN(D27), GPIO_FN(ED27), + GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0), + GPIO_FN(D28), GPIO_FN(ED28), + GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1), + GPIO_FN(D29), GPIO_FN(ED29), + GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1), + GPIO_FN(D30), GPIO_FN(ED30), + GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2), + GPIO_FN(D31), GPIO_FN(ED31), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD), + GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC), + + /* 49-5 (FN) */ + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK), + GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI), + GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD), + GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD), + GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3), + GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7), + GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR), + GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR), + GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0), + GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1), + GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON), + GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS), + GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD), + GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2), + GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2), + GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2), + GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3), + GPIO_FN(MSIOF1_SS2), + GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT), + GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), + GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3), + GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3), + GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1), + GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK), + GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC), + GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD), + GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW), + GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), + GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), + GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2), + GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD), + GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3), + GPIO_FN(SDHICLK0), GPIO_FN(TCK2), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), GPIO_FN(TMS2), + GPIO_FN(SDHID0_1), GPIO_FN(TDO2), + GPIO_FN(SDHID0_2), GPIO_FN(TDI2), + GPIO_FN(SDHID0_3), GPIO_FN(RTCK2), + + /* 49-6 (FN) */ + GPIO_FN(SDHICMD0), GPIO_FN(TRST2), + GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2), + GPIO_FN(SDHICLK1), GPIO_FN(TCK3), + GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), + GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3), + GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2), + GPIO_FN(TS_SDAT2), GPIO_FN(TDO3), + GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), + GPIO_FN(TS_SDEN2), GPIO_FN(TDI3), + GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), + GPIO_FN(TS_SCK2), GPIO_FN(RTCK3), + GPIO_FN(SDHICMD1), GPIO_FN(TRST3), + GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK), + GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD), + GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS), + GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD), + GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS), + GPIO_FN(SDHICMD2), + GPIO_FN(RESETOUTS), + GPIO_FN(DIVLOCK), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ + PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + PORTCR(84, 0xe6050054), /* PORT84CR */ + PORTCR(85, 0xe6050055), /* PORT85CR */ + PORTCR(86, 0xe6050056), /* PORT86CR */ + PORTCR(87, 0xe6050057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6051060), /* PORT96CR */ + PORTCR(97, 0xe6051061), /* PORT97CR */ + PORTCR(98, 0xe6051062), /* PORT98CR */ + PORTCR(99, 0xe6051063), /* PORT99CR */ + + PORTCR(100, 0xe6051064), /* PORT100CR */ + PORTCR(101, 0xe6051065), /* PORT101CR */ + PORTCR(102, 0xe6051066), /* PORT102CR */ + PORTCR(103, 0xe6051067), /* PORT103CR */ + PORTCR(104, 0xe6051068), /* PORT104CR */ + PORTCR(105, 0xe6051069), /* PORT105CR */ + PORTCR(106, 0xe605106a), /* PORT106CR */ + PORTCR(107, 0xe605106b), /* PORT107CR */ + PORTCR(108, 0xe605106c), /* PORT108CR */ + PORTCR(109, 0xe605106d), /* PORT109CR */ + + PORTCR(110, 0xe605106e), /* PORT110CR */ + PORTCR(111, 0xe605106f), /* PORT111CR */ + PORTCR(112, 0xe6051070), /* PORT112CR */ + PORTCR(113, 0xe6051071), /* PORT113CR */ + PORTCR(114, 0xe6051072), /* PORT114CR */ + PORTCR(115, 0xe6051073), /* PORT115CR */ + PORTCR(116, 0xe6051074), /* PORT116CR */ + PORTCR(117, 0xe6051075), /* PORT117CR */ + PORTCR(118, 0xe6051076), /* PORT118CR */ + PORTCR(119, 0xe6051077), /* PORT119CR */ + + PORTCR(120, 0xe6051078), /* PORT120CR */ + PORTCR(121, 0xe6051079), /* PORT121CR */ + PORTCR(122, 0xe605107a), /* PORT122CR */ + PORTCR(123, 0xe605107b), /* PORT123CR */ + PORTCR(124, 0xe605107c), /* PORT124CR */ + PORTCR(125, 0xe605107d), /* PORT125CR */ + PORTCR(126, 0xe605107e), /* PORT126CR */ + PORTCR(127, 0xe605107f), /* PORT127CR */ + PORTCR(128, 0xe6051080), /* PORT128CR */ + PORTCR(129, 0xe6051081), /* PORT129CR */ + + PORTCR(130, 0xe6051082), /* PORT130CR */ + PORTCR(131, 0xe6051083), /* PORT131CR */ + PORTCR(132, 0xe6051084), /* PORT132CR */ + PORTCR(133, 0xe6051085), /* PORT133CR */ + PORTCR(134, 0xe6051086), /* PORT134CR */ + PORTCR(135, 0xe6051087), /* PORT135CR */ + PORTCR(136, 0xe6051088), /* PORT136CR */ + PORTCR(137, 0xe6051089), /* PORT137CR */ + PORTCR(138, 0xe605108a), /* PORT138CR */ + PORTCR(139, 0xe605108b), /* PORT139CR */ + + PORTCR(140, 0xe605108c), /* PORT140CR */ + PORTCR(141, 0xe605108d), /* PORT141CR */ + PORTCR(142, 0xe605108e), /* PORT142CR */ + PORTCR(143, 0xe605108f), /* PORT143CR */ + PORTCR(144, 0xe6051090), /* PORT144CR */ + PORTCR(145, 0xe6051091), /* PORT145CR */ + PORTCR(146, 0xe6051092), /* PORT146CR */ + PORTCR(147, 0xe6051093), /* PORT147CR */ + PORTCR(148, 0xe6051094), /* PORT148CR */ + PORTCR(149, 0xe6051095), /* PORT149CR */ + + PORTCR(150, 0xe6051096), /* PORT150CR */ + PORTCR(151, 0xe6051097), /* PORT151CR */ + PORTCR(152, 0xe6051098), /* PORT152CR */ + PORTCR(153, 0xe6051099), /* PORT153CR */ + PORTCR(154, 0xe605109a), /* PORT154CR */ + PORTCR(155, 0xe605109b), /* PORT155CR */ + PORTCR(156, 0xe605109c), /* PORT156CR */ + PORTCR(157, 0xe605109d), /* PORT157CR */ + PORTCR(158, 0xe605109e), /* PORT158CR */ + PORTCR(159, 0xe605109f), /* PORT159CR */ + + PORTCR(160, 0xe60510a0), /* PORT160CR */ + PORTCR(161, 0xe60510a1), /* PORT161CR */ + PORTCR(162, 0xe60510a2), /* PORT162CR */ + PORTCR(163, 0xe60510a3), /* PORT163CR */ + PORTCR(164, 0xe60510a4), /* PORT164CR */ + PORTCR(165, 0xe60510a5), /* PORT165CR */ + PORTCR(166, 0xe60510a6), /* PORT166CR */ + PORTCR(167, 0xe60510a7), /* PORT167CR */ + PORTCR(168, 0xe60510a8), /* PORT168CR */ + PORTCR(169, 0xe60510a9), /* PORT169CR */ + + PORTCR(170, 0xe60510aa), /* PORT170CR */ + PORTCR(171, 0xe60510ab), /* PORT171CR */ + PORTCR(172, 0xe60510ac), /* PORT172CR */ + PORTCR(173, 0xe60510ad), /* PORT173CR */ + PORTCR(174, 0xe60510ae), /* PORT174CR */ + PORTCR(175, 0xe60520af), /* PORT175CR */ + PORTCR(176, 0xe60520b0), /* PORT176CR */ + PORTCR(177, 0xe60520b1), /* PORT177CR */ + PORTCR(178, 0xe60520b2), /* PORT178CR */ + PORTCR(179, 0xe60520b3), /* PORT179CR */ + + PORTCR(180, 0xe60520b4), /* PORT180CR */ + PORTCR(181, 0xe60520b5), /* PORT181CR */ + PORTCR(182, 0xe60520b6), /* PORT182CR */ + PORTCR(183, 0xe60520b7), /* PORT183CR */ + PORTCR(184, 0xe60520b8), /* PORT184CR */ + PORTCR(185, 0xe60520b9), /* PORT185CR */ + PORTCR(186, 0xe60520ba), /* PORT186CR */ + PORTCR(187, 0xe60520bb), /* PORT187CR */ + PORTCR(188, 0xe60520bc), /* PORT188CR */ + PORTCR(189, 0xe60520bd), /* PORT189CR */ + + PORTCR(190, 0xe60520be), /* PORT190CR */ + PORTCR(191, 0xe60520bf), /* PORT191CR */ + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60520e0), /* PORT224CR */ + PORTCR(225, 0xe60520e1), /* PORT225CR */ + PORTCR(226, 0xe60520e2), /* PORT226CR */ + PORTCR(227, 0xe60520e3), /* PORT227CR */ + PORTCR(228, 0xe60520e4), /* PORT228CR */ + PORTCR(229, 0xe60520e5), /* PORT229CR */ + + PORTCR(230, 0xe60520e6), /* PORT230CR */ + PORTCR(231, 0xe60520e7), /* PORT231CR */ + PORTCR(232, 0xe60520e8), /* PORT232CR */ + PORTCR(233, 0xe60520e9), /* PORT233CR */ + PORTCR(234, 0xe60520ea), /* PORT234CR */ + PORTCR(235, 0xe60520eb), /* PORT235CR */ + PORTCR(236, 0xe60530ec), /* PORT236CR */ + PORTCR(237, 0xe60530ed), /* PORT237CR */ + PORTCR(238, 0xe60530ee), /* PORT238CR */ + PORTCR(239, 0xe60530ef), /* PORT239CR */ + + PORTCR(240, 0xe60530f0), /* PORT240CR */ + PORTCR(241, 0xe60530f1), /* PORT241CR */ + PORTCR(242, 0xe60530f2), /* PORT242CR */ + PORTCR(243, 0xe60530f3), /* PORT243CR */ + PORTCR(244, 0xe60530f4), /* PORT244CR */ + PORTCR(245, 0xe60530f5), /* PORT245CR */ + PORTCR(246, 0xe60530f6), /* PORT246CR */ + PORTCR(247, 0xe60530f7), /* PORT247CR */ + PORTCR(248, 0xe60530f8), /* PORT248CR */ + PORTCR(249, 0xe60530f9), /* PORT249CR */ + + PORTCR(250, 0xe60530fa), /* PORT250CR */ + PORTCR(251, 0xe60530fb), /* PORT251CR */ + PORTCR(252, 0xe60530fc), /* PORT252CR */ + PORTCR(253, 0xe60530fd), /* PORT253CR */ + PORTCR(254, 0xe60530fe), /* PORT254CR */ + PORTCR(255, 0xe60530ff), /* PORT255CR */ + PORTCR(256, 0xe6053100), /* PORT256CR */ + PORTCR(257, 0xe6053101), /* PORT257CR */ + PORTCR(258, 0xe6053102), /* PORT258CR */ + PORTCR(259, 0xe6053103), /* PORT259CR */ + + PORTCR(260, 0xe6053104), /* PORT260CR */ + PORTCR(261, 0xe6053105), /* PORT261CR */ + PORTCR(262, 0xe6053106), /* PORT262CR */ + PORTCR(263, 0xe6053107), /* PORT263CR */ + PORTCR(264, 0xe6053108), /* PORT264CR */ + PORTCR(265, 0xe6053109), /* PORT265CR */ + PORTCR(266, 0xe605310a), /* PORT266CR */ + PORTCR(267, 0xe605310b), /* PORT267CR */ + PORTCR(268, 0xe605310c), /* PORT268CR */ + PORTCR(269, 0xe605310d), /* PORT269CR */ + + PORTCR(270, 0xe605310e), /* PORT270CR */ + PORTCR(271, 0xe605310f), /* PORT271CR */ + PORTCR(272, 0xe6053110), /* PORT272CR */ + + { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSELBCR_MSEL2_0, MSELBCR_MSEL2_1, + 0, 0, + 0, 0 } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { + PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { }, +}; + +static struct pinmux_info sh7367_pinmux_info = { + .name = "sh7367_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_DIVLOCK, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7367_pinmux_init(void) +{ + register_pinmux(&sh7367_pinmux_info); +} From 3a7b802d1a8c279876ec74094d71f3c6c45d8030 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 10 Feb 2010 20:13:31 +0900 Subject: [PATCH 16/27] ARM: mach-shmobile: G3EVM USBHS support Add G3EVM platform data and a magic setup sequence to initialize the r8a66597 block aka USBHS in sh7367. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-g3evm.c | 58 +++++++++++++++++++++++++++ arch/arm/mach-shmobile/clock-sh7367.c | 7 ++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 28ee589caba6..f36c9a94d326 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -86,9 +87,49 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* USBHS */ +void usb_host_port_power(int port, int power) +{ + if (!power) /* only power-on supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ + __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); +} + +static struct r8a66597_platdata usb_host_data = { + .on_chip = 1, + .port_power = usb_host_port_power, +}; + +static struct resource usb_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xe6890000, + .end = 0xe68900e5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .platform_data = &usb_host_data, + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; static struct platform_device *g3evm_devices[] __initdata = { &nor_flash_device, + &usb_host_device, }; static struct map_desc g3evm_io_desc[] __initdata = { @@ -138,6 +179,23 @@ static void __init g3evm_init(void) gpio_request(GPIO_FN_SCIFA1_CTS, NULL); gpio_request(GPIO_FN_SCIFA1_RTS, NULL); + /* USBHS */ + gpio_request(GPIO_FN_VBUS0, NULL); + gpio_request(GPIO_FN_PWEN, NULL); + gpio_request(GPIO_FN_OVCN, NULL); + gpio_request(GPIO_FN_OVCN2, NULL); + gpio_request(GPIO_FN_EXTLP, NULL); + gpio_request(GPIO_FN_IDIN, NULL); + + /* enable clock in SYMSTPCR2 */ + __raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048); + + /* setup USB phy */ + __raw_writew(0x0300, 0xe605810a); /* USBCR1 */ + __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ + __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ + __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + sh7367_add_standard_devices(); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 3b2e3f2fc7ea..58bd54e1113a 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -70,11 +70,18 @@ static struct clk r_clk = { .rate = 32768, }; +/* a static usb0 for now - enough to get r8a66597 working */ +static struct clk usb0_clk = { + .name = "usb0", +}; + static struct clk_lookup lookups[] = { { .clk = &peripheral_clk, }, { .clk = &r_clk, + }, { + .clk = &usb0_clk, } }; From 276b4f623cfd30320c004269725683ba8f262bb6 Mon Sep 17 00:00:00 2001 From: NISHIMOTO Hiroki Date: Fri, 12 Feb 2010 08:10:06 +0000 Subject: [PATCH 17/27] ARM: mach-shmobile: sh7377 and G4EVM pinmux support Add support for the sh 7377 pinmux using drivers/sh/pfc.c and some LEDs on G4EVM. Signed-off-by: NISHIMOTO Hiroki Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/board-g4evm.c | 24 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/sh7377.h | 360 ++++ arch/arm/mach-shmobile/pfc-sh7377.c | 1766 ++++++++++++++++++ 6 files changed, 2153 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7377.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7377.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 639df5ffbcef..a96c25a26272 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -36,6 +36,7 @@ config MACH_G3EVM config MACH_G4EVM bool "G4EVM board" depends on ARCH_SH7377 + select ARCH_REQUIRE_GPIOLIB config MACH_AP4EVB bool "AP4EVB board" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 9ef2630d1432..ce01951edda3 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Pinmux setup pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o +pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) # Board objects diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 0ddde038588e..ef4b0f59af49 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -113,6 +115,28 @@ static void __init g4evm_map_io(void) static void __init g4evm_init(void) { + sh7377_pinmux_init(); + + /* Lit DS14 LED */ + gpio_request(GPIO_PORT109, NULL); + gpio_direction_output(GPIO_PORT109, 1); + gpio_export(GPIO_PORT109, 1); + + /* Lit DS15 LED */ + gpio_request(GPIO_PORT110, NULL); + gpio_direction_output(GPIO_PORT110, 1); + gpio_export(GPIO_PORT110, 1); + + /* Lit DS16 LED */ + gpio_request(GPIO_PORT112, NULL); + gpio_direction_output(GPIO_PORT112, 1); + gpio_export(GPIO_PORT112, 1); + + /* Lit DS17 LED */ + gpio_request(GPIO_PORT113, NULL); + gpio_direction_output(GPIO_PORT113, 1); + gpio_export(GPIO_PORT113, 1); + sh7377_add_standard_devices(); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index a4846001e89a..d6f927b4bef6 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -13,6 +13,7 @@ extern void sh7367_pinmux_init(void); extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); extern void sh7377_add_standard_devices(void); +extern void sh7377_pinmux_init(void); extern void sh7372_init_irq(void); extern void sh7372_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h new file mode 100644 index 000000000000..f580e227dd1c --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7377.h @@ -0,0 +1,360 @@ +#ifndef __ASM_SH7377_H__ +#define __ASM_SH7377_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* 55-1 -> 55-5 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU, + GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU, + GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU, + GPIO_FN_PORT72_KEYIN6_PU, + + /* 55-1 (FN) */ + GPIO_FN_VBUS_0, + GPIO_FN_CPORT0, + GPIO_FN_CPORT1, + GPIO_FN_CPORT2, + GPIO_FN_CPORT3, + GPIO_FN_CPORT4, + GPIO_FN_CPORT5, + GPIO_FN_CPORT6, + GPIO_FN_CPORT7, + GPIO_FN_CPORT8, + GPIO_FN_CPORT9, + GPIO_FN_CPORT10, + GPIO_FN_CPORT11, GPIO_FN_SIN2, + GPIO_FN_CPORT12, GPIO_FN_XCTS2, + GPIO_FN_CPORT13, GPIO_FN_RFSPO4, + GPIO_FN_CPORT14, GPIO_FN_RFSPO5, + GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2, + GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3, + GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2, + GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_CPORT19_MPORT1, + GPIO_FN_CPORT20, GPIO_FN_RFSPO6, + GPIO_FN_CPORT21, GPIO_FN_STATUS0, + GPIO_FN_CPORT22, GPIO_FN_STATUS1, + GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7, + GPIO_FN_B_SYNLD1, + GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK, + GPIO_FN_XMAINPS, + GPIO_FN_XDIVPS, + GPIO_FN_XIDRST, + GPIO_FN_IDCLK, GPIO_FN_IC_DP, + GPIO_FN_IDIO, GPIO_FN_IC_DM, + GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT, + GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK, + GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS, + GPIO_FN_PCMCLKO, + GPIO_FN_SYNC8KO, + + /* 55-2 (FN) */ + GPIO_FN_DNPCM_A, + GPIO_FN_UPPCM_A, + GPIO_FN_VACK, + GPIO_FN_XTALB1L, + GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS, + GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD, + GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS, + GPIO_FN_GPS_IM, + GPIO_FN_GPS_IS, + GPIO_FN_GPS_QM, + GPIO_FN_GPS_QS, + GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, + GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3, + GPIO_FN_FMSIOLR, + GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1, + GPIO_FN_FMSIOBT, + GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2, + GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, + GPIO_FN_OPORT3, GPIO_FN_FMSIILR, + GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, + GPIO_FN_FMSIIBT, + GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0, + GPIO_FN_A0_EA0, GPIO_FN_BS, + GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2, + GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2, + GPIO_FN_TPU0TO1, + GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5, + GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4, + GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6, + GPIO_FN_D0_ED0_NAF0, + GPIO_FN_D1_ED1_NAF1, + GPIO_FN_D2_ED2_NAF2, + GPIO_FN_D3_ED3_NAF3, + GPIO_FN_D4_ED4_NAF4, + GPIO_FN_D5_ED5_NAF5, + GPIO_FN_D6_ED6_NAF6, + GPIO_FN_D7_ED7_NAF7, + GPIO_FN_D8_ED8_NAF8, + GPIO_FN_D9_ED9_NAF9, + GPIO_FN_D10_ED10_NAF10, + GPIO_FN_D11_ED11_NAF11, + GPIO_FN_D12_ED12_NAF12, + GPIO_FN_D13_ED13_NAF13, + GPIO_FN_D14_ED14_NAF14, + GPIO_FN_D15_ED15_NAF15, + GPIO_FN_CS4, + GPIO_FN_CS5A, GPIO_FN_FMSICK, + GPIO_FN_CS5B, GPIO_FN_FCE1, + + /* 55-3 (FN) */ + GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0, + GPIO_FN_FCE0, + GPIO_FN_WAIT, GPIO_FN_DREQ0, + GPIO_FN_RD_XRD, + GPIO_FN_WE0_XWR0_FWE, + GPIO_FN_WE1_XWR1, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT, + GPIO_FN_NBRST, + GPIO_FN_GPS_EPPSIN, + GPIO_FN_LATCHPULSE, + GPIO_FN_LTESIGNAL, + GPIO_FN_LEGACYSTATE, + GPIO_FN_TCKON, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0, + GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2, + GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC, + GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD, + GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3, + GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC, + GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR, + GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2, + GPIO_FN_PORT140_FSIAOBT, + GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3, + GPIO_FN_PORT141_FSIAOSLD, + GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK, + GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR, + GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD, + GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2, + GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5, + GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6, + GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD, + + /* 55-4 (FN) */ + GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0, + GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0, + GPIO_FN_MFG3_IN2, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0, + GPIO_FN_MFG3_IN1, + GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0, + GPIO_FN_MFG3_OUT1, + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI, + GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS, + GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS, + GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD, + GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK, + GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, GPIO_FN_XWR2, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3, + GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16, + GPIO_FN_ED16, + GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17, + GPIO_FN_ED17, + GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18, + GPIO_FN_ED18, + GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19, + GPIO_FN_ED19, + GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20, + GPIO_FN_ED20, + GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21, + GPIO_FN_ED21, + GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22, + GPIO_FN_ED22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0, + GPIO_FN_VIO_DR7, + GPIO_FN_D23, GPIO_FN_ED23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1, + GPIO_FN_VIO_VDR, + GPIO_FN_D24, GPIO_FN_ED24, + GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25, + GPIO_FN_ED25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_ED26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_ED28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_ED29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_ED30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_ED31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3, + GPIO_FN_VIO_CLKR, + GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3, + GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, + GPIO_FN_MSIOF0L_TXD, + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM, + GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG, + GPIO_FN_PORT233_FSIACK, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2, + GPIO_FN_PORT235_FSIAILR, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD, + GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3, + + /* 55-5 (FN) */ + GPIO_FN_MSIOF1_SS2, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS, + GPIO_FN_PORT244_MSIOF2_RXD, + GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS, + GPIO_FN_PORT245_MSIOF2_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, + GPIO_FN_PORT248_MSIOF2_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC, + GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0, + GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0, + GPIO_FN_SDHID0_2, GPIO_FN_TDI2, + GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0, + GPIO_FN_SDHICMD0, GPIO_FN_TRST2, + GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2, + GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1, + GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2, + GPIO_FN_TMS3_SWDIO_MC1, + GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2, + GPIO_FN_TDO3_SWO0_MC1, + GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3, + GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2, + GPIO_FN_RTCK3_SWO1_MC1, + GPIO_FN_SDHICMD1, GPIO_FN_TRST3, + GPIO_FN_RESETOUTS, +}; + +#endif /* __ASM_SH7377_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c new file mode 100644 index 000000000000..79b53d87d91b --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7377.c @@ -0,0 +1,1766 @@ +/* + * sh7377 processor support - PFC hardware block + * + * Copyright (C) 2010 NISHIMOTO Hiroki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _90(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \ + _10(fn, pfx##9, sfx) + +#define _265(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _90(fn, pfx, sfx), \ + _10(fn, pfx##10, sfx), \ + _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ + _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ + _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ + _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ + _1(fn, pfx##118, sfx), \ + _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ + _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ + _10(fn, pfx##15, sfx), \ + _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ + _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ + _1(fn, pfx##164, sfx), \ + _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ + _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ + _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ + _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \ + _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ + _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ + _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ + _1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \ + _1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \ + _1(fn, pfx##264, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_265(str) _265(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_265(IN), /* PORT0_IN -> PORT264_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */ + PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */ + PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */ + PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */ + PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */ + PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */ + PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */ + PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */ + PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */ + PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */ + + MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Special Pull-up / Pull-down Functions */ + PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK, + PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK, + PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK, + PORT72_KEYIN6_PU_MARK, + + /* 55-1 */ + VBUS_0_MARK, + CPORT0_MARK, + CPORT1_MARK, + CPORT2_MARK, + CPORT3_MARK, + CPORT4_MARK, + CPORT5_MARK, + CPORT6_MARK, + CPORT7_MARK, + CPORT8_MARK, + CPORT9_MARK, + CPORT10_MARK, + CPORT11_MARK, SIN2_MARK, + CPORT12_MARK, XCTS2_MARK, + CPORT13_MARK, RFSPO4_MARK, + CPORT14_MARK, RFSPO5_MARK, + CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK, + CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK, + CPORT17_IC_OE_MARK, SOUT2_MARK, + CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK, + CPORT19_MPORT1_MARK, + CPORT20_MARK, RFSPO6_MARK, + CPORT21_MARK, STATUS0_MARK, + CPORT22_MARK, STATUS1_MARK, + CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK, + B_SYNLD1_MARK, + B_SYNLD2_MARK, SYSENMSK_MARK, + XMAINPS_MARK, + XDIVPS_MARK, + XIDRST_MARK, + IDCLK_MARK, IC_DP_MARK, + IDIO_MARK, IC_DM_MARK, + SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK, + SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK, + XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK, + XCTS1_MARK, SCIFA4_CTS_MARK, + PCMCLKO_MARK, + SYNC8KO_MARK, + + /* 55-2 */ + DNPCM_A_MARK, + UPPCM_A_MARK, + VACK_MARK, + XTALB1L_MARK, + GPS_AGC1_MARK, SCIFA0_RTS_MARK, + GPS_AGC4_MARK, SCIFA0_RXD_MARK, + GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK, + GPS_IM_MARK, + GPS_IS_MARK, + GPS_QM_MARK, + GPS_QS_MARK, + FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, + FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK, + FMSIOLR_MARK, + FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK, + FMSIOBT_MARK, + FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK, + FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK, + FMSIILR_MARK, + FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK, + FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK, + A0_EA0_MARK, BS_MARK, + A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK, + A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK, + A14_EA14_MARK, PORT60_KEYOUT5_MARK, + A15_EA15_MARK, PORT61_KEYOUT4_MARK, + A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK, + A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK, + A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK, + A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK, + A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK, + A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK, + A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK, + A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK, + A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK, + A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK, + A26_MARK, PORT72_KEYIN6_MARK, + D0_ED0_NAF0_MARK, + D1_ED1_NAF1_MARK, + D2_ED2_NAF2_MARK, + D3_ED3_NAF3_MARK, + D4_ED4_NAF4_MARK, + D5_ED5_NAF5_MARK, + D6_ED6_NAF6_MARK, + D7_ED7_NAF7_MARK, + D8_ED8_NAF8_MARK, + D9_ED9_NAF9_MARK, + D10_ED10_NAF10_MARK, + D11_ED11_NAF11_MARK, + D12_ED12_NAF12_MARK, + D13_ED13_NAF13_MARK, + D14_ED14_NAF14_MARK, + D15_ED15_NAF15_MARK, + CS4_MARK, + CS5A_MARK, FMSICK_MARK, + CS5B_MARK, FCE1_MARK, + + /* 55-3 */ + CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK, + FCE0_MARK, + WAIT_MARK, DREQ0_MARK, + RD_XRD_MARK, + WE0_XWR0_FWE_MARK, + WE1_XWR1_MARK, + FRB_MARK, + CKO_MARK, + NBRSTOUT_MARK, + NBRST_MARK, + GPS_EPPSIN_MARK, + LATCHPULSE_MARK, + LTESIGNAL_MARK, + LEGACYSTATE_MARK, + TCKON_MARK, + VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK, + VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK, + VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK, + VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK, + VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK, + VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK, + VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK, + VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK, + VIO_D6_MARK, PORT136_KEYIN2_MARK, + VIO_D7_MARK, PORT137_KEYIN3_MARK, + VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK, + VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK, + VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK, + VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK, + VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK, + VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK, + VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK, + VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK, + VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK, + VIO_FIELD_MARK, PORT147_KEYIN5_MARK, + VIO_CKO_MARK, PORT148_KEYIN6_MARK, + A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK, + MFG0_IN2_MARK, + TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, + TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, + SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, + SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, + XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK, + XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK, + + /* 55-4 */ + DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, + PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK, + PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK, + MFG3_IN2_MARK, + PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK, + MFG3_IN1_MARK, + PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK, + MFG3_OUT1_MARK, TPU3TO0_MARK, + LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK, + LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK, + BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK, + BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK, + BBIF2_TXD1_MARK, + LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK, + LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK, + MFG2_OUT2_MARK, + TPU2TO1_MARK, + LCDD6_MARK, XWR2_MARK, + LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK, + LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK, + LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK, + LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK, + LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK, + LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK, + LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK, + LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK, + LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK, + VIO_DR7_MARK, D23_MARK, ED23_MARK, + LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK, + VIO_VDR_MARK, D24_MARK, ED24_MARK, + LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK, + LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK, + LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK, + LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK, + LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK, + LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK, + PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK, + LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK, + LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK, + LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, + SCIFA1_TXD_MARK, OVCN2_MARK, + EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK, + SCIFA1_RTS_MARK, IDIN_MARK, + SCIFA1_RXD_MARK, + SCIFA1_CTS_MARK, MFG1_IN1_MARK, + MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK, + MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK, + MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK, + MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK, + PORT233_FSIACK_MARK, + MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK, + MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK, + MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK, + MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK, + MSIOF1_SS1_MARK, EDBGREQ3_MARK, + + /* 55-5 */ + MSIOF1_SS2_MARK, + SCIFA6_TXD_MARK, + PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, + TPU4TO0_MARK, + PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, + PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, + PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK, + PORT244_MSIOF2_RXD_MARK, + PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK, + PORT245_MSIOF2_TXD_MARK, + PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, + TPU1TO0_MARK, + PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, + TPU3TO1_MARK, + PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, + TPU2TO0_MARK, + PORT248_MSIOF2_TSCK_MARK, + PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK, + SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK, + SDHID0_1_MARK, TDO2_SWO0_MC0_MARK, + SDHID0_2_MARK, TDI2_MARK, + SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK, + SDHICMD0_MARK, TRST2_MARK, + SDHIWP0_MARK, EDBGREQ2_MARK, + SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK, + SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK, + TMS3_SWDIO_MC1_MARK, + SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK, + SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK, + SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK, + SDHICMD1_MARK, TRST3_MARK, + RESETOUTS_MARK, + PINMUX_MARK_END, +}; + +#define PORT_DATA_I(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) + +#define PORT_DATA_I_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +#define PORT_DATA_I_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +#define PORT_DATA_I_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_O(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT) + +#define PORT_DATA_IO(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN) + +#define PORT_DATA_IO_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD) + +#define PORT_DATA_IO_PU(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PU) + +#define PORT_DATA_IO_PU_PD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_OUT, PORT##nr##_IN, \ + PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +static pinmux_enum_t pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + /* 55-1 (GPIO) */ + PORT_DATA_I_PD(0), PORT_DATA_I_PU(1), + PORT_DATA_I_PU(2), PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), + PORT_DATA_I_PU(6), PORT_DATA_I_PU(7), + PORT_DATA_I_PU(8), PORT_DATA_I_PU(9), + PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), + PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13), + PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), + PORT_DATA_O(16), PORT_DATA_IO(17), + PORT_DATA_O(18), PORT_DATA_O(19), + PORT_DATA_O(20), PORT_DATA_O(21), + PORT_DATA_O(22), PORT_DATA_O(23), + PORT_DATA_O(24), PORT_DATA_I_PD(25), + PORT_DATA_I_PD(26), PORT_DATA_O(27), + PORT_DATA_O(28), PORT_DATA_O(29), + PORT_DATA_IO(30), PORT_DATA_IO_PU(31), + PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33), + PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35), + PORT_DATA_O(36), PORT_DATA_IO(37), + + /* 55-2 (GPIO) */ + PORT_DATA_O(38), PORT_DATA_I_PU(39), + PORT_DATA_I_PU_PD(40), PORT_DATA_O(41), + PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43), + PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45), + PORT_DATA_I_PD(46), PORT_DATA_I_PD(47), + PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49), + PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51), + PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53), + PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55), + PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57), + PORT_DATA_IO(58), PORT_DATA_IO(59), + PORT_DATA_IO(60), PORT_DATA_IO(61), + PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), + PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), + PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73), + PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75), + PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77), + PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79), + PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81), + PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83), + PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85), + PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87), + PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89), + PORT_DATA_O(90), PORT_DATA_IO_PU(91), + PORT_DATA_O(92), + + /* 55-3 (GPIO) */ + PORT_DATA_IO_PU(93), + PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO(96), PORT_DATA_IO(97), + PORT_DATA_IO(98), PORT_DATA_I_PU(99), + PORT_DATA_O(100), PORT_DATA_O(101), + PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103), + PORT_DATA_I_PD(104), PORT_DATA_I_PD(105), + PORT_DATA_I_PD(106), PORT_DATA_I_PD(107), + PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109), + PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111), + PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), + PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115), + PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117), + PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128), + PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130), + PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132), + PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134), + PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136), + PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138), + PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140), + PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142), + PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144), + PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146), + PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148), + PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150), + PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152), + PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), + PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156), + PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158), + + /* 55-4 (GPIO) */ + PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160), + PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162), + PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164), + PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193), + PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), + PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199), + PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207), + PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209), + PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), + PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215), + PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217), + PORT_DATA_O(218), PORT_DATA_IO_PD(219), + PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221), + PORT_DATA_IO_PU_PD(222), + PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224), + PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226), + PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228), + PORT_DATA_I_PD(229), PORT_DATA_IO(230), + PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232), + PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234), + PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236), + PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238), + + /* 55-5 (GPIO) */ + PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240), + PORT_DATA_O(241), PORT_DATA_I_PD(242), + PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244), + PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246), + PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248), + PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250), + PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252), + PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254), + PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256), + PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258), + PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260), + PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262), + PORT_DATA_IO_PU_PD(263), + + /* Special Pull-up / Pull-down Functions */ + PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, + PORT66_FN2, PORT66_IN_PU), + PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, + PORT67_FN2, PORT67_IN_PU), + PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, + PORT68_FN2, PORT68_IN_PU), + PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, + PORT69_FN2, PORT69_IN_PU), + PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, + PORT70_FN2, PORT70_IN_PU), + PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, + PORT71_FN2, PORT71_IN_PU), + PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, + PORT72_FN2, PORT72_IN_PU), + + + /* 55-1 (FN) */ + PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), + PINMUX_DATA(CPORT0_MARK, PORT1_FN1), + PINMUX_DATA(CPORT1_MARK, PORT2_FN1), + PINMUX_DATA(CPORT2_MARK, PORT3_FN1), + PINMUX_DATA(CPORT3_MARK, PORT4_FN1), + PINMUX_DATA(CPORT4_MARK, PORT5_FN1), + PINMUX_DATA(CPORT5_MARK, PORT6_FN1), + PINMUX_DATA(CPORT6_MARK, PORT7_FN1), + PINMUX_DATA(CPORT7_MARK, PORT8_FN1), + PINMUX_DATA(CPORT8_MARK, PORT9_FN1), + PINMUX_DATA(CPORT9_MARK, PORT10_FN1), + PINMUX_DATA(CPORT10_MARK, PORT11_FN1), + PINMUX_DATA(CPORT11_MARK, PORT12_FN1), + PINMUX_DATA(SIN2_MARK, PORT12_FN2), + PINMUX_DATA(CPORT12_MARK, PORT13_FN1), + PINMUX_DATA(XCTS2_MARK, PORT13_FN2), + PINMUX_DATA(CPORT13_MARK, PORT14_FN1), + PINMUX_DATA(RFSPO4_MARK, PORT14_FN2), + PINMUX_DATA(CPORT14_MARK, PORT15_FN1), + PINMUX_DATA(RFSPO5_MARK, PORT15_FN2), + PINMUX_DATA(CPORT15_MARK, PORT16_FN1), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), + PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3), + PINMUX_DATA(CPORT16_MARK, PORT17_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), + PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3), + PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1), + PINMUX_DATA(SOUT2_MARK, PORT18_FN2), + PINMUX_DATA(CPORT18_MARK, PORT19_FN1), + PINMUX_DATA(XRTS2_MARK, PORT19_FN2), + PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), + PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1), + PINMUX_DATA(CPORT20_MARK, PORT21_FN1), + PINMUX_DATA(RFSPO6_MARK, PORT21_FN2), + PINMUX_DATA(CPORT21_MARK, PORT22_FN1), + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(CPORT22_MARK, PORT23_FN1), + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(CPORT23_MARK, PORT24_FN1), + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(RFSPO7_MARK, PORT24_FN3), + PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1), + PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1), + PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2), + PINMUX_DATA(XMAINPS_MARK, PORT27_FN1), + PINMUX_DATA(XDIVPS_MARK, PORT28_FN1), + PINMUX_DATA(XIDRST_MARK, PORT29_FN1), + PINMUX_DATA(IDCLK_MARK, PORT30_FN1), + PINMUX_DATA(IC_DP_MARK, PORT30_FN2), + PINMUX_DATA(IDIO_MARK, PORT31_FN1), + PINMUX_DATA(IC_DM_MARK, PORT31_FN2), + PINMUX_DATA(SOUT1_MARK, PORT32_FN1), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), + PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3), + PINMUX_DATA(SIN1_MARK, PORT33_FN1), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), + PINMUX_DATA(XWUP_MARK, PORT33_FN3), + PINMUX_DATA(XRTS1_MARK, PORT34_FN1), + PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2), + PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3), + PINMUX_DATA(XCTS1_MARK, PORT35_FN1), + PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2), + PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1), + PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1), + + /* 55-2 (FN) */ + PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1), + PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1), + PINMUX_DATA(VACK_MARK, PORT40_FN1), + PINMUX_DATA(XTALB1L_MARK, PORT41_FN1), + PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2), + PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), + PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2), + PINMUX_DATA(GPS_IM_MARK, PORT45_FN1), + PINMUX_DATA(GPS_IS_MARK, PORT46_FN1), + PINMUX_DATA(GPS_QM_MARK, PORT47_FN1), + PINMUX_DATA(GPS_QS_MARK, PORT48_FN1), + PINMUX_DATA(FMSOCK_MARK, PORT49_FN1), + PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2), + PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3), + PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1), + PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), + PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), + PINMUX_DATA(IPORT3_MARK, PORT50_FN4), + PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5), + PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1), + PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), + PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), + PINMUX_DATA(OPORT1_MARK, PORT51_FN4), + PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5), + PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1), + PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), + PINMUX_DATA(OPORT2_MARK, PORT52_FN3), + PINMUX_DATA(FMSOILR_MARK, PORT53_FN1), + PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2), + PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), + PINMUX_DATA(OPORT3_MARK, PORT53_FN4), + PINMUX_DATA(FMSIILR_MARK, PORT53_FN5), + PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1), + PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2), + PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), + PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4), + PINMUX_DATA(FMSISLD_MARK, PORT55_FN1), + PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2), + PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), + PINMUX_DATA(A0_EA0_MARK, PORT57_FN1), + PINMUX_DATA(BS_MARK, PORT57_FN2), + PINMUX_DATA(A12_EA12_MARK, PORT58_FN1), + PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2), + PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3), + PINMUX_DATA(A13_EA13_MARK, PORT59_FN1), + PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2), + PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3), + PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), + PINMUX_DATA(A14_EA14_MARK, PORT60_FN1), + PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2), + PINMUX_DATA(A15_EA15_MARK, PORT61_FN1), + PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2), + PINMUX_DATA(A16_EA16_MARK, PORT62_FN1), + PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3), + PINMUX_DATA(A17_EA17_MARK, PORT63_FN1), + PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3), + PINMUX_DATA(A18_EA18_MARK, PORT64_FN1), + PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3), + PINMUX_DATA(A19_EA19_MARK, PORT65_FN1), + PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3), + PINMUX_DATA(A20_EA20_MARK, PORT66_FN1), + PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3), + PINMUX_DATA(A21_EA21_MARK, PORT67_FN1), + PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3), + PINMUX_DATA(A22_EA22_MARK, PORT68_FN1), + PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3), + PINMUX_DATA(A23_EA23_MARK, PORT69_FN1), + PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3), + PINMUX_DATA(A24_EA24_MARK, PORT70_FN1), + PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3), + PINMUX_DATA(A25_EA25_MARK, PORT71_FN1), + PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3), + PINMUX_DATA(A26_MARK, PORT72_FN1), + PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2), + PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1), + PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1), + PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1), + PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1), + PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1), + PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1), + PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1), + PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1), + PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1), + PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1), + PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1), + PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1), + PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1), + PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1), + PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1), + PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1), + PINMUX_DATA(CS4_MARK, PORT90_FN1), + PINMUX_DATA(CS5A_MARK, PORT91_FN1), + PINMUX_DATA(FMSICK_MARK, PORT91_FN2), + PINMUX_DATA(CS5B_MARK, PORT92_FN1), + PINMUX_DATA(FCE1_MARK, PORT92_FN2), + + /* 55-3 (FN) */ + PINMUX_DATA(CS6B_MARK, PORT93_FN1), + PINMUX_DATA(XCS2_MARK, PORT93_FN2), + PINMUX_DATA(CS6A_MARK, PORT93_FN3), + PINMUX_DATA(DACK0_MARK, PORT93_FN4), + PINMUX_DATA(FCE0_MARK, PORT94_FN1), + PINMUX_DATA(WAIT_MARK, PORT95_FN1), + PINMUX_DATA(DREQ0_MARK, PORT95_FN2), + PINMUX_DATA(RD_XRD_MARK, PORT96_FN1), + PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1), + PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1), + PINMUX_DATA(FRB_MARK, PORT99_FN1), + PINMUX_DATA(CKO_MARK, PORT100_FN1), + PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1), + PINMUX_DATA(NBRST_MARK, PORT102_FN1), + PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1), + PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1), + PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1), + PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1), + PINMUX_DATA(TCKON_MARK, PORT118_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), + PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2), + PINMUX_DATA(IPORT0_MARK, PORT128_FN3), + PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), + PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2), + PINMUX_DATA(IPORT1_MARK, PORT129_FN3), + PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), + PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2), + PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3), + PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), + PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2), + PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), + PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), + PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2), + PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), + PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), + PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2), + PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3), + PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), + PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2), + PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3), + PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), + PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2), + PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3), + PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), + PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2), + PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), + PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2), + PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), + PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2), + PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3), + PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), + PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2), + PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3), + PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), + PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2), + PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3), + PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4), + PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), + PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2), + PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3), + PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4), + PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), + PINMUX_DATA(M13_BSW_MARK, PORT142_FN2), + PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3), + PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), + PINMUX_DATA(M14_GSW_MARK, PORT143_FN2), + PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3), + PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), + PINMUX_DATA(M15_RSW_MARK, PORT144_FN2), + PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3), + PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), + PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2), + PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3), + PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), + PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2), + PINMUX_DATA(IPORT2_MARK, PORT146_FN3), + PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), + PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2), + PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), + PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2), + PINMUX_DATA(A27_MARK, PORT149_FN1), + PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2), + PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), + PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2), + PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2), + PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1), + PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2), + PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3), + PINMUX_DATA(SOUT3_MARK, PORT154_FN1), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3), + PINMUX_DATA(SIN3_MARK, PORT155_FN1), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3), + PINMUX_DATA(XRTS3_MARK, PORT156_FN1), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2), + PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3), + PINMUX_DATA(XCTS3_MARK, PORT157_FN1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2), + PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3), + + /* 55-4 (FN) */ + PINMUX_DATA(DINT_MARK, PORT158_FN1), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2), + PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3), + PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1), + PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2), + PINMUX_DATA(NMI_MARK, PORT159_FN3), + PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1), + PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2), + PINMUX_DATA(SOUT0_MARK, PORT160_FN3), + PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1), + PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2), + PINMUX_DATA(XCTS0_MARK, PORT161_FN3), + PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4), + PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1), + PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2), + PINMUX_DATA(SIN0_MARK, PORT162_FN3), + PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4), + PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1), + PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2), + PINMUX_DATA(XRTS0_MARK, PORT163_FN3), + PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4), + PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), + PINMUX_DATA(LCDD0_MARK, PORT192_FN1), + PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2), + PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3), + PINMUX_DATA(LCDD1_MARK, PORT193_FN1), + PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2), + PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4), + PINMUX_DATA(LCDD2_MARK, PORT194_FN1), + PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2), + PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3), + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4), + PINMUX_DATA(LCDD3_MARK, PORT195_FN1), + PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2), + PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4), + PINMUX_DATA(LCDD4_MARK, PORT196_FN1), + PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2), + PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3), + PINMUX_DATA(LCDD5_MARK, PORT197_FN1), + PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2), + PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3), + PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4), + PINMUX_DATA(LCDD6_MARK, PORT198_FN1), + PINMUX_DATA(LCDD7_MARK, PORT199_FN1), + PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), + PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3), + PINMUX_DATA(LCDD8_MARK, PORT200_FN1), + PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2), + PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3), + PINMUX_DATA(D16_MARK, PORT200_FN4), + PINMUX_DATA(LCDD9_MARK, PORT201_FN1), + PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2), + PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3), + PINMUX_DATA(D17_MARK, PORT201_FN4), + PINMUX_DATA(LCDD10_MARK, PORT202_FN1), + PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2), + PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3), + PINMUX_DATA(D18_MARK, PORT202_FN4), + PINMUX_DATA(LCDD11_MARK, PORT203_FN1), + PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2), + PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3), + PINMUX_DATA(D19_MARK, PORT203_FN4), + PINMUX_DATA(LCDD12_MARK, PORT204_FN1), + PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2), + PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3), + PINMUX_DATA(D20_MARK, PORT204_FN4), + PINMUX_DATA(LCDD13_MARK, PORT205_FN1), + PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2), + PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3), + PINMUX_DATA(D21_MARK, PORT205_FN4), + PINMUX_DATA(LCDD14_MARK, PORT206_FN1), + PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2), + PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3), + PINMUX_DATA(D22_MARK, PORT206_FN4), + PINMUX_DATA(LCDD15_MARK, PORT207_FN1), + PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2), + PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3), + PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4), + PINMUX_DATA(D23_MARK, PORT207_FN5), + PINMUX_DATA(LCDD16_MARK, PORT208_FN1), + PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2), + PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3), + PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4), + PINMUX_DATA(D24_MARK, PORT208_FN5), + PINMUX_DATA(LCDD17_MARK, PORT209_FN1), + PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2), + PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3), + PINMUX_DATA(D25_MARK, PORT209_FN4), + PINMUX_DATA(LCDD18_MARK, PORT210_FN1), + PINMUX_DATA(DREQ2_MARK, PORT210_FN2), + PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3), + PINMUX_DATA(D26_MARK, PORT210_FN4), + PINMUX_DATA(LCDD19_MARK, PORT211_FN1), + PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2), + PINMUX_DATA(D27_MARK, PORT211_FN3), + PINMUX_DATA(LCDD20_MARK, PORT212_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3), + PINMUX_DATA(D28_MARK, PORT212_FN4), + PINMUX_DATA(LCDD21_MARK, PORT213_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3), + PINMUX_DATA(D29_MARK, PORT213_FN4), + PINMUX_DATA(LCDD22_MARK, PORT214_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3), + PINMUX_DATA(D30_MARK, PORT214_FN4), + PINMUX_DATA(LCDD23_MARK, PORT215_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3), + PINMUX_DATA(D31_MARK, PORT215_FN4), + PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), + PINMUX_DATA(LCDWR_MARK, PORT216_FN2), + PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3), + PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4), + PINMUX_DATA(LCDRD_MARK, PORT217_FN1), + PINMUX_DATA(DACK2_MARK, PORT217_FN2), + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3), + PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), + PINMUX_DATA(LCDCS_MARK, PORT218_FN2), + PINMUX_DATA(LCDCS2_MARK, PORT218_FN3), + PINMUX_DATA(DACK3_MARK, PORT218_FN4), + PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), + PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6), + PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), + PINMUX_DATA(LCDRS_MARK, PORT219_FN2), + PINMUX_DATA(DREQ3_MARK, PORT219_FN3), + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4), + PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), + PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), + PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3), + PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), + PINMUX_DATA(DREQ1_MARK, PORT221_FN2), + PINMUX_DATA(PWEN_MARK, PORT221_FN3), + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4), + PINMUX_DATA(LCDDON_MARK, PORT222_FN1), + PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), + PINMUX_DATA(DACK1_MARK, PORT222_FN3), + PINMUX_DATA(OVCN_MARK, PORT222_FN4), + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1), + PINMUX_DATA(OVCN2_MARK, PORT225_FN2), + PINMUX_DATA(EXTLP_MARK, PORT226_FN1), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), + PINMUX_DATA(USBTERM_MARK, PORT226_FN3), + PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1), + PINMUX_DATA(IDIN_MARK, PORT227_FN2), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1), + PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), + PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2), + PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), + PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2), + PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), + PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2), + PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), + PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2), + PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3), + PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), + PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2), + PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), + PINMUX_DATA(OPORT0_MARK, PORT235_FN2), + PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), + PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), + PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2), + PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), + PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2), + PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), + PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2), + + /* 55-5 (FN) */ + PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), + PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1), + PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), + PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), + PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), + PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1), + PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2), + PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1), + PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), + PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1), + PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), + PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3), + PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1), + PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), + PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3), + PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1), + PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), + PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3), + PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), + PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1), + PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), + PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3), + PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), + PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1), + PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), + PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3), + PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), + PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), + PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), + PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), + PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2), + PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), + PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2), + PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), + PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2), + PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), + PINMUX_DATA(TDI2_MARK, PORT254_FN2), + PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), + PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2), + PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), + PINMUX_DATA(TRST2_MARK, PORT256_FN2), + PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), + PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2), + PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), + PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2), + PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), + PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), + PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4), + PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), + PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2), + PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), + PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4), + PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), + PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2), + PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), + PINMUX_DATA(TDI3_MARK, PORT261_FN4), + PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), + PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2), + PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), + PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4), + PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), + PINMUX_DATA(TRST3_MARK, PORT263_FN2), + PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_265() _265(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + /* 55-1 -> 55-5 (GPIO) */ + GPIO_PORT_265(), + + /* Special Pull-up / Pull-down Functions */ + GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU), + GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU), + GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU), + GPIO_FN(PORT72_KEYIN6_PU), + + /* 55-1 (FN) */ + GPIO_FN(VBUS_0), + GPIO_FN(CPORT0), + GPIO_FN(CPORT1), + GPIO_FN(CPORT2), + GPIO_FN(CPORT3), + GPIO_FN(CPORT4), + GPIO_FN(CPORT5), + GPIO_FN(CPORT6), + GPIO_FN(CPORT7), + GPIO_FN(CPORT8), + GPIO_FN(CPORT9), + GPIO_FN(CPORT10), + GPIO_FN(CPORT11), GPIO_FN(SIN2), + GPIO_FN(CPORT12), GPIO_FN(XCTS2), + GPIO_FN(CPORT13), GPIO_FN(RFSPO4), + GPIO_FN(CPORT14), GPIO_FN(RFSPO5), + GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2), + GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3), + GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2), + GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2), + GPIO_FN(CPORT19_MPORT1), + GPIO_FN(CPORT20), GPIO_FN(RFSPO6), + GPIO_FN(CPORT21), GPIO_FN(STATUS0), + GPIO_FN(CPORT22), GPIO_FN(STATUS1), + GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7), + GPIO_FN(B_SYNLD1), + GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK), + GPIO_FN(XMAINPS), + GPIO_FN(XDIVPS), + GPIO_FN(XIDRST), + GPIO_FN(IDCLK), GPIO_FN(IC_DP), + GPIO_FN(IDIO), GPIO_FN(IC_DM), + GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT), + GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP), + GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK), + GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS), + GPIO_FN(PCMCLKO), + GPIO_FN(SYNC8KO), + + /* 55-2 (FN) */ + GPIO_FN(DNPCM_A), + GPIO_FN(UPPCM_A), + GPIO_FN(VACK), + GPIO_FN(XTALB1L), + GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS), + GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD), + GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS), + GPIO_FN(GPS_IM), + GPIO_FN(GPS_IS), + GPIO_FN(GPS_QM), + GPIO_FN(GPS_QS), + GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT), + GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2), + GPIO_FN(IPORT3), GPIO_FN(FMSIOLR), + GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3), + GPIO_FN(OPORT1), GPIO_FN(FMSIOBT), + GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2), + GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3), + GPIO_FN(OPORT3), GPIO_FN(FMSIILR), + GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2), + GPIO_FN(FMSIIBT), + GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0), + GPIO_FN(A0_EA0), GPIO_FN(BS), + GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2), + GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2), + GPIO_FN(TPU0TO1), + GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5), + GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4), + GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6), + GPIO_FN(D0_ED0_NAF0), + GPIO_FN(D1_ED1_NAF1), + GPIO_FN(D2_ED2_NAF2), + GPIO_FN(D3_ED3_NAF3), + GPIO_FN(D4_ED4_NAF4), + GPIO_FN(D5_ED5_NAF5), + GPIO_FN(D6_ED6_NAF6), + GPIO_FN(D7_ED7_NAF7), + GPIO_FN(D8_ED8_NAF8), + GPIO_FN(D9_ED9_NAF9), + GPIO_FN(D10_ED10_NAF10), + GPIO_FN(D11_ED11_NAF11), + GPIO_FN(D12_ED12_NAF12), + GPIO_FN(D13_ED13_NAF13), + GPIO_FN(D14_ED14_NAF14), + GPIO_FN(D15_ED15_NAF15), + GPIO_FN(CS4), + GPIO_FN(CS5A), GPIO_FN(FMSICK), + + /* 55-3 (FN) */ + GPIO_FN(CS5B), GPIO_FN(FCE1), + GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0), + GPIO_FN(FCE0), + GPIO_FN(WAIT), GPIO_FN(DREQ0), + GPIO_FN(RD_XRD), + GPIO_FN(WE0_XWR0_FWE), + GPIO_FN(WE1_XWR1), + GPIO_FN(FRB), + GPIO_FN(CKO), + GPIO_FN(NBRSTOUT), + GPIO_FN(NBRST), + GPIO_FN(GPS_EPPSIN), + GPIO_FN(LATCHPULSE), + GPIO_FN(LTESIGNAL), + GPIO_FN(LEGACYSTATE), + GPIO_FN(TCKON), + GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0), + GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1), + GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD), + GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1), + GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2), + GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5), + GPIO_FN(PORT133_MSIOF2_TSYNC), + GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD), + GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK), + GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2), + GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3), + GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC), + GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR), + GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2), + GPIO_FN(PORT140_FSIAOBT), + GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3), + GPIO_FN(PORT141_FSIAOSLD), + GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK), + GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR), + GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT), + GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD), + GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2), + GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5), + GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6), + GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1), + GPIO_FN(MFG0_IN2), + GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK), + GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1), + GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1), + GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2), + GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD), + + /* 55-4 (FN) */ + GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3), + GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI), + GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0), + GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0), + GPIO_FN(MFG3_IN2), + GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0), + GPIO_FN(MFG3_IN1), + GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0), + GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0), + GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI), + GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS), + GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS), + GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD), + GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD), + GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK), + GPIO_FN(MFG2_OUT2), + GPIO_FN(LCDD6), + GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2), + GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0), + GPIO_FN(D16), + GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1), + GPIO_FN(D17), + GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2), + GPIO_FN(D18), + GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3), + GPIO_FN(D19), + GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4), + GPIO_FN(D20), + GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5), + GPIO_FN(D21), + GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6), + GPIO_FN(D22), + GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0), + GPIO_FN(VIO_DR7), GPIO_FN(D23), + GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1), + GPIO_FN(VIO_VDR), GPIO_FN(D24), + GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR), + GPIO_FN(D25), + GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1), + GPIO_FN(D26), + GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27), + GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0), + GPIO_FN(D28), + GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1), + GPIO_FN(D29), + GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK), + GPIO_FN(D30), + GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC), + GPIO_FN(D31), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3), + GPIO_FN(VIO_CLKR), + GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC), + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3), + GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK), + GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5), + GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD), + GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN), + GPIO_FN(MSIOF0L_TXD), + GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2), + GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM), + GPIO_FN(PORT226_VIO_CKO2), + GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN), + GPIO_FN(SCIFA1_RXD), + GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1), + GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC), + GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR), + GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT), + GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG), + GPIO_FN(PORT233_FSIACK), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD), + GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2), + GPIO_FN(PORT235_FSIAILR), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT), + GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD), + GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3), + + /* 55-5 (FN) */ + GPIO_FN(MSIOF1_SS2), + GPIO_FN(SCIFA6_TXD), + GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1), + GPIO_FN(TPU4TO0), + GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2), + GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2), + GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1), + GPIO_FN(PORT244_SCIFB_CTS), + GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2), + GPIO_FN(PORT245_SCIFB_RTS), + GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1), + GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0), + GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2), + GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1), + GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1), + GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0), + GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1), + GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0), + GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0), + GPIO_FN(SDHID0_2), GPIO_FN(TDI2), + GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0), + GPIO_FN(SDHICMD0), GPIO_FN(TRST2), + GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2), + GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1), + GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2), + GPIO_FN(TMS3_SWDIO_MC1), + GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2), + GPIO_FN(TDO3_SWO0_MC1), + GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2), + GPIO_FN(TDI3), + GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2), + GPIO_FN(RTCK3_SWO1_MC1), + GPIO_FN(SDHICMD1), GPIO_FN(TRST3), + GPIO_FN(RESETOUTS), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + PORTCR(84, 0xe6050054), /* PORT84CR */ + PORTCR(85, 0xe6050055), /* PORT85CR */ + PORTCR(86, 0xe6050056), /* PORT86CR */ + PORTCR(87, 0xe6050057), /* PORT87CR */ + PORTCR(88, 0xe6050058), /* PORT88CR */ + PORTCR(89, 0xe6050059), /* PORT89CR */ + + PORTCR(90, 0xe605005a), /* PORT90CR */ + PORTCR(91, 0xe605005b), /* PORT91CR */ + PORTCR(92, 0xe605005c), /* PORT92CR */ + PORTCR(93, 0xe605005d), /* PORT93CR */ + PORTCR(94, 0xe605005e), /* PORT94CR */ + PORTCR(95, 0xe605005f), /* PORT95CR */ + PORTCR(96, 0xe6050060), /* PORT96CR */ + PORTCR(97, 0xe6050061), /* PORT97CR */ + PORTCR(98, 0xe6050062), /* PORT98CR */ + PORTCR(99, 0xe6050063), /* PORT99CR */ + + PORTCR(100, 0xe6050064), /* PORT100CR */ + PORTCR(101, 0xe6050065), /* PORT101CR */ + PORTCR(102, 0xe6050066), /* PORT102CR */ + PORTCR(103, 0xe6050067), /* PORT103CR */ + PORTCR(104, 0xe6050068), /* PORT104CR */ + PORTCR(105, 0xe6050069), /* PORT105CR */ + PORTCR(106, 0xe605006a), /* PORT106CR */ + PORTCR(107, 0xe605006b), /* PORT107CR */ + PORTCR(108, 0xe605006c), /* PORT108CR */ + PORTCR(109, 0xe605006d), /* PORT109CR */ + + PORTCR(110, 0xe605006e), /* PORT110CR */ + PORTCR(111, 0xe605006f), /* PORT111CR */ + PORTCR(112, 0xe6050070), /* PORT112CR */ + PORTCR(113, 0xe6050071), /* PORT113CR */ + PORTCR(114, 0xe6050072), /* PORT114CR */ + PORTCR(115, 0xe6050073), /* PORT115CR */ + PORTCR(116, 0xe6050074), /* PORT116CR */ + PORTCR(117, 0xe6050075), /* PORT117CR */ + PORTCR(118, 0xe6050076), /* PORT118CR */ + + PORTCR(128, 0xe6051080), /* PORT128CR */ + PORTCR(129, 0xe6051081), /* PORT129CR */ + + PORTCR(130, 0xe6051082), /* PORT130CR */ + PORTCR(131, 0xe6051083), /* PORT131CR */ + PORTCR(132, 0xe6051084), /* PORT132CR */ + PORTCR(133, 0xe6051085), /* PORT133CR */ + PORTCR(134, 0xe6051086), /* PORT134CR */ + PORTCR(135, 0xe6051087), /* PORT135CR */ + PORTCR(136, 0xe6051088), /* PORT136CR */ + PORTCR(137, 0xe6051089), /* PORT137CR */ + PORTCR(138, 0xe605108a), /* PORT138CR */ + PORTCR(139, 0xe605108b), /* PORT139CR */ + + PORTCR(140, 0xe605108c), /* PORT140CR */ + PORTCR(141, 0xe605108d), /* PORT141CR */ + PORTCR(142, 0xe605108e), /* PORT142CR */ + PORTCR(143, 0xe605108f), /* PORT143CR */ + PORTCR(144, 0xe6051090), /* PORT144CR */ + PORTCR(145, 0xe6051091), /* PORT145CR */ + PORTCR(146, 0xe6051092), /* PORT146CR */ + PORTCR(147, 0xe6051093), /* PORT147CR */ + PORTCR(148, 0xe6051094), /* PORT148CR */ + PORTCR(149, 0xe6051095), /* PORT149CR */ + + PORTCR(150, 0xe6051096), /* PORT150CR */ + PORTCR(151, 0xe6051097), /* PORT151CR */ + PORTCR(152, 0xe6051098), /* PORT152CR */ + PORTCR(153, 0xe6051099), /* PORT153CR */ + PORTCR(154, 0xe605109a), /* PORT154CR */ + PORTCR(155, 0xe605109b), /* PORT155CR */ + PORTCR(156, 0xe605109c), /* PORT156CR */ + PORTCR(157, 0xe605109d), /* PORT157CR */ + PORTCR(158, 0xe605109e), /* PORT158CR */ + PORTCR(159, 0xe605109f), /* PORT159CR */ + + PORTCR(160, 0xe60510a0), /* PORT160CR */ + PORTCR(161, 0xe60510a1), /* PORT161CR */ + PORTCR(162, 0xe60510a2), /* PORT162CR */ + PORTCR(163, 0xe60510a3), /* PORT163CR */ + PORTCR(164, 0xe60510a4), /* PORT164CR */ + + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60520e0), /* PORT224CR */ + PORTCR(225, 0xe60520e1), /* PORT225CR */ + PORTCR(226, 0xe60520e2), /* PORT226CR */ + PORTCR(227, 0xe60520e3), /* PORT227CR */ + PORTCR(228, 0xe60520e4), /* PORT228CR */ + PORTCR(229, 0xe60520e5), /* PORT229CR */ + + PORTCR(230, 0xe60520e6), /* PORT230CR */ + PORTCR(231, 0xe60520e7), /* PORT231CR */ + PORTCR(232, 0xe60520e8), /* PORT232CR */ + PORTCR(233, 0xe60520e9), /* PORT233CR */ + PORTCR(234, 0xe60520ea), /* PORT234CR */ + PORTCR(235, 0xe60520eb), /* PORT235CR */ + PORTCR(236, 0xe60520ec), /* PORT236CR */ + PORTCR(237, 0xe60520ed), /* PORT237CR */ + PORTCR(238, 0xe60520ee), /* PORT238CR */ + PORTCR(239, 0xe60520ef), /* PORT239CR */ + + PORTCR(240, 0xe60520f0), /* PORT240CR */ + PORTCR(241, 0xe60520f1), /* PORT241CR */ + PORTCR(242, 0xe60520f2), /* PORT242CR */ + PORTCR(243, 0xe60520f3), /* PORT243CR */ + PORTCR(244, 0xe60520f4), /* PORT244CR */ + PORTCR(245, 0xe60520f5), /* PORT245CR */ + PORTCR(246, 0xe60520f6), /* PORT246CR */ + PORTCR(247, 0xe60520f7), /* PORT247CR */ + PORTCR(248, 0xe60520f8), /* PORT248CR */ + PORTCR(249, 0xe60520f9), /* PORT249CR */ + + PORTCR(250, 0xe60520fa), /* PORT250CR */ + PORTCR(251, 0xe60520fb), /* PORT251CR */ + PORTCR(252, 0xe60520fc), /* PORT252CR */ + PORTCR(253, 0xe60520fd), /* PORT253CR */ + PORTCR(254, 0xe60520fe), /* PORT254CR */ + PORTCR(255, 0xe60520ff), /* PORT255CR */ + PORTCR(256, 0xe6052100), /* PORT256CR */ + PORTCR(257, 0xe6052101), /* PORT257CR */ + PORTCR(258, 0xe6052102), /* PORT258CR */ + PORTCR(259, 0xe6052103), /* PORT259CR */ + + PORTCR(260, 0xe6052104), /* PORT260CR */ + PORTCR(261, 0xe6052105), /* PORT261CR */ + PORTCR(262, 0xe6052106), /* PORT262CR */ + PORTCR(263, 0xe6052107), /* PORT263CR */ + PORTCR(264, 0xe6052108), /* PORT264CR */ + + { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MSELBCR_MSEL17_0, MSELBCR_MSEL17_1, + 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { }, +}; + +static struct pinmux_info sh7377_pinmux_info = { + .name = "sh7377_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_RESETOUTS, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7377_pinmux_init(void) +{ + register_pinmux(&sh7377_pinmux_info); +} From aa18ef609b65a76e4531b09dd0c196be3e04eb94 Mon Sep 17 00:00:00 2001 From: NISHIMOTO Hiroki Date: Fri, 12 Feb 2010 08:11:18 +0000 Subject: [PATCH 18/27] ARM: mach-shmobile: G4EVM USBHS support Add G4EVM platform data and a magic setup sequence to initialize the r8a66597 block aka USBHS in sh7377. Signed-off-by: NISHIMOTO Hiroki Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-g4evm.c | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index ef4b0f59af49..5acd623f93e7 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -86,9 +87,50 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* USBHS */ +void usb_host_port_power(int port, int power) +{ + if (!power) /* only power-on supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ + __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); +} + +static struct r8a66597_platdata usb_host_data = { + .on_chip = 1, + .port_power = usb_host_port_power, +}; + +static struct resource usb_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xe6890000, + .end = 0xe68900e5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .platform_data = &usb_host_data, + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; static struct platform_device *g4evm_devices[] __initdata = { &nor_flash_device, + &usb_host_device, }; static struct map_desc g4evm_io_desc[] __initdata = { @@ -137,6 +179,23 @@ static void __init g4evm_init(void) gpio_direction_output(GPIO_PORT113, 1); gpio_export(GPIO_PORT113, 1); + /* USBHS */ + gpio_request(GPIO_FN_VBUS_0, NULL); + gpio_request(GPIO_FN_PWEN, NULL); + gpio_request(GPIO_FN_OVCN, NULL); + gpio_request(GPIO_FN_OVCN2, NULL); + gpio_request(GPIO_FN_EXTLP, NULL); + gpio_request(GPIO_FN_IDIN, NULL); + + /* enable clock in SMSTPCR3 */ + __raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c); + + /* setup USB phy */ + __raw_writew(0x0200, 0xe605810a); /* USBCR1 */ + __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ + __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ + __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + sh7377_add_standard_devices(); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); From deded43508f065c95af506d18b8309ba842c397e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 12 Feb 2010 09:55:08 +0000 Subject: [PATCH 19/27] ARM: mach-shmobile: intc-sh7372 tidyup This patch is based on Rev 0.5 manual Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/intc-sh7372.c | 90 ++++++++++++++-------------- 1 file changed, 46 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index c6e747f92462..c57a923f97a6 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -39,8 +39,7 @@ enum { AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, MFI_MFIM, MFI_MFIS, BBIF1, BBIF2, - USBHSDMAC_USHDMI, - USBHS_USHI0, USBHS_USHI1, + USBHSDMAC0_USHDMI, _3DG_SGX540, CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, KEYSC_KEY, @@ -57,8 +56,8 @@ enum { DDM, SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, RWDT0, - DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, - DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, @@ -69,7 +68,7 @@ enum { FSI, FMSI, MIPI_HSI, IPMMU_IPMMUD, - CEC_CEC_1, CEC_CEC_2, + CEC_1, CEC_2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, MFIS2, CPORTR2S, @@ -79,14 +78,14 @@ enum { IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0, - USHSDMI, + USBHSDMAC1_USHDMI, /* interrupt groups INTCA */ - DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, - AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 + DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, + AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 }; -static struct intc_vect intca_vectors[] = { +static struct intc_vect intca_vectors[] __initdata = { INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), @@ -111,8 +110,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(AP_ARM_COMMRX, 0x0860), INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), - INTC_VECT(USBHSDMAC_USHDMI, 0x0a00), - INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), + INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00), INTC_VECT(_3DG_SGX540, 0x0a60), INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), @@ -137,10 +135,10 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), INTC_VECT(RWDT0, 0x1280), - INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), - INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), - INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), - INTC_VECT(DMAC_2_DADERR, 0x20c0), + INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), + INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), + INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0), + INTC_VECT(DMAC1_2_DADERR, 0x20c0), INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), @@ -149,7 +147,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), INTC_VECT(DMAC3_2_DADERR, 0x22c0), - INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), + INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320), INTC_VECT(SHWYSTAT_COM, 0x1340), INTC_VECT(HDMI, 0x17e0), INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), @@ -157,7 +155,7 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(FMSI, 0x1860), INTC_VECT(MIPI_HSI, 0x18e0), INTC_VECT(IPMMU_IPMMUD, 0x1920), - INTC_VECT(CEC_CEC_1, 0x1940), INTC_VECT(CEC_CEC_2, 0x1960), + INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960), INTC_VECT(AP_ARM_CTIIRQ, 0x1980), INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), @@ -172,14 +170,14 @@ static struct intc_vect intca_vectors[] = { INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), - INTC_VECT(USHSDMI, 0x1d00), + INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00), }; static struct intc_group intca_groups[] __initdata = { - INTC_GROUP(DMAC_1, DMAC_1_DEI0, - DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), - INTC_GROUP(DMAC_2, DMAC_2_DEI4, - DMAC_2_DEI5, DMAC_2_DADERR), + INTC_GROUP(DMAC1_1, DMAC1_1_DEI0, + DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), + INTC_GROUP(DMAC1_2, DMAC1_2_DEI4, + DMAC1_2_DEI5, DMAC1_2_DADERR), INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, @@ -188,8 +186,9 @@ static struct intc_group intca_groups[] __initdata = { DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), - INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), - INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), + INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX), + INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, + AP_ARM_DMAIRQ, AP_ARM_DMASIRQ), INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), @@ -203,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = { INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), }; -static struct intc_mask_reg intca_mask_registers[] = { +static struct intc_mask_reg intca_mask_registers[] __initdata = { { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ @@ -218,7 +217,7 @@ static struct intc_mask_reg intca_mask_registers[] = { AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ { 0, CRYPT_STD, DIRC, 0, - DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, + DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ { 0, 0, 0, 0, BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, @@ -229,7 +228,7 @@ static struct intc_mask_reg intca_mask_registers[] = { { DDM, 0, 0, 0, 0, 0, 0, 0 } }, { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, + { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ { SCIFB, SCIFA5, SCIFA4, MSIOF1, @@ -239,7 +238,7 @@ static struct intc_mask_reg intca_mask_registers[] = { FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, - TTI20, USBHSDMAC_USHDMI, 0, 0 } }, + TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, CMT2, 0, 0, _3DG_SGX540 } }, @@ -265,7 +264,7 @@ static struct intc_mask_reg intca_mask_registers[] = { { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, 0, 0, 0, MIPI_HSI } }, { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ - { 0, IPMMU_IPMMUD, CEC_CEC_1, CEC_CEC_2, + { 0, IPMMU_IPMMUD, CEC_1, CEC_2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ @@ -278,16 +277,16 @@ static struct intc_mask_reg intca_mask_registers[] = { { 0, 0, 0, 0, USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ - { USBHSDMAC_USHDMI, 0, 0, 0, + { USBHSDMAC1_USHDMI, 0, 0, 0, 0, 0, 0, 0 } }, }; -static struct intc_prio_reg intca_prio_registers[] = { +static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6900010, 0, 32, 4, /* INTPRI00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900014, 0, 32, 4, /* INTPRI10A */ { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900018, 0, 32, 4, /* INTPRI10A */ + { 0xe6900018, 0, 32, 4, /* INTPRI20A */ { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, { 0xe690001c, 0, 32, 4, /* INTPRI30A */ { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, @@ -298,16 +297,18 @@ static struct intc_prio_reg intca_prio_registers[] = { CMT1_CMT11, AP_ARM1 } }, { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_CMT12, 0 } }, - { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS, MFI_MFIM, 0 } }, - { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2, _3DG_SGX540, CMT1_CMT10 } }, { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, SCIFA2, SCIFA3 } }, - { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC_USHDMI, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI, FLCTL, SDHI0 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, - { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, 0, TTI20 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, + 0/* MSU */, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, + 0/* MSUG */, TTI20 } }, { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, @@ -318,7 +319,7 @@ static struct intc_prio_reg intca_prio_registers[] = { { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, - CEC_CEC_1, CEC_CEC_2 } }, + CEC_1, CEC_2 } }, { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, CMT14, CMT15 } }, @@ -328,20 +329,21 @@ static struct intc_prio_reg intca_prio_registers[] = { IIC4_WAITI4, IIC4_DTEI4 } }, { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, - { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0, 0, 0, 0 } }, + { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, + 0/*TXI*/, 0/*TEI*/} }, { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, - { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC_USHDMI, 0, 0, 0 } }, + { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, }; static struct intc_sense_reg intca_sense_registers[] __initdata = { - { 0xe6900000, 16, 2, /* ICR1A */ + { 0xe6900000, 32, 4, /* ICR1A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, - { 0xe6900004, 16, 2, /* ICR2A */ + { 0xe6900004, 32, 4, /* ICR2A */ { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, - { 0xe6900008, 16, 2, /* ICR3A */ + { 0xe6900008, 32, 4, /* ICR3A */ { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, - { 0xe690000c, 16, 2, /* ICR4A */ + { 0xe690000c, 32, 4, /* ICR4A */ { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, }; From b789b3fdccc1690826331f4c878b644c3904ca6b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 17 Feb 2010 09:39:10 +0000 Subject: [PATCH 20/27] ARM: mach-shmobile: Add sh7372 pinmux support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/include/mach/sh7372.h | 434 +++++ arch/arm/mach-shmobile/pfc-sh7372.c | 1637 ++++++++++++++++++ 5 files changed, 2074 insertions(+) create mode 100644 arch/arm/mach-shmobile/include/mach/sh7372.h create mode 100644 arch/arm/mach-shmobile/pfc-sh7372.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a96c25a26272..aeceb9b92aeb 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -41,6 +41,7 @@ config MACH_G4EVM config MACH_AP4EVB bool "AP4EVB board" depends on ARCH_SH7372 + select ARCH_REQUIRE_GPIOLIB comment "SH-Mobile System Configuration" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index ce01951edda3..6d385d371c33 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o # Pinmux setup pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o +pfc-$(CONFIG_ARCH_SH7372) := pfc-sh7372.o obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) # Board objects diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d6f927b4bef6..57903605cc51 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -18,5 +18,6 @@ extern void sh7377_pinmux_init(void); extern void sh7372_init_irq(void); extern void sh7372_add_early_devices(void); extern void sh7372_add_standard_devices(void); +extern void sh7372_pinmux_init(void); #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h new file mode 100644 index 000000000000..dc34f00c56b8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2010 Renesas Solutions Corp. + * + * Kuninori Morimoto + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_SH7372_H__ +#define __ASM_SH7372_H__ + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, + + /* IRQ */ + GPIO_FN_IRQ0_6, /* PORT 6 */ + GPIO_FN_IRQ0_162, /* PORT 162 */ + GPIO_FN_IRQ1, /* PORT 12 */ + GPIO_FN_IRQ2_4, /* PORT 4 */ + GPIO_FN_IRQ2_5, /* PORT 5 */ + GPIO_FN_IRQ3_8, /* PORT 8 */ + GPIO_FN_IRQ3_16, /* PORT 16 */ + GPIO_FN_IRQ4_17, /* PORT 17 */ + GPIO_FN_IRQ4_163, /* PORT 163 */ + GPIO_FN_IRQ5, /* PORT 18 */ + GPIO_FN_IRQ6_39, /* PORT 39 */ + GPIO_FN_IRQ6_164, /* PORT 164 */ + GPIO_FN_IRQ7_40, /* PORT 40 */ + GPIO_FN_IRQ7_167, /* PORT 167 */ + GPIO_FN_IRQ8_41, /* PORT 41 */ + GPIO_FN_IRQ8_168, /* PORT 168 */ + GPIO_FN_IRQ9_42, /* PORT 42 */ + GPIO_FN_IRQ9_169, /* PORT 169 */ + GPIO_FN_IRQ10, /* PORT 65 */ + GPIO_FN_IRQ11, /* PORT 67 */ + GPIO_FN_IRQ12_80, /* PORT 80 */ + GPIO_FN_IRQ12_137, /* PORT 137 */ + GPIO_FN_IRQ13_81, /* PORT 81 */ + GPIO_FN_IRQ13_145, /* PORT 145 */ + GPIO_FN_IRQ14_82, /* PORT 82 */ + GPIO_FN_IRQ14_146, /* PORT 146 */ + GPIO_FN_IRQ15_83, /* PORT 83 */ + GPIO_FN_IRQ15_147, /* PORT 147 */ + GPIO_FN_IRQ16_84, /* PORT 84 */ + GPIO_FN_IRQ16_170, /* PORT 170 */ + GPIO_FN_IRQ17, /* PORT 85 */ + GPIO_FN_IRQ18, /* PORT 86 */ + GPIO_FN_IRQ19, /* PORT 87 */ + GPIO_FN_IRQ20, /* PORT 92 */ + GPIO_FN_IRQ21, /* PORT 93 */ + GPIO_FN_IRQ22, /* PORT 94 */ + GPIO_FN_IRQ23, /* PORT 95 */ + GPIO_FN_IRQ24, /* PORT 112 */ + GPIO_FN_IRQ25, /* PORT 119 */ + GPIO_FN_IRQ26_121, /* PORT 121 */ + GPIO_FN_IRQ26_172, /* PORT 172 */ + GPIO_FN_IRQ27_122, /* PORT 122 */ + GPIO_FN_IRQ27_180, /* PORT 180 */ + GPIO_FN_IRQ28_123, /* PORT 123 */ + GPIO_FN_IRQ28_181, /* PORT 181 */ + GPIO_FN_IRQ29_129, /* PORT 129 */ + GPIO_FN_IRQ29_182, /* PORT 182 */ + GPIO_FN_IRQ30_130, /* PORT 130 */ + GPIO_FN_IRQ30_183, /* PORT 183 */ + GPIO_FN_IRQ31_138, /* PORT 138 */ + GPIO_FN_IRQ31_184, /* PORT 184 */ + + /* + * MSIOF0 (PORT 36, 37, 38, 39 + * 40, 41, 42, 43, 44, 45) + */ + GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD, + + /* + * MSIOF1 (PORT 39, 40, 41, 42, 43, 44 + * 84, 85, 86, 87, 88, 89, 90, 91, 92, 93) + */ + GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40, + GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89, + GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42, + GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91, + GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44, + GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + /* + * MSIOF2 (PORT 134, 135, 136, 137, 138, 139 + * 148, 149, 150, 151) + */ + GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2, + GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD, + + /* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD, + GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N, + + /* MSIOF4 (PORT 0, 1, 2, 3) */ + GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD, + + /* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */ + GPIO_FN_FSIACK, GPIO_FN_FSIBCK, + GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11, + GPIO_FN_FSIASPDIF_15, + + /* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */ + GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR, + GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT, + GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOILR, GPIO_FN_FMSIILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT, + GPIO_FN_FMSISLD, GPIO_FN_FMSICK, + + /* SCIFA0 (PORT 152, 153, 156, 157, 158) */ + GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS, + GPIO_FN_SCIFA0_CTS, + + /* SCIFA1 (PORT 154, 155, 159, 160, 161) */ + GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS, + GPIO_FN_SCIFA1_CTS, + + /* SCIFA2 (PORT 94, 95, 96, 97, 98) */ + GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1, + GPIO_FN_SCIFA2_SCK1, + + /* SCIFA3 (PORT 43, 44, + 140, 141, 142, 143, 144) */ + GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140, + GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141, + GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD, + GPIO_FN_SCIFA3_RXD, + + /* SCIFA4 (PORT 5, 6) */ + GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD, + + /* SCIFA5 (PORT 8, 12) */ + GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD, + + /* SCIFB (PORT 162, 163, 164, 165, 166) */ + GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS, + GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD, + GPIO_FN_SCIFB_RXD, + + /* + * CEU (PORT 16, 17, + * 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, + * 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, + * 120) + */ + GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, + GPIO_FN_VIO_CKO, + GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, + GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, + GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, + GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, + GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, + GPIO_FN_VIO_D15, + + /* USB0 (PORT 113, 114, 115, 116, 117, 167) */ + GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0, + GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0, + GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0, + + /* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */ + GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113, + GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138, + GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162, + GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1, + GPIO_FN_VBUS0_1, + + /* GPIO (PORT 41, 42, 43, 44) */ + GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1, + + /* + * BSC (PORT 19, + * 20, 21, 22, 25, 26, 27, 28, 29, + * 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, + * 40, 41, 42, 43, 44, 45, + * 62, 63, 64, 65, 66, 67, + * 71, 72, 74, 75) + */ + GPIO_FN_BS, GPIO_FN_WE1, + GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR, + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A, + + /* + * BSC/FLCTL (PORT 23, 24, + * 46, 47, 48, 49, + * 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, + * 60, 61, 69, 70) + */ + GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE, + GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE, + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + + /* + * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89, + * 90, 91, 92, 99) + */ + GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5, + GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7, + GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0, + + /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */ + GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2, + GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5, + GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7, + GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1, + + /* SPU2 (PORT 65) */ + GPIO_FN_VINT_I, + + /* FLCTL (PORT 66, 68, 73) */ + GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB, + + /* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ + GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY, + GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA, + GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE, + + /* + * MFI (PORT 76, 77, 78, 79, + * 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, + * 90, 91, 92, 93, 94, 95, 96, 97, 98, 99) + */ + GPIO_FN_MFIv6, /* see MSEL4CR 6 */ + GPIO_FN_MFIv4, /* see MSEL4CR 6 */ + + GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0, + GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0, + GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT, + + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, + + /* SIM (PORT 94, 95, 98) */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D, + + /* TPU (PORT 93, 99, 112, 160, 161) */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99, + GPIO_FN_TPU0TO3, + + /* I2C2 (PORT 110, 111) */ + GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2, + + /* I2C3(1) (PORT 114, 115) */ + GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3, + + /* I2C3(2) (PORT 137, 145) */ + GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S, + + /* I2C4(2) (PORT 116, 117) */ + GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4, + + /* I2C4(2) (PORT 146, 147) */ + GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S, + + /* + * KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, + * 130, 131, 132, 133, 134, 135, 136) + */ + GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136, + GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135, + GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134, + GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133, + GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4, + GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6, + GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7, + + /* + * LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, + * 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, + * 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, + * 150, 151) + */ + GPIO_FN_LCDC0_SELECT, /* LCDC 0 */ + GPIO_FN_LCDC1_SELECT, /* LCDC 1 */ + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK, + GPIO_FN_LCDDON, + + GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3, + GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7, + GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11, + GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15, + GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19, + GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23, + + /* IRDA (PORT 139, 140, 141, 142) */ + GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, + GPIO_FN_IROUT_139, GPIO_FN_IROUT_140, + + /* TSIF1 (PORT 156, 157, 158, 159) */ + GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */ + GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */ + GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */ + GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */ + + GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1, + GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1, + + /* TSIF2 (PORT 137, 145, 146, 147) */ + GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2, + GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2, + + /* HDMI (PORT 169, 170) */ + GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, + + /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */ + GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, + GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0, + GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3, + + /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */ + GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0, + GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3, + + /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */ + GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0, + GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3, + + /* SDENC see MSEL4CR 19 */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, +}; + +#endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c new file mode 100644 index 000000000000..9557d0964d73 --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh7372.c @@ -0,0 +1,1637 @@ +/* + * sh7372 processor support - PFC hardware block + * + * Copyright (C) 2010 Kuninori Morimoto + * + * Based on + * sh7367 processor support - PFC hardware block + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include + +#define _1(fn, pfx, sfx) fn(pfx, sfx) + +#define _10(fn, pfx, sfx) \ + _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ + _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ + _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ + _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ + _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) + +#define _80(fn, pfx, sfx) \ + _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ + _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ + _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ + _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx) + +#define _190(fn, pfx, sfx) \ + _10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \ + _10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx) + +#define _PORT(pfx, sfx) pfx##_##sfx +#define PORT_ALL(str) _190(_PORT, PORT, str) + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT190_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT190_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_IN_PU -> PORT190_IN_PU */ + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), + PINMUX_INPUT_PULLUP_END, + + /* PORT0_IN_PD -> PORT190_IN_PD */ + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), + PINMUX_INPUT_PULLDOWN_END, + + /* PORT0_OUT -> PORT190_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_8_0, MSEL1CR_8_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + MSEL1CR_0_0, MSEL1CR_0_1, + + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_15_0, MSEL3CR_15_1, + MSEL3CR_9_0, MSEL3CR_9_1, + MSEL3CR_6_0, MSEL3CR_6_1, + + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_6_0, MSEL4CR_6_1, + MSEL4CR_4_0, MSEL4CR_4_1, + MSEL4CR_1_0, MSEL4CR_1_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* IRQ */ + IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK, + IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK, + IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK, + IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK, + IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK, + IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK, + IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK, + IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK, + IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK, + IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK, + IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK, + IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK, + IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK, + + /* MSIOF0 */ + MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK, + MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK, + MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, + MSIOF0_TXD_MARK, + + /* MSIOF1 */ + MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK, + MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK, + MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK, + MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK, + MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK, + MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK, + MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + + /* MSIOF2 */ + MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK, + MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK, + MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, + MSIOF2_TXD_MARK, + + /* MSIOF3 */ + BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, + BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, + BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, + + /* MSIOF4 */ + BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, + BBIF2_TXD1_MARK, BBIF2_RXD_MARK, + + /* FSI */ + FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK, + FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK, + FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK, + + /* FMSI */ + FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK, + FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK, + FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK, + + /* SCIFA0 */ + SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK, + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, + + /* SCIFA1 */ + SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK, + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, + + /* SCIFA2 */ + SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK, + SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK, + + /* SCIFA3 */ + SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK, + SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK, + SCIFA3_RXD_MARK, + + /* SCIFA4 */ + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, + + /* SCIFA5 */ + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, + + /* SCIFB */ + SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK, + SCIFB_TXD_MARK, SCIFB_RXD_MARK, + + /* CEU */ + VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK, + VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK, + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, + VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, + VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, + + /* USB0 */ + IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK, + OVCN_0_MARK, VBUS0_0_MARK, + + /* USB1 */ + IDIN_1_18_MARK, IDIN_1_113_MARK, + PWEN_1_115_MARK, PWEN_1_138_MARK, + OVCN_1_114_MARK, OVCN_1_162_MARK, + EXTLP_1_MARK, OVCN2_1_MARK, + VBUS0_1_MARK, + + /* GPIO */ + GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK, + + /* BSC */ + BS_MARK, WE1_MARK, + CKO_MARK, WAIT_MARK, RDWR_MARK, + + A0_MARK, A1_MARK, A2_MARK, A3_MARK, + A6_MARK, A7_MARK, A8_MARK, A9_MARK, + A10_MARK, A11_MARK, A12_MARK, A13_MARK, + A14_MARK, A15_MARK, A16_MARK, A17_MARK, + A18_MARK, A19_MARK, A20_MARK, A21_MARK, + A22_MARK, A23_MARK, A24_MARK, A25_MARK, + A26_MARK, + + CS0_MARK, CS2_MARK, CS4_MARK, + CS5A_MARK, CS5B_MARK, CS6A_MARK, + + /* BSC/FLCTL */ + RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK, + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, + + /* MMCIF(1) */ + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, + MMCCMD0_MARK, MMCCLK0_MARK, + + /* MMCIF(2) */ + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, + MMCCLK1_MARK, MMCCMD1_MARK, + + /* SPU2 */ + VINT_I_MARK, + + /* FLCTL */ + FCE1_MARK, FCE0_MARK, FRB_MARK, + + /* HSI */ + GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK, + GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK, + MP_RX_READY_MARK, MP_TX_WAKE_MARK, + + /* MFI */ + MFIv6_MARK, + MFIv4_MARK, + + MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK, + MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK, + MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK, + MEMC_NWE_MARK, MEMC_INT_MARK, + + MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, + MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK, + MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK, + MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, + MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, + MEMC_AD15_MARK, + + /* SIM */ + SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK, + + /* TPU */ + TPU0TO0_MARK, TPU0TO1_MARK, + TPU0TO2_93_MARK, TPU0TO2_99_MARK, + TPU0TO3_MARK, + + /* I2C2 */ + I2C_SCL2_MARK, I2C_SDA2_MARK, + + /* I2C3(1) */ + I2C_SCL3_MARK, I2C_SDA3_MARK, + + /* I2C3(2) */ + I2C_SCL3S_MARK, I2C_SDA3S_MARK, + + /* I2C4(2) */ + I2C_SCL4_MARK, I2C_SDA4_MARK, + + /* I2C4(2) */ + I2C_SCL4S_MARK, I2C_SDA4S_MARK, + + /* KEYSC */ + KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK, + KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK, + KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK, + KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK, + KEYOUT4_MARK, KEYIN4_MARK, + KEYOUT5_MARK, KEYIN5_MARK, + KEYOUT6_MARK, KEYIN6_MARK, + KEYOUT7_MARK, KEYIN7_MARK, + + /* LCDC */ + LCDC0_SELECT_MARK, + LCDC1_SELECT_MARK, + LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK, + LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK, + LCDLCLK_MARK, LCDDON_MARK, + + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, + + /* IRDA */ + IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK, + IROUT_139_MARK, IROUT_140_MARK, + + /* TSIF1 */ + TS0_1SELECT_MARK, + TS0_2SELECT_MARK, + TS1_1SELECT_MARK, + TS1_2SELECT_MARK, + + TS_SPSYNC1_MARK, TS_SDAT1_MARK, + TS_SDEN1_MARK, TS_SCK1_MARK, + + /* TSIF2 */ + TS_SPSYNC2_MARK, TS_SDAT2_MARK, + TS_SDEN2_MARK, TS_SCK2_MARK, + + /* HDMI */ + HDMI_HPD_MARK, HDMI_CEC_MARK, + + /* SDHI0 */ + SDHICLK0_MARK, SDHICD0_MARK, + SDHICMD0_MARK, SDHIWP0_MARK, + SDHID0_0_MARK, SDHID0_1_MARK, + SDHID0_2_MARK, SDHID0_3_MARK, + + /* SDHI1 */ + SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK, + SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, + + /* SDHI2 */ + SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK, + SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, + + /* SDENC */ + SDENC_CPG_MARK, + SDENC_DV_CLKI_MARK, + + PINMUX_MARK_END, +}; + +/* PORT_DATA_I_PD(nr) */ +#define _I___D(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +/* PORT_DATA_I_PU(nr) */ +#define _I__U_(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +/* PORT_DATA_I_PU_PD(nr) */ +#define _I__UD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + +/* PORT_DATA_O(nr) */ +#define __O___(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) + +/* PORT_DATA_IO(nr) */ +#define _IO___(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN) + +/* PORT_DATA_IO_PD(nr) */ +#define _IO__D(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD) + +/* PORT_DATA_IO_PU(nr) */ +#define _IO_U_(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PU) + +/* PORT_DATA_IO_PU_PD(nr) */ +#define _IO_UD(nr) \ + PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ + PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) + + +static pinmux_enum_t pinmux_data[] = { + + /* specify valid pin states for each pin in GPIO mode */ + + _IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4), + _I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9), + + __O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14), + __O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19), + + _IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24), + _IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29), + + _IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34), + _IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39), + + _IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44), + _IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49), + + _IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54), + _IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59), + + _IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64), + _IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/ + + _IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74), + _IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79), + + _IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84), + _IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89), + + _IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94), + _IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/ + + _IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104), + _IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109), + + _IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114), + _IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119), + + _IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124), + _IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129), + + _IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134), + _IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139), + + _IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144), + _IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149), + + _IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154), + _I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159), + + __O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164), + _IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169), + + _I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174), + _IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179), + + _IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184), + __O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189), + + _IO_UD(190), + + /* IRQ */ + PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), + PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1), + PINMUX_DATA(IRQ1_MARK, PORT12_FN0), + PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0), + PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1), + PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0), + PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1), + PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0), + PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1), + PINMUX_DATA(IRQ5_MARK, PORT18_FN0), + PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0), + PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1), + PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1), + PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0), + PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1), + PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0), + PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0), + PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1), + PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1), + PINMUX_DATA(IRQ11_MARK, PORT67_FN0), + PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0), + PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1), + PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0), + PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1), + PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0), + PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1), + PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0), + PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1), + PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0), + PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1), + PINMUX_DATA(IRQ17_MARK, PORT85_FN0), + PINMUX_DATA(IRQ18_MARK, PORT86_FN0), + PINMUX_DATA(IRQ19_MARK, PORT87_FN0), + PINMUX_DATA(IRQ20_MARK, PORT92_FN0), + PINMUX_DATA(IRQ21_MARK, PORT93_FN0), + PINMUX_DATA(IRQ22_MARK, PORT94_FN0), + PINMUX_DATA(IRQ23_MARK, PORT95_FN0), + PINMUX_DATA(IRQ24_MARK, PORT112_FN0), + PINMUX_DATA(IRQ25_MARK, PORT119_FN0), + PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1), + PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0), + PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1), + PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0), + PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1), + PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0), + PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1), + PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0), + PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1), + PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0), + PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1), + PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0), + + /* Function 1 */ + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1), + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1), + PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1), + PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1), + PINMUX_DATA(FSIACK_MARK, PORT4_FN1), + PINMUX_DATA(FSIAILR_MARK, PORT5_FN1), + PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1), + PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1), + PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1), + PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1), + PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1), + PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1), + PINMUX_DATA(FMSOCK_MARK, PORT12_FN1), + PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1), + PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1), + PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1), + PINMUX_DATA(FMSOILR_MARK, PORT16_FN1), + PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1), + PINMUX_DATA(FMSISLD_MARK, PORT18_FN1), + PINMUX_DATA(A0_MARK, PORT19_FN1), + PINMUX_DATA(A1_MARK, PORT20_FN1), + PINMUX_DATA(A2_MARK, PORT21_FN1), + PINMUX_DATA(A3_MARK, PORT22_FN1), + PINMUX_DATA(A4_FOE_MARK, PORT23_FN1), + PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1), + PINMUX_DATA(A6_MARK, PORT25_FN1), + PINMUX_DATA(A7_MARK, PORT26_FN1), + PINMUX_DATA(A8_MARK, PORT27_FN1), + PINMUX_DATA(A9_MARK, PORT28_FN1), + PINMUX_DATA(A10_MARK, PORT29_FN1), + PINMUX_DATA(A11_MARK, PORT30_FN1), + PINMUX_DATA(A12_MARK, PORT31_FN1), + PINMUX_DATA(A13_MARK, PORT32_FN1), + PINMUX_DATA(A14_MARK, PORT33_FN1), + PINMUX_DATA(A15_MARK, PORT34_FN1), + PINMUX_DATA(A16_MARK, PORT35_FN1), + PINMUX_DATA(A17_MARK, PORT36_FN1), + PINMUX_DATA(A18_MARK, PORT37_FN1), + PINMUX_DATA(A19_MARK, PORT38_FN1), + PINMUX_DATA(A20_MARK, PORT39_FN1), + PINMUX_DATA(A21_MARK, PORT40_FN1), + PINMUX_DATA(A22_MARK, PORT41_FN1), + PINMUX_DATA(A23_MARK, PORT42_FN1), + PINMUX_DATA(A24_MARK, PORT43_FN1), + PINMUX_DATA(A25_MARK, PORT44_FN1), + PINMUX_DATA(A26_MARK, PORT45_FN1), + PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1), + PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1), + PINMUX_DATA(CS0_MARK, PORT62_FN1), + PINMUX_DATA(CS2_MARK, PORT63_FN1), + PINMUX_DATA(CS4_MARK, PORT64_FN1), + PINMUX_DATA(CS5A_MARK, PORT65_FN1), + PINMUX_DATA(CS5B_MARK, PORT66_FN1), + PINMUX_DATA(CS6A_MARK, PORT67_FN1), + PINMUX_DATA(FCE0_MARK, PORT68_FN1), + PINMUX_DATA(RD_FSC_MARK, PORT69_FN1), + PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1), + PINMUX_DATA(WE1_MARK, PORT71_FN1), + PINMUX_DATA(CKO_MARK, PORT72_FN1), + PINMUX_DATA(FRB_MARK, PORT73_FN1), + PINMUX_DATA(WAIT_MARK, PORT74_FN1), + PINMUX_DATA(RDWR_MARK, PORT75_FN1), + PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1), + PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1), + PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1), + PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1), + PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1), + PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1), + PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1), + PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1), + PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1), + PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1), + PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1), + PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1), + PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1), + PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1), + PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1), + PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1), + PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1), + PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1), + PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1), + PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1), + PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1), + PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1), + PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1), + PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT100_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT101_FN1), + PINMUX_DATA(VIO_D0_MARK, PORT102_FN1), + PINMUX_DATA(VIO_D1_MARK, PORT103_FN1), + PINMUX_DATA(VIO_D2_MARK, PORT104_FN1), + PINMUX_DATA(VIO_D3_MARK, PORT105_FN1), + PINMUX_DATA(VIO_D4_MARK, PORT106_FN1), + PINMUX_DATA(VIO_D5_MARK, PORT107_FN1), + PINMUX_DATA(VIO_D6_MARK, PORT108_FN1), + PINMUX_DATA(VIO_D7_MARK, PORT109_FN1), + PINMUX_DATA(VIO_D8_MARK, PORT110_FN1), + PINMUX_DATA(VIO_D9_MARK, PORT111_FN1), + PINMUX_DATA(VIO_D10_MARK, PORT112_FN1), + PINMUX_DATA(VIO_D11_MARK, PORT113_FN1), + PINMUX_DATA(VIO_D12_MARK, PORT114_FN1), + PINMUX_DATA(VIO_D13_MARK, PORT115_FN1), + PINMUX_DATA(VIO_D14_MARK, PORT116_FN1), + PINMUX_DATA(VIO_D15_MARK, PORT117_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1), + PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1), + PINMUX_DATA(LCDD0_MARK, PORT121_FN1), + PINMUX_DATA(LCDD1_MARK, PORT122_FN1), + PINMUX_DATA(LCDD2_MARK, PORT123_FN1), + PINMUX_DATA(LCDD3_MARK, PORT124_FN1), + PINMUX_DATA(LCDD4_MARK, PORT125_FN1), + PINMUX_DATA(LCDD5_MARK, PORT126_FN1), + PINMUX_DATA(LCDD6_MARK, PORT127_FN1), + PINMUX_DATA(LCDD7_MARK, PORT128_FN1), + PINMUX_DATA(LCDD8_MARK, PORT129_FN1), + PINMUX_DATA(LCDD9_MARK, PORT130_FN1), + PINMUX_DATA(LCDD10_MARK, PORT131_FN1), + PINMUX_DATA(LCDD11_MARK, PORT132_FN1), + PINMUX_DATA(LCDD12_MARK, PORT133_FN1), + PINMUX_DATA(LCDD13_MARK, PORT134_FN1), + PINMUX_DATA(LCDD14_MARK, PORT135_FN1), + PINMUX_DATA(LCDD15_MARK, PORT136_FN1), + PINMUX_DATA(LCDD16_MARK, PORT137_FN1), + PINMUX_DATA(LCDD17_MARK, PORT138_FN1), + PINMUX_DATA(LCDD18_MARK, PORT139_FN1), + PINMUX_DATA(LCDD19_MARK, PORT140_FN1), + PINMUX_DATA(LCDD20_MARK, PORT141_FN1), + PINMUX_DATA(LCDD21_MARK, PORT142_FN1), + PINMUX_DATA(LCDD22_MARK, PORT143_FN1), + PINMUX_DATA(LCDD23_MARK, PORT144_FN1), + PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1), + PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1), + PINMUX_DATA(LCDDCK_MARK, PORT147_FN1), + PINMUX_DATA(LCDRD_MARK, PORT148_FN1), + PINMUX_DATA(LCDDISP_MARK, PORT149_FN1), + PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1), + PINMUX_DATA(LCDDON_MARK, PORT151_FN1), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1), + PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1), + PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1), + PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1), + PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1), + PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1), + PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1), + PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1), + PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1), + PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1), + PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1), + PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1), + PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1), + PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1), + PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1), + PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1), + PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1), + PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1), + PINMUX_DATA(SDHICD0_MARK, PORT172_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1), + PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1), + PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1), + PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1), + PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1), + PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1), + PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1), + PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1), + PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1), + PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1), + PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1), + PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1), + + /* Function 2 */ + PINMUX_DATA(FSIBCK_MARK, PORT4_FN2), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2), + PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2), + PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2), + PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2), + PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2), + PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2), + PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2), + PINMUX_DATA(FMSIILR_MARK, PORT16_FN2), + PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2), + PINMUX_DATA(BS_MARK, PORT19_FN2), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2), + PINMUX_DATA(FMSICK_MARK, PORT65_FN2), + PINMUX_DATA(FCE1_MARK, PORT66_FN2), + PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2), + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2), + PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2), + PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2), + PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2), + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2), + PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2), + PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2), + PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1), + PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2), + PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2), + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2), + PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2), + PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2), + PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1), + PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1), + PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1), + PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2), + PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2), + PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1), + PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2), + PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2), + PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2), + PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2), + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2), + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2), + PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2), + PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2), + PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2), + PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2), + PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2), + + /* Function 3 */ + PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3), + PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3), + PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1), + PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0), + PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0), + PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1), + PINMUX_DATA(VINT_I_MARK, PORT65_FN3), + PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1), + PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3), + PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3), + PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3), + PINMUX_DATA(IDIN_0_MARK, PORT113_FN3), + PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3), + PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3), + PINMUX_DATA(PWEN_0_MARK, PORT116_FN3), + PINMUX_DATA(OVCN_0_MARK, PORT117_FN3), + PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3), + PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3), + PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3), + PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3), + PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3), + PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3), + PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3), + PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3), + PINMUX_DATA(KEYIN7_MARK, PORT129_FN3), + PINMUX_DATA(KEYIN6_MARK, PORT130_FN3), + PINMUX_DATA(KEYIN5_MARK, PORT131_FN3), + PINMUX_DATA(KEYIN4_MARK, PORT132_FN3), + PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0), + PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0), + PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3), + PINMUX_DATA(IROUT_139_MARK, PORT139_FN3), + PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3), + PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3), + PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3), + PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3), + PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3), + + /* Function 4 */ + PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0), + PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4), + PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4), + PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4), + PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4), + PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4), + PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4), + PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4), + PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4), + PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4), + PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0), + PINMUX_DATA(SIM_RST_MARK, PORT94_FN4), + PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4), + PINMUX_DATA(SIM_D_MARK, PORT98_FN4), + PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0), + PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0), + PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0), + PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4), + PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4), + PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4), + PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1), + PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1), + PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4), + PINMUX_DATA(IROUT_140_MARK, PORT140_FN4), + PINMUX_DATA(LCDCS_MARK, PORT145_FN4), + PINMUX_DATA(LCDWR_MARK, PORT147_FN4), + PINMUX_DATA(LCDRS_MARK, PORT149_FN4), + PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1), + + /* Function 5 */ + PINMUX_DATA(GPI0_MARK, PORT41_FN5), + PINMUX_DATA(GPI1_MARK, PORT42_FN5), + PINMUX_DATA(GPO0_MARK, PORT43_FN5), + PINMUX_DATA(GPO1_MARK, PORT44_FN5), + PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0), + PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0), + PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0), + PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0), + + /* Function select */ + PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), + PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), + + PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0), + PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1), + PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0), + PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1), + + PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), + PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), + + PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0), + PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), +}; + +#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) +#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) + +static struct pinmux_gpio pinmux_gpios[] = { + + /* PORT */ + GPIO_PORT_ALL(), + + /* IRQ */ + GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), + GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), + GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), + GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), + GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), + GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), + GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), + GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), + GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), + GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), + GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), + GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), + GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), + GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), + GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), + GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), + GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), + + /* MSIOF0 */ + GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), + GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), + GPIO_FN(MSIOF0_TXD), + + /* MSIOF1 */ + GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), + GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), + GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), + GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), + GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), + GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), + GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + + /* MSIOF2 */ + GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), + GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), + GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), + GPIO_FN(MSIOF2_TXD), + + /* MSIOF3 */ + GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), + GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), + GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), + + /* MSIOF4 */ + GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), + + /* FSI */ + GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), + GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), + GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), + GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), + + /* FMSI */ + GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), + GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), + GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), + GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), + + /* SCIFA0 */ + GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), + GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), + + /* SCIFA1 */ + GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), + GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), + + /* SCIFA2 */ + GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), + GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), + + /* SCIFA3 */ + GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), + GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), + GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), + GPIO_FN(SCIFA3_RXD), + + /* SCIFA4 */ + GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), + + /* SCIFA5 */ + GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), + + /* SCIFB */ + GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), + GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), + + /* CEU */ + GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), + GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), + GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), + GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), + GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), + GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), + GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), + GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), + + /* USB0 */ + GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), + GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), + + /* USB1 */ + GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), + GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), + GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), + GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), + GPIO_FN(VBUS0_1), + + /* GPIO */ + GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), + + /* BSC */ + GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), + GPIO_FN(WAIT), GPIO_FN(RDWR), + + GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), + GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), + GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), + GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), + GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), + GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), + GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), + GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), + GPIO_FN(A26), + + GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), + GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), + + /* BSC/FLCTL */ + GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), + GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), + GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), + GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), + GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), + GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), + GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), + + /* MMCIF(1) */ + GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5), + GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0), + GPIO_FN(MMCCLK0), + + /* MMCIF(2) */ + GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2), + GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5), + GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1), + GPIO_FN(MMCCMD1), + + /* SPU2 */ + GPIO_FN(VINT_I), + + /* FLCTL */ + GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), + + /* HSI */ + GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), + GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), + GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), + + /* MFI */ + GPIO_FN(MFIv6), + GPIO_FN(MFIv4), + + GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), + GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), + GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), + GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), + + GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), + GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), + GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), + GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), + GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), + GPIO_FN(MEMC_AD15), + + /* SIM */ + GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), + + /* TPU */ + GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), + GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), + + /* I2C2 */ + GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), + + /* I2C3(1) */ + GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), + + /* I2C3(2) */ + GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), + + /* I2C4(2) */ + GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), + + /* I2C4(2) */ + GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), + + /* KEYSC */ + GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), + GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), + GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), + GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), + GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), + GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), + GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), + + /* LCDC */ + GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), + GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), + GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), + GPIO_FN(LCDDON), + + GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), + GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), + GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), + GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), + GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), + GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), + GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), + GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), + + /* IRDA */ + GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), + GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), + + /* TSIF1 */ + GPIO_FN(TS0_1SELECT), + GPIO_FN(TS0_2SELECT), + GPIO_FN(TS1_1SELECT), + GPIO_FN(TS1_2SELECT), + + GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), + GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), + + /* TSIF2 */ + GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), + GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), + + /* HDMI */ + GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), + + /* SDHI0 */ + GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0), + GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3), + + /* SDHI1 */ + GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0), + GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3), + + /* SDHI2 */ + GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0), + GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3), + + /* SDENC */ + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), +}; + +/* helper for top 4 bits in PORTnCR */ +#define PCRH(in, in_pd, in_pu, out) \ + 0, (out), (in), 0, \ + 0, 0, 0, 0, \ + 0, 0, (in_pd), 0, \ + 0, 0, (in_pu), 0 + +#define PORTCR(nr, reg) \ + { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ + PORT##nr##_IN_PU, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ + PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xE6051000), /* PORT0CR */ + PORTCR(1, 0xE6051001), /* PORT1CR */ + PORTCR(2, 0xE6051002), /* PORT2CR */ + PORTCR(3, 0xE6051003), /* PORT3CR */ + PORTCR(4, 0xE6051004), /* PORT4CR */ + PORTCR(5, 0xE6051005), /* PORT5CR */ + PORTCR(6, 0xE6051006), /* PORT6CR */ + PORTCR(7, 0xE6051007), /* PORT7CR */ + PORTCR(8, 0xE6051008), /* PORT8CR */ + PORTCR(9, 0xE6051009), /* PORT9CR */ + PORTCR(10, 0xE605100A), /* PORT10CR */ + PORTCR(11, 0xE605100B), /* PORT11CR */ + PORTCR(12, 0xE605100C), /* PORT12CR */ + PORTCR(13, 0xE605100D), /* PORT13CR */ + PORTCR(14, 0xE605100E), /* PORT14CR */ + PORTCR(15, 0xE605100F), /* PORT15CR */ + PORTCR(16, 0xE6051010), /* PORT16CR */ + PORTCR(17, 0xE6051011), /* PORT17CR */ + PORTCR(18, 0xE6051012), /* PORT18CR */ + PORTCR(19, 0xE6051013), /* PORT19CR */ + PORTCR(20, 0xE6051014), /* PORT20CR */ + PORTCR(21, 0xE6051015), /* PORT21CR */ + PORTCR(22, 0xE6051016), /* PORT22CR */ + PORTCR(23, 0xE6051017), /* PORT23CR */ + PORTCR(24, 0xE6051018), /* PORT24CR */ + PORTCR(25, 0xE6051019), /* PORT25CR */ + PORTCR(26, 0xE605101A), /* PORT26CR */ + PORTCR(27, 0xE605101B), /* PORT27CR */ + PORTCR(28, 0xE605101C), /* PORT28CR */ + PORTCR(29, 0xE605101D), /* PORT29CR */ + PORTCR(30, 0xE605101E), /* PORT30CR */ + PORTCR(31, 0xE605101F), /* PORT31CR */ + PORTCR(32, 0xE6051020), /* PORT32CR */ + PORTCR(33, 0xE6051021), /* PORT33CR */ + PORTCR(34, 0xE6051022), /* PORT34CR */ + PORTCR(35, 0xE6051023), /* PORT35CR */ + PORTCR(36, 0xE6051024), /* PORT36CR */ + PORTCR(37, 0xE6051025), /* PORT37CR */ + PORTCR(38, 0xE6051026), /* PORT38CR */ + PORTCR(39, 0xE6051027), /* PORT39CR */ + PORTCR(40, 0xE6051028), /* PORT40CR */ + PORTCR(41, 0xE6051029), /* PORT41CR */ + PORTCR(42, 0xE605102A), /* PORT42CR */ + PORTCR(43, 0xE605102B), /* PORT43CR */ + PORTCR(44, 0xE605102C), /* PORT44CR */ + PORTCR(45, 0xE605102D), /* PORT45CR */ + PORTCR(46, 0xE605202E), /* PORT46CR */ + PORTCR(47, 0xE605202F), /* PORT47CR */ + PORTCR(48, 0xE6052030), /* PORT48CR */ + PORTCR(49, 0xE6052031), /* PORT49CR */ + PORTCR(50, 0xE6052032), /* PORT50CR */ + PORTCR(51, 0xE6052033), /* PORT51CR */ + PORTCR(52, 0xE6052034), /* PORT52CR */ + PORTCR(53, 0xE6052035), /* PORT53CR */ + PORTCR(54, 0xE6052036), /* PORT54CR */ + PORTCR(55, 0xE6052037), /* PORT55CR */ + PORTCR(56, 0xE6052038), /* PORT56CR */ + PORTCR(57, 0xE6052039), /* PORT57CR */ + PORTCR(58, 0xE605203A), /* PORT58CR */ + PORTCR(59, 0xE605203B), /* PORT59CR */ + PORTCR(60, 0xE605203C), /* PORT60CR */ + PORTCR(61, 0xE605203D), /* PORT61CR */ + PORTCR(62, 0xE605203E), /* PORT62CR */ + PORTCR(63, 0xE605203F), /* PORT63CR */ + PORTCR(64, 0xE6052040), /* PORT64CR */ + PORTCR(65, 0xE6052041), /* PORT65CR */ + PORTCR(66, 0xE6052042), /* PORT66CR */ + PORTCR(67, 0xE6052043), /* PORT67CR */ + PORTCR(68, 0xE6052044), /* PORT68CR */ + PORTCR(69, 0xE6052045), /* PORT69CR */ + PORTCR(70, 0xE6052046), /* PORT70CR */ + PORTCR(71, 0xE6052047), /* PORT71CR */ + PORTCR(72, 0xE6052048), /* PORT72CR */ + PORTCR(73, 0xE6052049), /* PORT73CR */ + PORTCR(74, 0xE605204A), /* PORT74CR */ + PORTCR(75, 0xE605204B), /* PORT75CR */ + PORTCR(76, 0xE605004C), /* PORT76CR */ + PORTCR(77, 0xE605004D), /* PORT77CR */ + PORTCR(78, 0xE605004E), /* PORT78CR */ + PORTCR(79, 0xE605004F), /* PORT79CR */ + PORTCR(80, 0xE6050050), /* PORT80CR */ + PORTCR(81, 0xE6050051), /* PORT81CR */ + PORTCR(82, 0xE6050052), /* PORT82CR */ + PORTCR(83, 0xE6050053), /* PORT83CR */ + PORTCR(84, 0xE6050054), /* PORT84CR */ + PORTCR(85, 0xE6050055), /* PORT85CR */ + PORTCR(86, 0xE6050056), /* PORT86CR */ + PORTCR(87, 0xE6050057), /* PORT87CR */ + PORTCR(88, 0xE6050058), /* PORT88CR */ + PORTCR(89, 0xE6050059), /* PORT89CR */ + PORTCR(90, 0xE605005A), /* PORT90CR */ + PORTCR(91, 0xE605005B), /* PORT91CR */ + PORTCR(92, 0xE605005C), /* PORT92CR */ + PORTCR(93, 0xE605005D), /* PORT93CR */ + PORTCR(94, 0xE605005E), /* PORT94CR */ + PORTCR(95, 0xE605005F), /* PORT95CR */ + PORTCR(96, 0xE6050060), /* PORT96CR */ + PORTCR(97, 0xE6050061), /* PORT97CR */ + PORTCR(98, 0xE6050062), /* PORT98CR */ + PORTCR(99, 0xE6050063), /* PORT99CR */ + PORTCR(100, 0xE6053064), /* PORT100CR */ + PORTCR(101, 0xE6053065), /* PORT101CR */ + PORTCR(102, 0xE6053066), /* PORT102CR */ + PORTCR(103, 0xE6053067), /* PORT103CR */ + PORTCR(104, 0xE6053068), /* PORT104CR */ + PORTCR(105, 0xE6053069), /* PORT105CR */ + PORTCR(106, 0xE605306A), /* PORT106CR */ + PORTCR(107, 0xE605306B), /* PORT107CR */ + PORTCR(108, 0xE605306C), /* PORT108CR */ + PORTCR(109, 0xE605306D), /* PORT109CR */ + PORTCR(110, 0xE605306E), /* PORT110CR */ + PORTCR(111, 0xE605306F), /* PORT111CR */ + PORTCR(112, 0xE6053070), /* PORT112CR */ + PORTCR(113, 0xE6053071), /* PORT113CR */ + PORTCR(114, 0xE6053072), /* PORT114CR */ + PORTCR(115, 0xE6053073), /* PORT115CR */ + PORTCR(116, 0xE6053074), /* PORT116CR */ + PORTCR(117, 0xE6053075), /* PORT117CR */ + PORTCR(118, 0xE6053076), /* PORT118CR */ + PORTCR(119, 0xE6053077), /* PORT119CR */ + PORTCR(120, 0xE6053078), /* PORT120CR */ + PORTCR(121, 0xE6050079), /* PORT121CR */ + PORTCR(122, 0xE605007A), /* PORT122CR */ + PORTCR(123, 0xE605007B), /* PORT123CR */ + PORTCR(124, 0xE605007C), /* PORT124CR */ + PORTCR(125, 0xE605007D), /* PORT125CR */ + PORTCR(126, 0xE605007E), /* PORT126CR */ + PORTCR(127, 0xE605007F), /* PORT127CR */ + PORTCR(128, 0xE6050080), /* PORT128CR */ + PORTCR(129, 0xE6050081), /* PORT129CR */ + PORTCR(130, 0xE6050082), /* PORT130CR */ + PORTCR(131, 0xE6050083), /* PORT131CR */ + PORTCR(132, 0xE6050084), /* PORT132CR */ + PORTCR(133, 0xE6050085), /* PORT133CR */ + PORTCR(134, 0xE6050086), /* PORT134CR */ + PORTCR(135, 0xE6050087), /* PORT135CR */ + PORTCR(136, 0xE6050088), /* PORT136CR */ + PORTCR(137, 0xE6050089), /* PORT137CR */ + PORTCR(138, 0xE605008A), /* PORT138CR */ + PORTCR(139, 0xE605008B), /* PORT139CR */ + PORTCR(140, 0xE605008C), /* PORT140CR */ + PORTCR(141, 0xE605008D), /* PORT141CR */ + PORTCR(142, 0xE605008E), /* PORT142CR */ + PORTCR(143, 0xE605008F), /* PORT143CR */ + PORTCR(144, 0xE6050090), /* PORT144CR */ + PORTCR(145, 0xE6050091), /* PORT145CR */ + PORTCR(146, 0xE6050092), /* PORT146CR */ + PORTCR(147, 0xE6050093), /* PORT147CR */ + PORTCR(148, 0xE6050094), /* PORT148CR */ + PORTCR(149, 0xE6050095), /* PORT149CR */ + PORTCR(150, 0xE6050096), /* PORT150CR */ + PORTCR(151, 0xE6050097), /* PORT151CR */ + PORTCR(152, 0xE6053098), /* PORT152CR */ + PORTCR(153, 0xE6053099), /* PORT153CR */ + PORTCR(154, 0xE605309A), /* PORT154CR */ + PORTCR(155, 0xE605309B), /* PORT155CR */ + PORTCR(156, 0xE605009C), /* PORT156CR */ + PORTCR(157, 0xE605009D), /* PORT157CR */ + PORTCR(158, 0xE605009E), /* PORT158CR */ + PORTCR(159, 0xE605009F), /* PORT159CR */ + PORTCR(160, 0xE60500A0), /* PORT160CR */ + PORTCR(161, 0xE60500A1), /* PORT161CR */ + PORTCR(162, 0xE60500A2), /* PORT162CR */ + PORTCR(163, 0xE60500A3), /* PORT163CR */ + PORTCR(164, 0xE60500A4), /* PORT164CR */ + PORTCR(165, 0xE60500A5), /* PORT165CR */ + PORTCR(166, 0xE60500A6), /* PORT166CR */ + PORTCR(167, 0xE60520A7), /* PORT167CR */ + PORTCR(168, 0xE60520A8), /* PORT168CR */ + PORTCR(169, 0xE60520A9), /* PORT169CR */ + PORTCR(170, 0xE60520AA), /* PORT170CR */ + PORTCR(171, 0xE60520AB), /* PORT171CR */ + PORTCR(172, 0xE60520AC), /* PORT172CR */ + PORTCR(173, 0xE60520AD), /* PORT173CR */ + PORTCR(174, 0xE60520AE), /* PORT174CR */ + PORTCR(175, 0xE60520AF), /* PORT175CR */ + PORTCR(176, 0xE60520B0), /* PORT176CR */ + PORTCR(177, 0xE60520B1), /* PORT177CR */ + PORTCR(178, 0xE60520B2), /* PORT178CR */ + PORTCR(179, 0xE60520B3), /* PORT179CR */ + PORTCR(180, 0xE60520B4), /* PORT180CR */ + PORTCR(181, 0xE60520B5), /* PORT181CR */ + PORTCR(182, 0xE60520B6), /* PORT182CR */ + PORTCR(183, 0xE60520B7), /* PORT183CR */ + PORTCR(184, 0xE60520B8), /* PORT184CR */ + PORTCR(185, 0xE60520B9), /* PORT185CR */ + PORTCR(186, 0xE60520BA), /* PORT186CR */ + PORTCR(187, 0xE60520BB), /* PORT187CR */ + PORTCR(188, 0xE60520BC), /* PORT188CR */ + PORTCR(189, 0xE60520BD), /* PORT189CR */ + PORTCR(190, 0xE60520BE), /* PORT190CR */ + + { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + 0, 0, 0, 0, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_8_0, MSEL1CR_8_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + 0, 0, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + 0, 0, + MSEL1CR_0_0, MSEL1CR_0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, + MSEL3CR_9_0, MSEL3CR_9_1, + 0, 0, 0, 0, + MSEL3CR_6_0, MSEL3CR_6_1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + 0, 0, 0, 0, + 0, 0, + MSEL4CR_10_0, MSEL4CR_10_1, + 0, 0, 0, 0, + 0, 0, + MSEL4CR_6_0, MSEL4CR_6_1, + 0, 0, + MSEL4CR_4_0, MSEL4CR_4_1, + 0, 0, 0, 0, + MSEL4CR_1_0, MSEL4CR_1_1, + 0, 0, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, + } + }, + { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + 0, 0, 0, 0, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, + } + }, + { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, + } + }, + { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, + } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, + } + }, + { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, + } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) { + 0, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) { + 0, 0, 0, 0, + 0, 0, 0, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + 0, 0, 0, 0, + } + }, + { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) { + 0, 0, 0, 0, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { }, +}; + +static struct pinmux_info sh7372_pinmux_info = { + .name = "sh7372_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_SDENC_DV_CLKI, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void sh7372_pinmux_init(void) +{ + register_pinmux(&sh7372_pinmux_info); +} From 1b7e0677fb1513605df327ae2987d17e0b2ae3ea Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 17 Feb 2010 09:30:14 +0000 Subject: [PATCH 21/27] ARM: mach-shmobile: SMSC 9220 support for AP4EVB. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 94b545b3fe82..70277e073808 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -27,11 +27,15 @@ #include #include #include +#include +#include #include +#include #include #include #include +/* MTD */ static struct mtd_partition nor_flash_partitions[] = { { .name = "loader", @@ -84,9 +88,37 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +/* SMSC 9220 */ +static struct resource smc911x_resources[] = { + { + .start = 0x14000000, + .end = 0x16000000 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 6, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct smsc911x_platform_config smsc911x_info = { + .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device smc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, + .dev = { + .platform_data = &smsc911x_info, + }, +}; static struct platform_device *ap4evb_devices[] __initdata = { &nor_flash_device, + &smc911x_device, }; static struct map_desc ap4evb_io_desc[] __initdata = { @@ -113,6 +145,12 @@ static void __init ap4evb_map_io(void) static void __init ap4evb_init(void) { + sh7372_pinmux_init(); + + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); From b228b48e454007436a8e6ff1c6b6f4f6602fc45e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 18 Feb 2010 16:44:41 +0900 Subject: [PATCH 22/27] ARM: mach-shmobile: ap4evb: Add SCIFA0 support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 70277e073808..4fd9ec8735d6 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -147,6 +147,10 @@ static void __init ap4evb_init(void) { sh7372_pinmux_init(); + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIFA0_TXD, NULL); + gpio_request(GPIO_FN_SCIFA0_RXD, NULL); + /* enable SMSC911X */ gpio_request(GPIO_FN_CS5A, NULL); gpio_request(GPIO_FN_IRQ6_39, NULL); From 02624a17896036c663fd5992c22919af8dad93ed Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 18 Feb 2010 17:58:19 +0900 Subject: [PATCH 23/27] ARM: mach-shmobile: ap4evb: Add tiny document Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 4fd9ec8735d6..41bc2487de4d 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -35,6 +35,48 @@ #include #include +/* + * Address Interface BusWidth note + * ------------------------------------------------------------------ + * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON + * 0x0800_0000 user area - + * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF + * 0x1400_0000 Ether (LAN9220) 16bit + * 0x1600_0000 user area - cannot use with NAND + * 0x1800_0000 user area - + * 0x1A00_0000 - + * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit + */ + +/* + * NOR Flash ROM + * + * SW1 | SW2 | SW7 | NOR Flash ROM + * bit1 | bit1 bit2 | bit1 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | Area 0 + * OFF | ON OFF | OFF | Area 4 + */ + +/* + * NAND Flash ROM + * + * SW1 | SW2 | SW7 | NAND Flash ROM + * bit1 | bit1 bit2 | bit2 | Memory allocation + * ------+------------+------+------------------ + * OFF | ON OFF | ON | FCE 0 + * OFF | ON OFF | OFF | FCE 1 + */ + +/* + * SMSC 9220 + * + * SW1 SMSC 9220 + * ----------------------- + * ON access disable + * OFF access enable + */ + /* MTD */ static struct mtd_partition nor_flash_partitions[] = { { From 5098280e015e36daebfd16f976ec3db6f4975fac Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 22 Feb 2010 09:20:39 +0000 Subject: [PATCH 24/27] ARM: mach-shmobile: ap4evb: Add LED support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 41bc2487de4d..4714cad373b8 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -197,6 +197,20 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_CS5A, NULL); gpio_request(GPIO_FN_IRQ6_39, NULL); + /* enable LED 1 - 4 */ + gpio_request(GPIO_PORT185, NULL); + gpio_request(GPIO_PORT186, NULL); + gpio_request(GPIO_PORT187, NULL); + gpio_request(GPIO_PORT188, NULL); + gpio_direction_output(GPIO_PORT185, 1); + gpio_direction_output(GPIO_PORT186, 1); + gpio_direction_output(GPIO_PORT187, 1); + gpio_direction_output(GPIO_PORT188, 1); + gpio_export(GPIO_PORT185, 0); + gpio_export(GPIO_PORT186, 0); + gpio_export(GPIO_PORT187, 0); + gpio_export(GPIO_PORT188, 0); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); From 8cb3a2ebc19eef58bcbd5460c4fb463f30bc6459 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 22 Feb 2010 09:30:12 +0000 Subject: [PATCH 25/27] ARM: mach-shmobile: ap4evb: Add S6 debug switch support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 4714cad373b8..d9a46d0ce01c 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -211,6 +211,20 @@ static void __init ap4evb_init(void) gpio_export(GPIO_PORT187, 0); gpio_export(GPIO_PORT188, 0); + /* enable Debug switch (S6) */ + gpio_request(GPIO_PORT32, NULL); + gpio_request(GPIO_PORT33, NULL); + gpio_request(GPIO_PORT34, NULL); + gpio_request(GPIO_PORT35, NULL); + gpio_direction_input(GPIO_PORT32); + gpio_direction_input(GPIO_PORT33); + gpio_direction_input(GPIO_PORT34); + gpio_direction_input(GPIO_PORT35); + gpio_export(GPIO_PORT32, 0); + gpio_export(GPIO_PORT33, 0); + gpio_export(GPIO_PORT34, 0); + gpio_export(GPIO_PORT35, 0); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); From 41dcc17c735d4e99a91002b09850d0f09ee4ab4b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 19 Feb 2010 07:52:12 +0000 Subject: [PATCH 26/27] ARM: mach-shmobile: pfc-sh7377: modify KEYIN settings Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/pfc-sh7377.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c index 79b53d87d91b..613e6842ad05 100644 --- a/arch/arm/mach-shmobile/pfc-sh7377.c +++ b/arch/arm/mach-shmobile/pfc-sh7377.c @@ -102,6 +102,7 @@ enum { PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */ MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, + MSELBCR_MSEL16_1, MSELBCR_MSEL16_0, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, @@ -528,19 +529,19 @@ static pinmux_enum_t pinmux_data[] = { PORT_DATA_IO_PU_PD(263), /* Special Pull-up / Pull-down Functions */ - PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT66_FN2, PORT66_IN_PU), - PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT67_FN2, PORT67_IN_PU), - PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT68_FN2, PORT68_IN_PU), - PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT69_FN2, PORT69_IN_PU), - PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT70_FN2, PORT70_IN_PU), - PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT71_FN2, PORT71_IN_PU), - PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, + PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, PORT72_FN2, PORT72_IN_PU), @@ -1637,7 +1638,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MSELBCR_MSEL17_0, MSELBCR_MSEL17_1, - 0, 0, + MSELBCR_MSEL16_0, MSELBCR_MSEL16_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, From 17ccb834d517c66c09123c24ba8553c5b14e0f78 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 23 Feb 2010 07:07:01 +0000 Subject: [PATCH 27/27] ARM: mach-shmobile: ap4evb: Add KEYSC support Because AP4 board has capacitor for KEYSC, we need much time for waiting. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index d9a46d0ce01c..a0463d926447 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include #include @@ -77,6 +79,15 @@ * OFF access enable */ +/* + * KEYSC + * + * SW43 KEYSC + * ------------------------- + * ON enable + * OFF disable + */ + /* MTD */ static struct mtd_partition nor_flash_partitions[] = { { @@ -158,9 +169,47 @@ static struct platform_device smc911x_device = { }, }; +/* KEYSC (Needs SW43 set to ON) */ +static struct sh_keysc_info keysc_info = { + .mode = SH_KEYSC_MODE_1, + .scan_timing = 3, + .delay = 2500, + .keycodes = { + KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, + KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, + KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, + KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, + KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, + }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0xe61b0000, + .end = 0xe61b0063, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 79, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_info, + }, +}; + static struct platform_device *ap4evb_devices[] __initdata = { &nor_flash_device, &smc911x_device, + &keysc_device, }; static struct map_desc ap4evb_io_desc[] __initdata = { @@ -225,6 +274,18 @@ static void __init ap4evb_init(void) gpio_export(GPIO_PORT34, 0); gpio_export(GPIO_PORT35, 0); + /* enable KEYSC */ + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4, NULL); + gpio_request(GPIO_FN_KEYIN0_136, NULL); + gpio_request(GPIO_FN_KEYIN1_135, NULL); + gpio_request(GPIO_FN_KEYIN2_134, NULL); + gpio_request(GPIO_FN_KEYIN3_133, NULL); + gpio_request(GPIO_FN_KEYIN4, NULL); + sh7372_add_standard_devices(); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));