drm/radeon: handle cg in KB/KV dpm code
Clockgating needs to be disabled around certain parts of dpm setup otherwise the smc gets into a bad state and dpm doesn't work properly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cf0ab2cd45
Коммит
6500fc0c9f
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@ -1105,6 +1105,11 @@ int kv_dpm_enable(struct radeon_device *rdev)
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struct kv_power_info *pi = kv_get_pi(rdev);
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struct kv_power_info *pi = kv_get_pi(rdev);
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int ret;
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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ret = kv_process_firmware_header(rdev);
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ret = kv_process_firmware_header(rdev);
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if (ret) {
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if (ret) {
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DRM_ERROR("kv_process_firmware_header failed\n");
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DRM_ERROR("kv_process_firmware_header failed\n");
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@ -1204,6 +1209,11 @@ int kv_dpm_enable(struct radeon_device *rdev)
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kv_dpm_powergate_vce(rdev, true);
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kv_dpm_powergate_vce(rdev, true);
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kv_dpm_powergate_uvd(rdev, true);
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kv_dpm_powergate_uvd(rdev, true);
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), true);
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kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
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kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
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return ret;
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return ret;
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@ -1211,6 +1221,11 @@ int kv_dpm_enable(struct radeon_device *rdev)
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void kv_dpm_disable(struct radeon_device *rdev)
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void kv_dpm_disable(struct radeon_device *rdev)
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{
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{
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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kv_enable_smc_cac(rdev, false);
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kv_enable_smc_cac(rdev, false);
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kv_enable_didt(rdev, false);
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kv_enable_didt(rdev, false);
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kv_clear_vc(rdev);
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kv_clear_vc(rdev);
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@ -1695,6 +1710,11 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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/*struct radeon_ps *old_ps = &pi->current_rps;*/
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/*struct radeon_ps *old_ps = &pi->current_rps;*/
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int ret;
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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if (rdev->family == CHIP_KABINI) {
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if (rdev->family == CHIP_KABINI) {
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if (pi->enable_dpm) {
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if (pi->enable_dpm) {
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kv_set_valid_clock_range(rdev, new_ps);
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kv_set_valid_clock_range(rdev, new_ps);
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@ -1750,6 +1770,12 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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kv_enable_nb_dpm(rdev);
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kv_enable_nb_dpm(rdev);
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}
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}
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}
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}
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), true);
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rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
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rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
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return 0;
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return 0;
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}
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}
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