drm/radeon: Use direct mapping for fast fb access on RS780/RS880 (v2)
v2: fix trailing whitespace Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e49f3959a9
Коммит
65337e60a7
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@ -1046,6 +1046,24 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
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return -1;
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}
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uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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uint32_t r;
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WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
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r = RREG32(R_0028FC_MC_DATA);
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WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
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return r;
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}
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void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
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S_0028F8_MC_IND_WR_EN(1));
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WREG32(R_0028FC_MC_DATA, v);
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WREG32(R_0028F8_MC_INDEX, 0x7F);
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}
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static void r600_mc_program(struct radeon_device *rdev)
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{
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struct rv515_mc_save save;
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@ -1181,6 +1199,8 @@ static int r600_mc_init(struct radeon_device *rdev)
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{
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u32 tmp;
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int chansize, numchan;
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uint32_t h_addr, l_addr;
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unsigned long long k8_addr;
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/* Get VRAM informations */
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rdev->mc.vram_is_ddr = true;
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@ -1221,7 +1241,30 @@ static int r600_mc_init(struct radeon_device *rdev)
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if (rdev->flags & RADEON_IS_IGP) {
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rs690_pm_info(rdev);
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
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/* Use K8 direct mapping for fast fb access. */
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rdev->fastfb_working = false;
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h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
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l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
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k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
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#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
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if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
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#endif
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{
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/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
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* memory is present.
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*/
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if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
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DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
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(unsigned long long)rdev->mc.aper_base, k8_addr);
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rdev->mc.aper_base = (resource_size_t)k8_addr;
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rdev->fastfb_working = true;
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}
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}
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}
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}
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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@ -1342,6 +1342,14 @@
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#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
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#define PACKET3_SURFACE_BASE_UPDATE 0x73
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#define R_000011_K8_FB_LOCATION 0x11
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#define R_000012_MC_MISC_UMA_CNTL 0x12
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#define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
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#define R_0028F8_MC_INDEX 0x28F8
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#define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
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#define C_0028F8_MC_IND_ADDR 0xFFFFFE00
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#define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
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#define R_0028FC_MC_DATA 0x28FC
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#define R_008020_GRBM_SOFT_RESET 0x8020
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#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
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@ -122,6 +122,10 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
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rdev->mc_rreg = &rs780_mc_rreg;
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rdev->mc_wreg = &rs780_mc_wreg;
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}
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if (rdev->family >= CHIP_R600) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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@ -347,6 +347,8 @@ extern bool r600_gui_idle(struct radeon_device *rdev);
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extern void r600_pm_misc(struct radeon_device *rdev);
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extern void r600_pm_init_profile(struct radeon_device *rdev);
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extern void rs780_pm_init_profile(struct radeon_device *rdev);
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extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
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extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
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extern int r600_get_pcie_lanes(struct radeon_device *rdev);
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