clocksource/drivers/imx-tpm: Correct some registers operation flow
[ Upstream commit 506a7be93f
]
According to i.MX7ULP reference manual, TPM_SC_CPWMS can ONLY be written when
counter is disabled, TPM_SC_TOF is write-1-clear, TPM_C0SC_CHF is also
write-1-clear, correct these registers initialization flow;
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Родитель
cda6fd4d93
Коммит
65783949c8
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@ -20,6 +20,7 @@
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#define TPM_SC 0x10
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#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
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#define TPM_SC_CMOD_DIV_DEFAULT 0x3
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#define TPM_SC_TOF_MASK (0x1 << 7)
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#define TPM_CNT 0x14
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#define TPM_MOD 0x18
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#define TPM_STATUS 0x1c
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@ -29,6 +30,7 @@
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#define TPM_C0SC_MODE_SHIFT 2
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#define TPM_C0SC_MODE_MASK 0x3c
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#define TPM_C0SC_MODE_SW_COMPARE 0x4
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#define TPM_C0SC_CHF_MASK (0x1 << 7)
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#define TPM_C0V 0x24
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static void __iomem *timer_base;
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@ -205,9 +207,13 @@ static int __init tpm_timer_init(struct device_node *np)
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* 4) Channel0 disabled
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* 5) DMA transfers disabled
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*/
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/* make sure counter is disabled */
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writel(0, timer_base + TPM_SC);
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/* TOF is W1C */
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writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
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writel(0, timer_base + TPM_CNT);
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writel(0, timer_base + TPM_C0SC);
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/* CHF is W1C */
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writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
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/* increase per cnt, div 8 by default */
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writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
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