dt-bindings: clock: gcc-sdm845: add sdm670 global clocks
The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most of the new clocks, GDSCs, and resets already have reserved IDs but there are some resources that don't. Add the new clock from Snapdragon 670 and document the differences between the SoC parent clocks. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com
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@ -19,23 +19,17 @@ description: |
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properties:
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compatible:
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const: qcom,gcc-sdm845
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enum:
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- qcom,gcc-sdm670
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- qcom,gcc-sdm845
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source
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- description: PCIE 1 Pipe clock source
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minItems: 3
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maxItems: 5
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_0_pipe_clk
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- const: pcie_1_pipe_clk
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minItems: 3
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maxItems: 5
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power-domains:
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maxItems: 1
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@ -45,6 +39,45 @@ required:
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,gcc-sdm670
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then:
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properties:
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- if:
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properties:
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compatible:
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contains:
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const: qcom,gcc-sdm845
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then:
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properties:
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source
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- description: PCIE 1 Pipe clock source
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_0_pipe_clk
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- const: pcie_1_pipe_clk
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unevaluatedProperties: false
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@ -199,6 +199,7 @@
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
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#define GCC_LPASS_Q6_AXI_CLK 190
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#define GCC_LPASS_SWAY_CLK 191
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#define GPLL6 192
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/* GCC Resets */
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#define GCC_MMSS_BCR 0
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