net: dsa: mv88e6xxx: implement .port_set_policy for Amethyst
The 16-bit Port Policy CTL register from older chips is on 6393x changed to Port Policy MGMT CTL, which can access more data, but indirectly and via 8-bit registers. The original 16-bit value is divided into first two 8-bit register in the Port Policy MGMT CTL. We can therefore use the previous code to compute the mask and shift, and then - if 0 <= shift < 8, we access register 0 in Port Policy MGMT CTL - if 8 <= shift < 16, we access register 1 in Port Policy MGMT CTL There are in fact other possible policy settings for Amethyst which could be added here, but this can be done in the future. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Pavana Sharma <pavana.sharma@digi.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Marek Behún
David S. Miller
Родитель
de776d0d31
Коммит
6584b26020
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@ -4627,6 +4627,7 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = {
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.port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
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.port_max_speed_mode = mv88e6393x_port_max_speed_mode,
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.port_tag_remap = mv88e6390_port_tag_remap,
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.port_set_policy = mv88e6393x_port_set_policy,
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
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.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
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.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
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@ -1325,6 +1325,27 @@ int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
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/* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
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static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
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u16 pointer, u8 *data)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
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pointer);
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if (err)
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return err;
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err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
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®);
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if (err)
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return err;
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*data = reg;
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return 0;
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}
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static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
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u16 pointer, u8 data)
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{
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@ -1526,6 +1547,68 @@ int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
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/* Offset 0x0E: Policy Control Register */
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static int
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mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
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enum mv88e6xxx_policy_action action,
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u16 *mask, u16 *val, int *shift)
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{
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switch (mapping) {
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case MV88E6XXX_POLICY_MAPPING_DA:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_SA:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_VTU:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_ETYPE:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_PPPOE:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_VBAS:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_OPT82:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_UDP:
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*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
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*mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
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break;
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default:
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return -EOPNOTSUPP;
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}
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switch (action) {
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case MV88E6XXX_POLICY_ACTION_NORMAL:
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*val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
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break;
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case MV88E6XXX_POLICY_ACTION_MIRROR:
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*val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
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break;
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case MV88E6XXX_POLICY_ACTION_TRAP:
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*val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
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break;
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case MV88E6XXX_POLICY_ACTION_DISCARD:
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*val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_policy_mapping mapping,
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enum mv88e6xxx_policy_action action)
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@ -1534,59 +1617,10 @@ int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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int shift;
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int err;
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switch (mapping) {
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case MV88E6XXX_POLICY_MAPPING_DA:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_SA:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_VTU:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_ETYPE:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_PPPOE:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_VBAS:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_OPT82:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
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break;
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case MV88E6XXX_POLICY_MAPPING_UDP:
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shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
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mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
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break;
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default:
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return -EOPNOTSUPP;
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}
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switch (action) {
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case MV88E6XXX_POLICY_ACTION_NORMAL:
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val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
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break;
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case MV88E6XXX_POLICY_ACTION_MIRROR:
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val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
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break;
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case MV88E6XXX_POLICY_ACTION_TRAP:
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val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
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break;
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case MV88E6XXX_POLICY_ACTION_DISCARD:
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val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
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break;
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default:
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return -EOPNOTSUPP;
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}
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err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
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&val, &shift);
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if (err)
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return err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
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if (err)
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@ -1597,3 +1631,37 @@ int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
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}
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int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_policy_mapping mapping,
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enum mv88e6xxx_policy_action action)
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{
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u16 mask, val;
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int shift;
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int err;
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u16 ptr;
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u8 reg;
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err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
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&val, &shift);
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if (err)
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return err;
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/* The 16-bit Port Policy CTL register from older chips is on 6393x
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* changed to Port Policy MGMT CTL, which can access more data, but
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* indirectly. The original 16-bit value is divided into two 8-bit
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* registers.
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*/
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ptr = shift / 8;
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shift %= 8;
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mask >>= ptr * 8;
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err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
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if (err)
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return err;
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reg &= ~mask;
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reg |= (val << shift) & mask;
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return mv88e6393x_port_policy_write(chip, port, ptr, reg);
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}
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@ -386,6 +386,9 @@ int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
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int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_policy_mapping mapping,
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enum mv88e6xxx_policy_action action);
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int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_policy_mapping mapping,
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enum mv88e6xxx_policy_action action);
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int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
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u16 etype);
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int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
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