MIPS: ath79: Use local variables for clock rates
Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
Родитель
59a8c10b25
Коммит
6612a6885b
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@ -40,25 +40,34 @@ static struct clk ath79_uart_clk;
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static void __init ar71xx_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR71XX_BASE_FREQ;
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ref_rate = AR71XX_BASE_FREQ;
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pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * ath79_ref_clk.rate;
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freq = div * ref_rate;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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ath79_cpu_clk.rate = freq / div;
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cpu_rate = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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ddr_rate = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ahb_rate = cpu_rate / div;
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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@ -66,26 +75,35 @@ static void __init ar71xx_clocks_init(void)
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static void __init ar724x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR724X_BASE_FREQ;
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ref_rate = AR724X_BASE_FREQ;
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pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * ath79_ref_clk.rate;
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freq = div * ref_rate;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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freq *= div;
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ath79_cpu_clk.rate = freq;
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cpu_rate = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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ddr_rate = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ahb_rate = cpu_rate / div;
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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@ -93,23 +111,32 @@ static void __init ar724x_clocks_init(void)
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static void __init ar913x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ath79_ref_clk.rate = AR913X_BASE_FREQ;
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ref_rate = AR913X_BASE_FREQ;
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pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
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freq = div * ath79_ref_clk.rate;
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freq = div * ref_rate;
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ath79_cpu_clk.rate = freq;
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cpu_rate = freq;
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div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / div;
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ddr_rate = freq / div;
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div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
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ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
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ahb_rate = cpu_rate / div;
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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@ -117,6 +144,10 @@ static void __init ar913x_clocks_init(void)
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static void __init ar933x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 clock_ctrl;
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u32 cpu_config;
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u32 freq;
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@ -124,21 +155,21 @@ static void __init ar933x_clocks_init(void)
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t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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ath79_ref_clk.rate = (40 * 1000 * 1000);
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ref_rate = (40 * 1000 * 1000);
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else
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ath79_ref_clk.rate = (25 * 1000 * 1000);
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ref_rate = (25 * 1000 * 1000);
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clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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ath79_cpu_clk.rate = ath79_ref_clk.rate;
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ath79_ahb_clk.rate = ath79_ref_clk.rate;
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ath79_ddr_clk.rate = ath79_ref_clk.rate;
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cpu_rate = ref_rate;
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ahb_rate = ref_rate;
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ddr_rate = ref_rate;
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} else {
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cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = ath79_ref_clk.rate / t;
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freq = ref_rate / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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@ -153,17 +184,22 @@ static void __init ar933x_clocks_init(void)
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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ath79_cpu_clk.rate = freq / t;
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cpu_rate = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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ath79_ddr_clk.rate = freq / t;
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ddr_rate = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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ath79_ahb_clk.rate = freq / t;
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ahb_rate = freq / t;
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}
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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}
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@ -190,6 +226,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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static void __init ar934x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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@ -199,9 +239,9 @@ static void __init ar934x_clocks_init(void)
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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ath79_ref_clk.rate = 40 * 1000 * 1000;
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ref_rate = 40 * 1000 * 1000;
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else
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ath79_ref_clk.rate = 25 * 1000 * 1000;
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ref_rate = 25 * 1000 * 1000;
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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@ -227,7 +267,7 @@ static void __init ar934x_clocks_init(void)
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frac = 1 << 6;
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}
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cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
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cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
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@ -254,7 +294,7 @@ static void __init ar934x_clocks_init(void)
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frac = 1 << 10;
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}
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ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
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ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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@ -263,31 +303,36 @@ static void __init ar934x_clocks_init(void)
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AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
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ath79_cpu_clk.rate = ath79_ref_clk.rate;
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cpu_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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cpu_rate = cpu_pll / (postdiv + 1);
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else
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ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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cpu_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
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ath79_ddr_clk.rate = ath79_ref_clk.rate;
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ddr_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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ddr_rate = ddr_pll / (postdiv + 1);
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else
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ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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ddr_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
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ath79_ahb_clk.rate = ath79_ref_clk.rate;
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ahb_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ref_clk.rate;
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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@ -297,15 +342,19 @@ static void __init ar934x_clocks_init(void)
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
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ath79_ref_clk.rate = 40 * 1000 * 1000;
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ref_rate = 40 * 1000 * 1000;
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else
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ath79_ref_clk.rate = 25 * 1000 * 1000;
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ref_rate = 25 * 1000 * 1000;
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pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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@ -317,8 +366,8 @@ static void __init qca955x_clocks_init(void)
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frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
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@ -331,8 +380,8 @@ static void __init qca955x_clocks_init(void)
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frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
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@ -341,31 +390,36 @@ static void __init qca955x_clocks_init(void)
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QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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ath79_cpu_clk.rate = ath79_ref_clk.rate;
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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cpu_rate = ddr_pll / (postdiv + 1);
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else
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ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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cpu_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ath79_ddr_clk.rate = ath79_ref_clk.rate;
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ddr_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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ddr_rate = cpu_pll / (postdiv + 1);
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else
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ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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ddr_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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ath79_ahb_clk.rate = ath79_ref_clk.rate;
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ahb_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_ref_clk.rate = ref_rate;
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ath79_cpu_clk.rate = cpu_rate;
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ath79_ddr_clk.rate = ddr_rate;
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ath79_ahb_clk.rate = ahb_rate;
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ath79_wdt_clk.rate = ath79_ref_clk.rate;
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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Загрузка…
Ссылка в новой задаче