coresight: etm4x: Cleanup TRCSSPCICRn register accesses
This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-14-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Коммит
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@ -1842,7 +1842,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
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spin_lock(&drvdata->spinlock);
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spin_lock(&drvdata->spinlock);
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idx = config->ss_idx;
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idx = config->ss_idx;
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config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
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config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
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/* must clear bit 31 in related status register on programming */
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/* must clear bit 31 in related status register on programming */
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config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
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config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
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spin_unlock(&drvdata->spinlock);
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spin_unlock(&drvdata->spinlock);
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@ -218,6 +218,8 @@
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#define TRCSSCSRn_STATUS BIT(31)
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#define TRCSSCSRn_STATUS BIT(31)
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#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
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#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
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#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
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/*
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/*
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* System instructions to access ETM registers.
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* System instructions to access ETM registers.
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* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
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* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
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