ARM: dts: am43xx: add clkctrl nodes
Add clkctrl nodes for AM43xx SoC. These are going to be acting as replacement for part of the existing clock data and the existing clkctrl hooks under hwmod data. This patch also removes any obsolete clock nodes, and reroutes all users for these to use the new clkctrl clocks instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo
Tony Lindgren
Родитель
0537634f7e
Коммит
664ae1ab25
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@ -10,6 +10,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/am4.h>
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/ {
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compatible = "ti,am4372", "ti,am43";
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@ -998,7 +999,7 @@
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reg = <0x483a8000 0x8000>;
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syscon-phy-power = <&scm_conf 0x620>;
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clocks = <&usb_phy0_always_on_clk32k>,
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<&usb_otg_ss0_refclk960m>;
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<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
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clock-names = "wkupclk", "refclk";
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#phy-cells = <0>;
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status = "disabled";
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@ -1017,7 +1018,7 @@
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reg = <0x483e8000 0x8000>;
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syscon-phy-power = <&scm_conf 0x628>;
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clocks = <&usb_phy1_always_on_clk32k>,
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<&usb_otg_ss1_refclk960m>;
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<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
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clock-names = "wkupclk", "refclk";
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#phy-cells = <0>;
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status = "disabled";
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@ -1180,4 +1181,4 @@
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};
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};
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/include/ "am43xx-clocks.dtsi"
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#include "am43xx-clocks.dtsi"
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@ -985,7 +985,7 @@
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rx-num-evt = <32>;
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};
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&synctimer_32kclk {
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&mux_synctimer32k_ck {
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assigned-clocks = <&mux_synctimer32k_ck>;
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assigned-clock-parents = <&clkdiv32k_ick>;
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};
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@ -524,54 +524,6 @@
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reg = <0x4240>;
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};
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gpio0_dbclk: gpio0_dbclk@2b68 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&gpio0_dbclk_mux_ck>;
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ti,bit-shift = <8>;
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reg = <0x2b68>;
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};
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gpio1_dbclk: gpio1_dbclk@8c78 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ick>;
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ti,bit-shift = <8>;
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reg = <0x8c78>;
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};
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gpio2_dbclk: gpio2_dbclk@8c80 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ick>;
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ti,bit-shift = <8>;
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reg = <0x8c80>;
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};
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gpio3_dbclk: gpio3_dbclk@8c88 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ick>;
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ti,bit-shift = <8>;
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reg = <0x8c88>;
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};
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gpio4_dbclk: gpio4_dbclk@8c90 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ick>;
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ti,bit-shift = <8>;
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reg = <0x8c90>;
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};
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gpio5_dbclk: gpio5_dbclk@8c98 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ick>;
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ti,bit-shift = <8>;
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reg = <0x8c98>;
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};
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mmc_clk: mmc_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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@ -629,14 +581,6 @@
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reg = <0x4230>;
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};
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synctimer_32kclk: synctimer_32kclk@2a30 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&mux_synctimer32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x2a30>;
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};
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timer8_fck: timer8_fck@421c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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@ -763,110 +707,76 @@
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ti,bit-shift = <8>;
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reg = <0x2a48>;
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};
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};
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usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_clkdcoldo>;
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ti,bit-shift = <8>;
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reg = <0x8a60>;
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&prcm {
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l4_wkup_cm: l4_wkup_cm@2800 {
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compatible = "ti,omap4-cm";
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reg = <0x2800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2800 0x400>;
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l4_wkup_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0x34c>;
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#clock-cells = <2>;
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};
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};
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usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_clkdcoldo>;
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ti,bit-shift = <8>;
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reg = <0x8a68>;
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mpu_cm: mpu_cm@8300 {
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compatible = "ti,omap4-cm";
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reg = <0x8300 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8300 0x100>;
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mpu_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0x4>;
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#clock-cells = <2>;
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};
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};
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clkout1_osc_div_ck: clkout1_osc_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sys_clkin_ck>;
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ti,bit-shift = <20>;
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ti,max-div = <4>;
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reg = <0x4100>;
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gfx_l3_cm: gfx_l3_cm@8400 {
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compatible = "ti,omap4-cm";
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reg = <0x8400 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8400 0x100>;
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gfx_l3_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0x4>;
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#clock-cells = <2>;
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};
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};
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clkout1_src2_mux_ck: clkout1_src2_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
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<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
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<&dpll_mpu_m2_ck>;
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reg = <0x4100>;
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l4_rtc_cm: l4_rtc_cm@8500 {
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compatible = "ti,omap4-cm";
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reg = <0x8500 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8500 0x100>;
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l4_rtc_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0x4>;
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#clock-cells = <2>;
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};
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};
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clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout1_src2_mux_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <8>;
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reg = <0x4100>;
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};
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l4_per_cm: l4_per_cm@8800 {
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compatible = "ti,omap4-cm";
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reg = <0x8800 0xc00>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8800 0xc00>;
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clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout1_src2_pre_div_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <32>;
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ti,index-power-of-two;
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reg = <0x4100>;
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};
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clkout1_mux_ck: clkout1_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
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<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
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ti,bit-shift = <16>;
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reg = <0x4100>;
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};
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clkout1_ck: clkout1_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkout1_mux_ck>;
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ti,bit-shift = <23>;
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reg = <0x4100>;
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};
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clkout2_src_mux_ck: clkout2_src_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
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<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
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<&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
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reg = <0x4108>;
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};
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clkout2_pre_div_ck: clkout2_pre_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout2_src_mux_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <8>;
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reg = <0x4108>;
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};
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clkout2_post_div_ck: clkout2_post_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout2_pre_div_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <32>;
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ti,index-power-of-two;
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reg = <0x4108>;
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};
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clkout2_ck: clkout2_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkout2_post_div_ck>;
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ti,bit-shift = <16>;
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reg = <0x4108>;
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l4_per_clkctrl: clk@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0xb04>;
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#clock-cells = <2>;
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};
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};
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};
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