Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ALSA: AACI: fix timeout duration ALSA: AACI: fix timeout condition checking ARM: 6636/1: ep93xx: default multiplexed gpio ports to gpio mode ARM: 6637/1: Make the argument to virt_to_phys() "const volatile" ARM: twd: ensure timer reload is reprogrammed on entry to periodic mode ARM: 6635/2: Configure reference clock for Versatile Express timers ARM: versatile: name configuration options after actual board names ARM: realview: name configuration options after actual board names ARM: realview,vexpress: fix section mismatch warning for pen_release ARM: 6632/3: mmci: stop using the blockend interrupts
This commit is contained in:
Linus Torvalds
Коммит
6663050edd
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@ -50,6 +50,12 @@
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#define SCPCELLID2 0xFF8
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#define SCPCELLID3 0xFFC
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#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
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#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
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#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
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#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
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static inline void sysctl_soft_reset(void __iomem *base)
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{
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/* writing any value to SCSYSSTAT reg will reset system */
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@ -188,7 +188,7 @@
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* translation for translating DMA addresses. Use the driver
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* DMA support - see dma-mapping.h.
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*/
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static inline unsigned long virt_to_phys(void *x)
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static inline unsigned long virt_to_phys(const volatile void *x)
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{
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return __virt_to_phys((unsigned long)(x));
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}
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@ -36,6 +36,7 @@ static void twd_set_mode(enum clock_event_mode mode,
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/* timer load already set up */
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ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
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| TWD_TIMER_CONTROL_PERIODIC;
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__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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@ -81,7 +82,7 @@ int twd_timer_ack(void)
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static void __cpuinit twd_calibrate_rate(void)
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{
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unsigned long load, count;
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unsigned long count;
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u64 waitjiffies;
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/*
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@ -116,10 +117,6 @@ static void __cpuinit twd_calibrate_rate(void)
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printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
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(twd_timer_rate / 1000000) % 100);
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}
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load = twd_timer_rate / HZ;
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__raw_writel(load, twd_base + TWD_TIMER_LOAD);
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}
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/*
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@ -427,6 +427,13 @@ void __init ep93xx_gpio_init(void)
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{
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int i;
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/* Set Ports C, D, E, G, and H for GPIO use */
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ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
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EP93XX_SYSCON_DEVCFG_GONK |
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EP93XX_SYSCON_DEVCFG_EONIDE |
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EP93XX_SYSCON_DEVCFG_GONIDE |
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EP93XX_SYSCON_DEVCFG_HONIDE);
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
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gpiochip_add(&ep93xx_gpio_banks[i].chip);
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}
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@ -2,52 +2,56 @@ menu "RealView platform type"
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depends on ARCH_REALVIEW
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config MACH_REALVIEW_EB
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bool "Support RealView/EB platform"
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bool "Support RealView(R) Emulation Baseboard"
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select ARM_GIC
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help
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Include support for the ARM(R) RealView Emulation Baseboard platform.
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Include support for the ARM(R) RealView(R) Emulation Baseboard
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platform.
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config REALVIEW_EB_A9MP
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bool "Support Multicore Cortex-A9"
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bool "Support Multicore Cortex-A9 Tile"
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depends on MACH_REALVIEW_EB
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select CPU_V7
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help
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Enable support for the Cortex-A9MPCore tile on the Realview platform.
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Enable support for the Cortex-A9MPCore tile fitted to the
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Realview(R) Emulation Baseboard platform.
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config REALVIEW_EB_ARM11MP
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bool "Support ARM11MPCore tile"
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bool "Support ARM11MPCore Tile"
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depends on MACH_REALVIEW_EB
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select CPU_V6
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select ARCH_HAS_BARRIERS if SMP
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help
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Enable support for the ARM11MPCore tile on the Realview platform.
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Enable support for the ARM11MPCore tile fitted to the Realview(R)
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Emulation Baseboard platform.
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config REALVIEW_EB_ARM11MP_REVB
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bool "Support ARM11MPCore RevB tile"
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bool "Support ARM11MPCore RevB Tile"
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depends on REALVIEW_EB_ARM11MP
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help
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Enable support for the ARM11MPCore RevB tile on the Realview
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platform. Since there are device address differences, a
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kernel built with this option enabled is not compatible with
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other revisions of the ARM11MPCore tile.
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Enable support for the ARM11MPCore Revision B tile on the
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Realview(R) Emulation Baseboard platform. Since there are device
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address differences, a kernel built with this option enabled is
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not compatible with other revisions of the ARM11MPCore tile.
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config MACH_REALVIEW_PB11MP
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bool "Support RealView/PB11MPCore platform"
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bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
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select CPU_V6
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select ARM_GIC
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select HAVE_PATA_PLATFORM
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select ARCH_HAS_BARRIERS if SMP
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help
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Include support for the ARM(R) RealView MPCore Platform Baseboard.
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PB11MPCore is a platform with an on-board ARM11MPCore and has
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Include support for the ARM(R) RealView(R) Platform Baseboard for
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the ARM11MPCore. This platform has an on-board ARM11MPCore and has
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support for PCI-E and Compact Flash.
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config MACH_REALVIEW_PB1176
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bool "Support RealView/PB1176 platform"
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bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
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select CPU_V6
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select ARM_GIC
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help
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Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
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Include support for the ARM(R) RealView(R) Platform Baseboard for
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ARM1176JZF-S.
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config REALVIEW_PB1176_SECURE_FLASH
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bool "Allow access to the secure flash memory block"
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@ -59,23 +63,24 @@ config REALVIEW_PB1176_SECURE_FLASH
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block (64MB @ 0x3c000000) is required.
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config MACH_REALVIEW_PBA8
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bool "Support RealView/PB-A8 platform"
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bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
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select CPU_V7
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select ARM_GIC
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select HAVE_PATA_PLATFORM
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help
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Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard.
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PB-A8 is a platform with an on-board Cortex-A8 and has support for
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PCI-E and Compact Flash.
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Include support for the ARM(R) RealView Platform Baseboard for
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Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
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support for PCI-E and Compact Flash.
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config MACH_REALVIEW_PBX
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bool "Support RealView/PBX platform"
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bool "Support RealView(R) Platform Baseboard Explore"
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select ARM_GIC
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select HAVE_PATA_PLATFORM
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select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
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select ZONE_DMA if SPARSEMEM
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help
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Include support for the ARM(R) RealView PBX platform.
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Include support for the ARM(R) RealView(R) Platform Baseboard
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Explore.
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config REALVIEW_HIGH_PHYS_OFFSET
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bool "High physical base address for the RealView platform"
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@ -41,7 +41,7 @@ volatile int __cpuinitdata pen_release = -1;
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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@ -2,17 +2,19 @@ menu "Versatile platform type"
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depends on ARCH_VERSATILE
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config ARCH_VERSATILE_PB
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bool "Support Versatile/PB platform"
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bool "Support Versatile Platform Baseboard for ARM926EJ-S"
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select CPU_ARM926T
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select MIGHT_HAVE_PCI
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default y
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help
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Include support for the ARM(R) Versatile/PB platform.
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Include support for the ARM(R) Versatile Platform Baseboard
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for the ARM926EJ-S.
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config MACH_VERSATILE_AB
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bool "Support Versatile/AB platform"
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bool "Support Versatile Application Baseboard for ARM926EJ-S"
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select CPU_ARM926T
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help
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Include support for the ARM(R) Versatile/AP platform.
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Include support for the ARM(R) Versatile Application Baseboard
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for the ARM926EJ-S.
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endmenu
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@ -39,7 +39,7 @@ volatile int __cpuinitdata pen_release = -1;
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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|
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@ -19,6 +19,7 @@
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#include <asm/mach/time.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/sp810.h>
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#include <mach/motherboard.h>
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@ -50,8 +51,16 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
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static void __init v2m_timer_init(void)
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{
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u32 scctrl;
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versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
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/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
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scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
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scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
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scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
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writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
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writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
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writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
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|
|
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|
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@ -46,10 +46,6 @@ static unsigned int fmax = 515633;
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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* @broken_blockend: the MCI_DATABLOCKEND is broken on the hardware
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* and will not work at all.
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* @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware when
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* using DMA.
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* @sdio: variant supports SDIO
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* @st_clkdiv: true if using a ST-specific clock divider algorithm
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*/
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@ -59,8 +55,6 @@ struct variant_data {
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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bool broken_blockend;
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bool broken_blockend_dma;
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bool sdio;
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bool st_clkdiv;
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};
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|
|
@ -76,7 +70,6 @@ static struct variant_data variant_u300 = {
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.fifohalfsize = 8 * 4,
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.clkreg_enable = 1 << 13, /* HWFCEN */
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.datalength_bits = 16,
|
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.broken_blockend_dma = true,
|
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.sdio = true,
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};
|
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|
||||
|
|
@ -86,7 +79,6 @@ static struct variant_data variant_ux500 = {
|
|||
.clkreg = MCI_CLK_ENABLE,
|
||||
.clkreg_enable = 1 << 14, /* HWFCEN */
|
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.datalength_bits = 24,
|
||||
.broken_blockend = true,
|
||||
.sdio = true,
|
||||
.st_clkdiv = true,
|
||||
};
|
||||
|
|
@ -210,8 +202,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
|
|||
host->data = data;
|
||||
host->size = data->blksz * data->blocks;
|
||||
host->data_xfered = 0;
|
||||
host->blockend = false;
|
||||
host->dataend = false;
|
||||
|
||||
mmci_init_sg(host, data);
|
||||
|
||||
|
|
@ -288,21 +278,26 @@ static void
|
|||
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
|
||||
unsigned int status)
|
||||
{
|
||||
struct variant_data *variant = host->variant;
|
||||
|
||||
/* First check for errors */
|
||||
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
|
||||
dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
|
||||
if (status & MCI_DATACRCFAIL)
|
||||
data->error = -EILSEQ;
|
||||
else if (status & MCI_DATATIMEOUT)
|
||||
data->error = -ETIMEDOUT;
|
||||
else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
|
||||
data->error = -EIO;
|
||||
u32 remain, success;
|
||||
|
||||
/* Force-complete the transaction */
|
||||
host->blockend = true;
|
||||
host->dataend = true;
|
||||
/* Calculate how far we are into the transfer */
|
||||
remain = readl(host->base + MMCIDATACNT) << 2;
|
||||
success = data->blksz * data->blocks - remain;
|
||||
|
||||
dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
|
||||
if (status & MCI_DATACRCFAIL) {
|
||||
/* Last block was not successful */
|
||||
host->data_xfered = ((success / data->blksz) - 1 * data->blksz);
|
||||
data->error = -EILSEQ;
|
||||
} else if (status & MCI_DATATIMEOUT) {
|
||||
host->data_xfered = success;
|
||||
data->error = -ETIMEDOUT;
|
||||
} else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
|
||||
host->data_xfered = success;
|
||||
data->error = -EIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* We hit an error condition. Ensure that any data
|
||||
|
|
@ -321,61 +316,14 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* On ARM variants in PIO mode, MCI_DATABLOCKEND
|
||||
* is always sent first, and we increase the
|
||||
* transfered number of bytes for that IRQ. Then
|
||||
* MCI_DATAEND follows and we conclude the transaction.
|
||||
*
|
||||
* On the Ux500 single-IRQ variant MCI_DATABLOCKEND
|
||||
* doesn't seem to immediately clear from the status,
|
||||
* so we can't use it keep count when only one irq is
|
||||
* used because the irq will hit for other reasons, and
|
||||
* then the flag is still up. So we use the MCI_DATAEND
|
||||
* IRQ at the end of the entire transfer because
|
||||
* MCI_DATABLOCKEND is broken.
|
||||
*
|
||||
* In the U300, the IRQs can arrive out-of-order,
|
||||
* e.g. MCI_DATABLOCKEND sometimes arrives after MCI_DATAEND,
|
||||
* so for this case we use the flags "blockend" and
|
||||
* "dataend" to make sure both IRQs have arrived before
|
||||
* concluding the transaction. (This does not apply
|
||||
* to the Ux500 which doesn't fire MCI_DATABLOCKEND
|
||||
* at all.) In DMA mode it suffers from the same problem
|
||||
* as the Ux500.
|
||||
*/
|
||||
if (status & MCI_DATABLOCKEND) {
|
||||
/*
|
||||
* Just being a little over-cautious, we do not
|
||||
* use this progressive update if the hardware blockend
|
||||
* flag is unreliable: since it can stay high between
|
||||
* IRQs it will corrupt the transfer counter.
|
||||
*/
|
||||
if (!variant->broken_blockend)
|
||||
host->data_xfered += data->blksz;
|
||||
host->blockend = true;
|
||||
}
|
||||
if (status & MCI_DATABLOCKEND)
|
||||
dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
|
||||
|
||||
if (status & MCI_DATAEND)
|
||||
host->dataend = true;
|
||||
|
||||
/*
|
||||
* On variants with broken blockend we shall only wait for dataend,
|
||||
* on others we must sync with the blockend signal since they can
|
||||
* appear out-of-order.
|
||||
*/
|
||||
if (host->dataend && (host->blockend || variant->broken_blockend)) {
|
||||
if (status & MCI_DATAEND) {
|
||||
mmci_stop_data(host);
|
||||
|
||||
/* Reset these flags */
|
||||
host->blockend = false;
|
||||
host->dataend = false;
|
||||
|
||||
/*
|
||||
* Variants with broken blockend flags need to handle the
|
||||
* end of the entire transfer here.
|
||||
*/
|
||||
if (variant->broken_blockend && !data->error)
|
||||
if (!data->error)
|
||||
/* The error clause is handled above, success! */
|
||||
host->data_xfered += data->blksz * data->blocks;
|
||||
|
||||
if (!data->stop) {
|
||||
|
|
@ -770,7 +718,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
|||
struct variant_data *variant = id->data;
|
||||
struct mmci_host *host;
|
||||
struct mmc_host *mmc;
|
||||
unsigned int mask;
|
||||
int ret;
|
||||
|
||||
/* must have platform data */
|
||||
|
|
@ -951,12 +898,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
|||
goto irq0_free;
|
||||
}
|
||||
|
||||
mask = MCI_IRQENABLE;
|
||||
/* Don't use the datablockend flag if it's broken */
|
||||
if (variant->broken_blockend)
|
||||
mask &= ~MCI_DATABLOCKEND;
|
||||
|
||||
writel(mask, host->base + MMCIMASK0);
|
||||
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
||||
|
||||
amba_set_drvdata(dev, mmc);
|
||||
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@
|
|||
#define MCI_IRQENABLE \
|
||||
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
|
||||
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
|
||||
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
|
||||
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK)
|
||||
|
||||
/* These interrupts are directed to IRQ1 when two IRQ lines are available */
|
||||
#define MCI_IRQ1MASK \
|
||||
|
|
@ -177,9 +177,6 @@ struct mmci_host {
|
|||
struct timer_list timer;
|
||||
unsigned int oldstat;
|
||||
|
||||
bool blockend;
|
||||
bool dataend;
|
||||
|
||||
/* pio stuff */
|
||||
struct sg_mapping_iter sg_miter;
|
||||
unsigned int size;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
|
||||
#define DRIVER_NAME "aaci-pl041"
|
||||
|
||||
#define FRAME_PERIOD_US 21
|
||||
|
||||
/*
|
||||
* PM support is not complete. Turn it off.
|
||||
*/
|
||||
|
|
@ -64,8 +66,8 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|||
unsigned short val)
|
||||
{
|
||||
struct aaci *aaci = ac97->private_data;
|
||||
int timeout;
|
||||
u32 v;
|
||||
int timeout = 5000;
|
||||
|
||||
if (ac97->num >= 4)
|
||||
return;
|
||||
|
|
@ -81,14 +83,17 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|||
writel(val << 4, aaci->base + AACI_SL2TX);
|
||||
writel(reg << 12, aaci->base + AACI_SL1TX);
|
||||
|
||||
/*
|
||||
* Wait for the transmission of both slots to complete.
|
||||
*/
|
||||
/* Initially, wait one frame period */
|
||||
udelay(FRAME_PERIOD_US);
|
||||
|
||||
/* And then wait an additional eight frame periods for it to be sent */
|
||||
timeout = FRAME_PERIOD_US * 8;
|
||||
do {
|
||||
udelay(1);
|
||||
v = readl(aaci->base + AACI_SLFR);
|
||||
} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
|
||||
|
||||
if (!timeout)
|
||||
if (v & (SLFR_1TXB|SLFR_2TXB))
|
||||
dev_err(&aaci->dev->dev,
|
||||
"timeout waiting for write to complete\n");
|
||||
|
||||
|
|
@ -101,9 +106,8 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|||
static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
|
||||
{
|
||||
struct aaci *aaci = ac97->private_data;
|
||||
int timeout, retries = 10;
|
||||
u32 v;
|
||||
int timeout = 5000;
|
||||
int retries = 10;
|
||||
|
||||
if (ac97->num >= 4)
|
||||
return ~0;
|
||||
|
|
@ -117,35 +121,34 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
|
|||
*/
|
||||
writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
|
||||
|
||||
/*
|
||||
* Wait for the transmission to complete.
|
||||
*/
|
||||
/* Initially, wait one frame period */
|
||||
udelay(FRAME_PERIOD_US);
|
||||
|
||||
/* And then wait an additional eight frame periods for it to be sent */
|
||||
timeout = FRAME_PERIOD_US * 8;
|
||||
do {
|
||||
udelay(1);
|
||||
v = readl(aaci->base + AACI_SLFR);
|
||||
} while ((v & SLFR_1TXB) && --timeout);
|
||||
|
||||
if (!timeout) {
|
||||
if (v & SLFR_1TXB) {
|
||||
dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
|
||||
v = ~0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Give the AC'97 codec more than enough time
|
||||
* to respond. (42us = ~2 frames at 48kHz.)
|
||||
*/
|
||||
udelay(42);
|
||||
/* Now wait for the response frame */
|
||||
udelay(FRAME_PERIOD_US);
|
||||
|
||||
/*
|
||||
* Wait for slot 2 to indicate data.
|
||||
*/
|
||||
timeout = 5000;
|
||||
/* And then wait an additional eight frame periods for data */
|
||||
timeout = FRAME_PERIOD_US * 8;
|
||||
do {
|
||||
udelay(1);
|
||||
cond_resched();
|
||||
v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
|
||||
} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
|
||||
|
||||
if (!timeout) {
|
||||
if (v != (SLFR_1RXV|SLFR_2RXV)) {
|
||||
dev_err(&aaci->dev->dev, "timeout on RX valid\n");
|
||||
v = ~0;
|
||||
goto out;
|
||||
|
|
@ -179,6 +182,7 @@ aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask)
|
|||
int timeout = 5000;
|
||||
|
||||
do {
|
||||
udelay(1);
|
||||
val = readl(aacirun->base + AACI_SR);
|
||||
} while (val & mask && timeout--);
|
||||
}
|
||||
|
|
@ -874,7 +878,7 @@ static int __devinit aaci_probe_ac97(struct aaci *aaci)
|
|||
* Give the AC'97 codec more than enough time
|
||||
* to wake up. (42us = ~2 frames at 48kHz.)
|
||||
*/
|
||||
udelay(42);
|
||||
udelay(FRAME_PERIOD_US * 2);
|
||||
|
||||
ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
|
||||
if (ret)
|
||||
|
|
|
|||
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