ath9k_hw: Initialize interrupt mask for AR9003
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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55e82df4be
Коммит
668602404d
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@ -736,12 +736,24 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
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AR_IMR_RXORN |
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AR_IMR_BCNMISC;
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if (ah->config.rx_intr_mitigation)
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imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
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else
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imr_reg |= AR_IMR_RXOK;
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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imr_reg |= AR_IMR_RXOK_HP;
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if (ah->config.rx_intr_mitigation)
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imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
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else
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imr_reg |= AR_IMR_RXOK_LP;
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imr_reg |= AR_IMR_TXOK;
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} else {
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if (ah->config.rx_intr_mitigation)
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imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
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else
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imr_reg |= AR_IMR_RXOK;
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}
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if (ah->config.tx_intr_mitigation)
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imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
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else
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imr_reg |= AR_IMR_TXOK;
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if (opmode == NL80211_IFTYPE_AP)
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imr_reg |= AR_IMR_MIB;
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@ -755,6 +767,13 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
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REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
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}
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
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REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
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REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
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REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
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}
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}
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static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
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@ -1042,6 +1042,11 @@ enum {
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#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
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#define AR_PCIE_MSI_ENABLE 0x00000001
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#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
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#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
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#define AR_INTR_PRIO_SYNC_MASK 0x40cc
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#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
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#define AR_RTC_9300_PLL_DIV 0x000003ff
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#define AR_RTC_9300_PLL_DIV_S 0
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#define AR_RTC_9300_PLL_REFDIV 0x00003C00
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