clk: ux500: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd
Родитель
45e21151a2
Коммит
66f4ae777d
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@ -40,8 +40,7 @@ static int ab8500_reg_clks(struct device *dev)
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return ret;
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/* ab8500_sysclk */
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clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
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clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
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clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
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clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
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@ -68,7 +67,7 @@ static int ab8500_reg_clks(struct device *dev)
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clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
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AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
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38400000, 9000, CLK_IS_ROOT);
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38400000, 9000, 0);
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clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0");
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/* ab8500_intclk */
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@ -91,21 +91,21 @@ void u8500_clk_init(void)
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/* Clock sources */
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clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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prcmu_clk[PRCMU_PLLSOC0] = clk;
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clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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prcmu_clk[PRCMU_PLLSOC1] = clk;
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clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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prcmu_clk[PRCMU_PLLDDR] = clk;
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/* FIXME: Add sys, ulp and int clocks here. */
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rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
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CLK_IS_ROOT|CLK_IGNORE_UNUSED,
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CLK_IGNORE_UNUSED,
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32768);
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/* PRCMU clocks */
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@ -126,105 +126,101 @@ void u8500_clk_init(void)
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clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
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PRCMU_SGACLK, 0);
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else
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clk = clk_reg_prcmu_gate("sgclk", NULL,
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PRCMU_SGACLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
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prcmu_clk[PRCMU_SGACLK] = clk;
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clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
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prcmu_clk[PRCMU_UARTCLK] = clk;
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clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
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prcmu_clk[PRCMU_MSP02CLK] = clk;
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clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
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prcmu_clk[PRCMU_MSP1CLK] = clk;
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clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
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prcmu_clk[PRCMU_I2CCLK] = clk;
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clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
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prcmu_clk[PRCMU_SLIMCLK] = clk;
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clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
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prcmu_clk[PRCMU_PER1CLK] = clk;
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clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
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prcmu_clk[PRCMU_PER2CLK] = clk;
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clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
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prcmu_clk[PRCMU_PER3CLK] = clk;
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clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
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prcmu_clk[PRCMU_PER5CLK] = clk;
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clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
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prcmu_clk[PRCMU_PER6CLK] = clk;
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clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
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prcmu_clk[PRCMU_PER7CLK] = clk;
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clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_LCDCLK] = clk;
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clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
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prcmu_clk[PRCMU_BMLCLK] = clk;
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clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_HSITXCLK] = clk;
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clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_HSIRXCLK] = clk;
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clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_HDMICLK] = clk;
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clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
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prcmu_clk[PRCMU_APEATCLK] = clk;
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clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_APETRACECLK] = clk;
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clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
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prcmu_clk[PRCMU_MCDECLK] = clk;
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clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
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prcmu_clk[PRCMU_IPI2CCLK] = clk;
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clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
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prcmu_clk[PRCMU_DSIALTCLK] = clk;
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clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
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prcmu_clk[PRCMU_DMACLK] = clk;
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clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
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prcmu_clk[PRCMU_B2R2CLK] = clk;
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clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_TVCLK] = clk;
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clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
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prcmu_clk[PRCMU_SSPCLK] = clk;
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clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
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prcmu_clk[PRCMU_RNGCLK] = clk;
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clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
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prcmu_clk[PRCMU_UICCCLK] = clk;
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clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
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prcmu_clk[PRCMU_TIMCLK] = clk;
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clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
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100000000,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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100000000, CLK_SET_RATE_GATE);
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prcmu_clk[PRCMU_SDMMCCLK] = clk;
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clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
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@ -252,7 +248,7 @@ void u8500_clk_init(void)
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prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
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clk = clk_reg_prcmu_scalable_rate("armss", NULL,
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PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
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prcmu_clk[PRCMU_ARMSS] = clk;
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twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
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@ -56,28 +56,28 @@ void u8540_clk_init(void)
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/* Clock sources. */
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/* Fixed ClockGen */
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clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "soc0_pll", NULL);
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clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "soc1_pll", NULL);
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clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "ddr_pll", NULL);
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clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED,
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CLK_IGNORE_UNUSED,
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32768);
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clk_register_clkdev(clk, "clk32k", NULL);
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clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
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clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED,
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CLK_IGNORE_UNUSED,
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38400000);
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clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
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clk_register_clkdev(clk, NULL, "UART");
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/* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
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@ -85,120 +85,116 @@ void u8540_clk_init(void)
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PRCMU_MSP02CLK, 0);
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clk_register_clkdev(clk, NULL, "MSP02");
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clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
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clk_register_clkdev(clk, NULL, "MSP1");
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clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
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clk_register_clkdev(clk, NULL, "I2C");
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clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
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clk_register_clkdev(clk, NULL, "slim");
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clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH1");
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clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH2");
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clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH3");
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clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH5");
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clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH6");
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clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
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clk_register_clkdev(clk, NULL, "PERIPH7");
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clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "lcd");
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clk_register_clkdev(clk, "lcd", "mcde");
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clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
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clk_register_clkdev(clk, NULL, "bml");
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clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "hdmi");
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clk_register_clkdev(clk, "hdmi", "mcde");
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clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
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clk_register_clkdev(clk, NULL, "apeat");
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clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 0);
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clk_register_clkdev(clk, NULL, "apetrace");
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clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
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clk_register_clkdev(clk, NULL, "mcde");
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clk_register_clkdev(clk, "mcde", "mcde");
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clk_register_clkdev(clk, NULL, "dsilink.0");
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clk_register_clkdev(clk, NULL, "dsilink.1");
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clk_register_clkdev(clk, NULL, "dsilink.2");
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clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
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clk_register_clkdev(clk, NULL, "ipi2");
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clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
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CLK_IS_ROOT);
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clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
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clk_register_clkdev(clk, NULL, "dsialt");
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|
||||
clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "dma40.0");
|
||||
|
||||
clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "b2r2");
|
||||
clk_register_clkdev(clk, NULL, "b2r2_core");
|
||||
clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
|
||||
clk_register_clkdev(clk, NULL, "b2r2_1_core");
|
||||
|
||||
clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
|
||||
CLK_IS_ROOT|CLK_SET_RATE_GATE);
|
||||
CLK_SET_RATE_GATE);
|
||||
clk_register_clkdev(clk, NULL, "tv");
|
||||
clk_register_clkdev(clk, "tv", "mcde");
|
||||
|
||||
clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "SSP");
|
||||
|
||||
clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "rngclk");
|
||||
|
||||
clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "uicc");
|
||||
|
||||
clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "mtu0");
|
||||
clk_register_clkdev(clk, NULL, "mtu1");
|
||||
|
||||
clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
|
||||
PRCMU_SDMMCCLK, 100000000,
|
||||
CLK_IS_ROOT|CLK_SET_RATE_GATE);
|
||||
CLK_SET_RATE_GATE);
|
||||
clk_register_clkdev(clk, NULL, "sdmmc");
|
||||
|
||||
clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
|
||||
PRCMU_SDMMCHCLK, 400000000,
|
||||
CLK_IS_ROOT|CLK_SET_RATE_GATE);
|
||||
CLK_SET_RATE_GATE);
|
||||
clk_register_clkdev(clk, NULL, "sdmmchclk");
|
||||
|
||||
clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "hva");
|
||||
|
||||
clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT);
|
||||
clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, 0);
|
||||
clk_register_clkdev(clk, NULL, "g1");
|
||||
|
||||
clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
|
||||
CLK_IS_ROOT|CLK_SET_RATE_GATE);
|
||||
CLK_SET_RATE_GATE);
|
||||
clk_register_clkdev(clk, "dsilcd", "mcde");
|
||||
|
||||
clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
|
||||
|
|
@ -244,7 +240,7 @@ void u8540_clk_init(void)
|
|||
clk_register_clkdev(clk, "dsilp2", "mcde");
|
||||
|
||||
clk = clk_reg_prcmu_scalable_rate("armss", NULL,
|
||||
PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
|
||||
PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
|
||||
clk_register_clkdev(clk, "armss", NULL);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
|
||||
|
|
|
|||
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