Some new clock ids for rk3188 and rk3368 as well as removal of a
superfluous memory allocation error message. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlnmPGsQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgYO7CACCYT7nEtwfQd4ajxUp9CoMYqBUEuZYv1xR NWbaK99eF2gNLZwUIkY3Y1C/YV8SA14gfeD2zmqbBe+f7MNqyUvi8VtEzidyHj0d JpIGjD1Gqy/A/Qli2RN76rPyQc9hW7KgFGIFSOEdKwmmkf6gQcb66tlG9qFfmAka Gfx7+5E226NGOtG6vjGtfW6lsrxpgpffsyOZiAK0MWLSF6y2tvxkO8kA4/elWhfc +fRYuBxjxZ74O2zJvIFMNC7L9S3fflPJ1+LRs+PSZwUgTwd7+bQlSXxh3ktc/9uf v57UmlDcRLABdL126tEK4oQLCXwIDy+LGx/2XCr791HRyQDcXo3q =0pyD -----END PGP SIGNATURE----- Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk drivers updates from Heiko Stuebner: - new clock ids for rk3188 and rk3368 - removal of a superfluous memory allocation error message * tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: use new cif/vdpu clock ids on rk3188 clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs clk: rockchip: add more rk3188 graphics clock ids clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()
This commit is contained in:
Stephen Boyd
Коммит
6705fc9441
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@ -322,8 +322,6 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
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sizeof(*rates) * nrates,
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GFP_KERNEL);
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if (!cpuclk->rate_table) {
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pr_err("%s: could not allocate memory for cpuclk rates\n",
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__func__);
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ret = -ENOMEM;
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goto unregister_notifier;
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}
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@ -290,15 +290,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
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div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
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COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
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COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
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RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 9, GFLAGS),
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GATE(0, "hclk_vepu", "aclk_vepu", 0,
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GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
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RK2928_CLKGATE_CON(3), 10, GFLAGS),
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COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
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COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
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RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 11, GFLAGS),
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GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
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GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
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RK2928_CLKGATE_CON(3), 12, GFLAGS),
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GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
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@ -644,13 +644,13 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
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GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
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GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
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GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
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GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
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GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
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GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(5), 14, GFLAGS),
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GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
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GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
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GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
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GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
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@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
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GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
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GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
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GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
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GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
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GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
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/*
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@ -68,12 +68,14 @@
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#define ACLK_LCDC1 196
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#define ACLK_GPU 197
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#define ACLK_SMC 198
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#define ACLK_CIF 199
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#define ACLK_CIF1 199
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#define ACLK_IPP 200
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#define ACLK_RGA 201
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#define ACLK_CIF0 202
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#define ACLK_CPU 203
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#define ACLK_PERI 204
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#define ACLK_VEPU 205
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#define ACLK_VDPU 206
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/* pclk gates */
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#define PCLK_GRF 320
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@ -134,8 +136,11 @@
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#define HCLK_NANDC0 467
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#define HCLK_CPU 468
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#define HCLK_PERI 469
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#define HCLK_CIF1 470
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#define HCLK_VEPU 471
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#define HCLK_VDPU 472
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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#define CLK_NR_CLKS (HCLK_VDPU + 1)
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/* soft-reset indices */
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#define SRST_MCORE 2
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@ -156,6 +156,7 @@
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#define PCLK_ISP 366
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#define PCLK_VIP 367
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#define PCLK_WDT 368
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#define PCLK_EFUSE256 369
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/* hclk gates */
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#define HCLK_SFC 448
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