i7core_edac: add support for more than one MC socket
Some Nehalem architectures have more than one MC socket. Socket 0 is located at bus 255. Currently, it is using up to 2 sockets, but increasing it to a larger number is just a matter of increasing MAX_SOCKETS definition. This seems to be required for properly support of Xeon 55xx. Still needs testing with Xeon 55xx. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
Родитель
d1fd4fb69e
Коммит
67166af4ab
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@ -155,6 +155,7 @@
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#define NUM_CHANS 3
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#define MAX_DIMMS 3 /* Max DIMMS per channel */
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#define NUM_SOCKETS 2 /* Max number of MC sockets */
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#define MAX_MCR_FUNC 4
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#define MAX_CHAN_FUNC 3
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@ -169,6 +170,7 @@ struct i7core_info {
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struct i7core_inject {
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int enable;
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u8 socket;
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u32 section;
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u32 type;
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u32 eccmask;
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@ -186,21 +188,25 @@ struct pci_id_descr {
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int dev;
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int func;
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int dev_id;
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struct pci_dev *pdev;
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struct pci_dev *pdev[NUM_SOCKETS];
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};
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struct i7core_pvt {
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struct pci_dev *pci_noncore;
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struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
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struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
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struct pci_dev *pci_noncore[NUM_SOCKETS];
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struct pci_dev *pci_mcr[NUM_SOCKETS][MAX_MCR_FUNC + 1];
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struct pci_dev *pci_ch[NUM_SOCKETS][NUM_CHANS][MAX_CHAN_FUNC + 1];
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struct i7core_info info;
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struct i7core_inject inject;
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struct i7core_channel channel[NUM_CHANS];
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struct i7core_channel channel[NUM_SOCKETS][NUM_CHANS];
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int sockets; /* Number of sockets */
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int channels; /* Number of active channels */
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int ce_count_available;
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unsigned long ce_count[MAX_DIMMS]; /* ECC corrected errors counts per dimm */
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int last_ce_count[MAX_DIMMS];
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int ce_count_available[NUM_SOCKETS];
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/* ECC corrected errors counts per dimm */
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unsigned long ce_count[NUM_SOCKETS][MAX_DIMMS];
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int last_ce_count[NUM_SOCKETS][MAX_DIMMS];
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/* mcelog glue */
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struct edac_mce edac_mce;
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@ -324,24 +330,26 @@ static inline int numcol(u32 col)
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/****************************************************************************
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Memory check routines
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****************************************************************************/
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static struct pci_dev *get_pdev_slot_func(int slot, int func)
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static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
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unsigned func)
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{
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int i;
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for (i = 0; i < N_DEVS; i++) {
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if (!pci_devs[i].pdev)
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if (!pci_devs[i].pdev[socket])
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continue;
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if (PCI_SLOT(pci_devs[i].pdev->devfn) == slot &&
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PCI_FUNC(pci_devs[i].pdev->devfn) == func) {
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return pci_devs[i].pdev;
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if (PCI_SLOT(pci_devs[i].pdev[socket]->devfn) == slot &&
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PCI_FUNC(pci_devs[i].pdev[socket]->devfn) == func) {
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return pci_devs[i].pdev[socket];
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}
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}
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return NULL;
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}
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static int i7core_get_active_channels(int *channels, int *csrows)
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static int i7core_get_active_channels(u8 socket, unsigned *channels,
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unsigned *csrows)
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{
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struct pci_dev *pdev = NULL;
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int i, j;
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@ -350,9 +358,10 @@ static int i7core_get_active_channels(int *channels, int *csrows)
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*channels = 0;
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*csrows = 0;
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pdev = get_pdev_slot_func(3, 0);
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pdev = get_pdev_slot_func(socket, 3, 0);
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if (!pdev) {
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i7core_printk(KERN_ERR, "Couldn't find fn 3.0!!!\n");
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i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
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socket);
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return -ENODEV;
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}
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@ -370,10 +379,11 @@ static int i7core_get_active_channels(int *channels, int *csrows)
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if (status & (1 << i))
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continue;
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pdev = get_pdev_slot_func(i + 4, 1);
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pdev = get_pdev_slot_func(socket, i + 4, 1);
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if (!pdev) {
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i7core_printk(KERN_ERR, "Couldn't find fn %d.%d!!!\n",
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i + 4, 1);
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i7core_printk(KERN_ERR, "Couldn't find socket %d "
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"fn %d.%d!!!\n",
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socket, i + 4, 1);
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return -ENODEV;
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}
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/* Devices 4-6 function 1 */
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@ -393,12 +403,13 @@ static int i7core_get_active_channels(int *channels, int *csrows)
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}
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}
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debugf0("Number of active channels: %d\n", *channels);
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debugf0("Number of active channels on socked %d: %d\n",
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socket, *channels);
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return 0;
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}
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static int get_dimm_config(struct mem_ctl_info *mci)
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static int get_dimm_config(struct mem_ctl_info *mci, u8 socket)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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struct csrow_info *csr;
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@ -409,7 +420,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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enum mem_type mtype;
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/* Get data from the MC register, function 0 */
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pdev = pvt->pci_mcr[0];
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pdev = pvt->pci_mcr[socket][0];
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if (!pdev)
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return -ENODEV;
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@ -458,10 +469,11 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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}
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/* Devices 4-6 function 0 */
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pci_read_config_dword(pvt->pci_ch[i][0],
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pci_read_config_dword(pvt->pci_ch[socket][i][0],
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MC_CHANNEL_DIMM_INIT_PARAMS, &data);
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pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? 4 : 2;
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pvt->channel[socket][i].ranks = (data & QUAD_RANK_PRESENT) ?
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4 : 2;
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if (data & REGISTERED_DIMM)
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mtype = MEM_RDDR3;
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@ -477,11 +489,11 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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#endif
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/* Devices 4-6 function 1 */
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pci_read_config_dword(pvt->pci_ch[i][1],
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pci_read_config_dword(pvt->pci_ch[socket][i][1],
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MC_DOD_CH_DIMM0, &dimm_dod[0]);
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pci_read_config_dword(pvt->pci_ch[i][1],
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pci_read_config_dword(pvt->pci_ch[socket][i][1],
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MC_DOD_CH_DIMM1, &dimm_dod[1]);
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pci_read_config_dword(pvt->pci_ch[i][1],
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pci_read_config_dword(pvt->pci_ch[socket][i][1],
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MC_DOD_CH_DIMM2, &dimm_dod[2]);
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debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
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@ -489,7 +501,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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i,
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RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
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data,
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pvt->channel[i].ranks,
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pvt->channel[socket][i].ranks,
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(data & REGISTERED_DIMM) ? 'R' : 'U');
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for (j = 0; j < 3; j++) {
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@ -507,7 +519,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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/* DDR3 has 8 I/O banks */
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size = (rows * cols * banks * ranks) >> (20 - 3);
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pvt->channel[i].dimms++;
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pvt->channel[socket][i].dimms++;
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debugf0("\tdimm %d (0x%08x) %d Mb offset: %x, "
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"numbank: %d,\n\t\t"
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@ -592,15 +604,42 @@ static int disable_inject(struct mem_ctl_info *mci)
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pvt->inject.enable = 0;
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if (!pvt->pci_ch[pvt->inject.channel][0])
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if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
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return -ENODEV;
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, 0);
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return 0;
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}
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/*
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* i7core inject inject.socket
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*
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* accept and store error injection inject.socket value
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*/
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static ssize_t i7core_inject_socket_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int rc;
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rc = strict_strtoul(data, 10, &value);
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if ((rc < 0) || (value > pvt->sockets))
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return 0;
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pvt->inject.section = (u32) value;
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return count;
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}
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static ssize_t i7core_inject_socket_show(struct mem_ctl_info *mci,
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char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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return sprintf(data, "%d\n", pvt->inject.socket);
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}
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/*
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* i7core inject inject.section
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*
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@ -838,7 +877,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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int rc;
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long enable;
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if (!pvt->pci_ch[pvt->inject.channel][0])
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if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
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return 0;
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rc = strict_strtoul(data, 10, &enable);
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@ -856,7 +895,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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if (pvt->inject.dimm < 0)
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mask |= 1L << 41;
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else {
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if (pvt->channel[pvt->inject.channel].dimms > 2)
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if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
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mask |= (pvt->inject.dimm & 0x3L) << 35;
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else
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mask |= (pvt->inject.dimm & 0x1L) << 36;
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@ -866,7 +905,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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if (pvt->inject.rank < 0)
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mask |= 1L << 40;
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else {
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if (pvt->channel[pvt->inject.channel].dimms > 2)
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if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
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mask |= (pvt->inject.rank & 0x1L) << 34;
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else
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mask |= (pvt->inject.rank & 0x3L) << 34;
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@ -891,38 +930,41 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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mask |= (pvt->inject.col & 0x3fffL);
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/* Unlock writes to registers */
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pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, 0x2);
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pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
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MC_CFG_CONTROL, 0x2);
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msleep(100);
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/* Zeroes error count registers */
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pci_write_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, 0);
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pci_write_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, 0);
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pvt->ce_count_available = 0;
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pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
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MC_TEST_ERR_RCV1, 0);
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pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
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MC_TEST_ERR_RCV0, 0);
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pvt->ce_count_available[pvt->inject.socket] = 0;
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#if USE_QWORD
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pci_write_config_qword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_qword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH, mask);
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#else
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH, mask);
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
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#endif
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#if 1
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#if USE_QWORD
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u64 rdmask;
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pci_read_config_qword(pvt->pci_ch[pvt->inject.channel][0],
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pci_read_config_qword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH, &rdmask);
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debugf0("Inject addr match write 0x%016llx, read: 0x%016llx\n",
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mask, rdmask);
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#else
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u32 rdmask1, rdmask2;
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pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH, &rdmask1);
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pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ADDR_MATCH + 4, &rdmask2);
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debugf0("Inject addr match write 0x%016llx, read: 0x%08x 0x%08x\n",
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@ -930,7 +972,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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#endif
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#endif
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
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/*
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@ -944,7 +986,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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(pvt->inject.section & 0x3) << 1 |
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(pvt->inject.type & 0x6) << (3 - 1);
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, injectmask);
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#if 0
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@ -965,7 +1007,7 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
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struct i7core_pvt *pvt = mci->pvt_info;
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u32 injectmask;
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pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, &injectmask);
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debugf0("Inject error read: 0x%018x\n", injectmask);
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@ -978,23 +1020,38 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
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static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
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{
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unsigned i, count, total = 0;
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struct i7core_pvt *pvt = mci->pvt_info;
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if (!pvt->ce_count_available)
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return sprintf(data, "unavailable\n");
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for (i = 0; i < pvt->sockets; i++) {
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if (!pvt->ce_count_available[i])
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count = sprintf(data, "socket 0 data unavailable\n");
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else
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count = sprintf(data, "socket %d, dimm0: %lu\n"
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"dimm1: %lu\ndimm2: %lu\n",
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i,
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pvt->ce_count[i][0],
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pvt->ce_count[i][1],
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pvt->ce_count[i][2]);
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data += count;
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total += count;
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}
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return sprintf(data, "dimm0: %lu\ndimm1: %lu\ndimm2: %lu\n",
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pvt->ce_count[0],
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pvt->ce_count[1],
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pvt->ce_count[2]);
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return total;
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}
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/*
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* Sysfs struct
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*/
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static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
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{
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.attr = {
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.name = "inject_socket",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_inject_socket_show,
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.store = i7core_inject_socket_store,
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}, {
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.attr = {
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.name = "inject_section",
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.mode = (S_IRUGO | S_IWUSR)
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@ -1049,10 +1106,11 @@ static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
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*/
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static void i7core_put_devices(void)
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{
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int i;
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int i, j;
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for (i = 0; i < N_DEVS; i++)
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pci_dev_put(pci_devs[i].pdev);
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for (i = 0; i < NUM_SOCKETS; i++)
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for (j = 0; j < N_DEVS; j++)
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pci_dev_put(pci_devs[j].pdev[i]);
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}
|
||||
|
||||
/*
|
||||
|
|
@ -1065,6 +1123,8 @@ static int i7core_get_devices(void)
|
|||
{
|
||||
int rc, i;
|
||||
struct pci_dev *pdev = NULL;
|
||||
u8 bus = 0;
|
||||
u8 socket = 0;
|
||||
|
||||
for (i = 0; i < N_DEVS; i++) {
|
||||
pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
|
|
@ -1078,14 +1138,32 @@ static int i7core_get_devices(void)
|
|||
pci_devs[i].dev_id, NULL);
|
||||
}
|
||||
|
||||
if (likely(pdev))
|
||||
pci_devs[i].pdev = pdev;
|
||||
else {
|
||||
if (likely(pdev)) {
|
||||
bus = pdev->bus->number;
|
||||
|
||||
if (bus == 0x3f)
|
||||
socket = 0;
|
||||
else
|
||||
socket = 255 - bus;
|
||||
|
||||
if (socket >= NUM_SOCKETS) {
|
||||
i7core_printk(KERN_ERR,
|
||||
"Found unexpected socket for "
|
||||
"dev %02x:%02x.%d PCI ID %04x:%04x\n",
|
||||
bus, pci_devs[i].dev, pci_devs[i].func,
|
||||
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id);
|
||||
|
||||
rc = -ENODEV;
|
||||
goto error;
|
||||
}
|
||||
|
||||
pci_devs[i].pdev[socket] = pdev;
|
||||
} else {
|
||||
i7core_printk(KERN_ERR,
|
||||
"Device not found: PCI ID %04x:%04x "
|
||||
"(dev %d, func %d)\n",
|
||||
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
|
||||
pci_devs[i].dev, pci_devs[i].func);
|
||||
"Device not found: "
|
||||
"dev %02x:%02x.%d PCI ID %04x:%04x\n",
|
||||
bus, pci_devs[i].dev, pci_devs[i].func,
|
||||
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id);
|
||||
|
||||
/* Dev 3 function 2 only exists on chips with RDIMMs */
|
||||
if ((pci_devs[i].dev == 3) && (pci_devs[i].func == 2))
|
||||
|
|
@ -1121,9 +1199,10 @@ static int i7core_get_devices(void)
|
|||
}
|
||||
|
||||
i7core_printk(KERN_INFO,
|
||||
"Registered device %0x:%0x fn %d.%d\n",
|
||||
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
||||
"Registered socket %d "
|
||||
"dev %02x:%02x.%d PCI ID %04x:%04x\n",
|
||||
socket, bus, pci_devs[i].dev, pci_devs[i].func,
|
||||
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1137,30 +1216,33 @@ static int mci_bind_devs(struct mem_ctl_info *mci)
|
|||
{
|
||||
struct i7core_pvt *pvt = mci->pvt_info;
|
||||
struct pci_dev *pdev;
|
||||
int i, func, slot;
|
||||
int i, j, func, slot;
|
||||
|
||||
for (i = 0; i < N_DEVS; i++) {
|
||||
pdev = pci_devs[i].pdev;
|
||||
if (!pdev)
|
||||
continue;
|
||||
for (i = 0; i < pvt->sockets; i++) {
|
||||
for (j = 0; j < N_DEVS; j++) {
|
||||
pdev = pci_devs[j].pdev[i];
|
||||
if (!pdev)
|
||||
continue;
|
||||
|
||||
func = PCI_FUNC(pdev->devfn);
|
||||
slot = PCI_SLOT(pdev->devfn);
|
||||
if (slot == 3) {
|
||||
if (unlikely(func > MAX_MCR_FUNC))
|
||||
func = PCI_FUNC(pdev->devfn);
|
||||
slot = PCI_SLOT(pdev->devfn);
|
||||
if (slot == 3) {
|
||||
if (unlikely(func > MAX_MCR_FUNC))
|
||||
goto error;
|
||||
pvt->pci_mcr[i][func] = pdev;
|
||||
} else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
|
||||
if (unlikely(func > MAX_CHAN_FUNC))
|
||||
goto error;
|
||||
pvt->pci_ch[i][slot - 4][func] = pdev;
|
||||
} else if (!slot && !func)
|
||||
pvt->pci_noncore[i] = pdev;
|
||||
else
|
||||
goto error;
|
||||
pvt->pci_mcr[func] = pdev;
|
||||
} else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
|
||||
if (unlikely(func > MAX_CHAN_FUNC))
|
||||
goto error;
|
||||
pvt->pci_ch[slot - 4][func] = pdev;
|
||||
} else if (!slot && !func)
|
||||
pvt->pci_noncore = pdev;
|
||||
else
|
||||
goto error;
|
||||
|
||||
debugf0("Associated fn %d.%d, dev = %p\n",
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev);
|
||||
debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
|
||||
pdev, i);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1182,20 +1264,20 @@ error:
|
|||
* also available at:
|
||||
* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
|
||||
*/
|
||||
static void check_mc_test_err(struct mem_ctl_info *mci)
|
||||
static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
|
||||
{
|
||||
struct i7core_pvt *pvt = mci->pvt_info;
|
||||
u32 rcv1, rcv0;
|
||||
int new0, new1, new2;
|
||||
|
||||
if (!pvt->pci_mcr[4]) {
|
||||
if (!pvt->pci_mcr[socket][4]) {
|
||||
debugf0("%s MCR registers not found\n",__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Corrected error reads */
|
||||
pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
|
||||
pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
|
||||
pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
|
||||
pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
|
||||
|
||||
/* Store the new values */
|
||||
new2 = DIMM2_COR_ERR(rcv1);
|
||||
|
|
@ -1209,32 +1291,32 @@ static void check_mc_test_err(struct mem_ctl_info *mci)
|
|||
#endif
|
||||
|
||||
/* Updates CE counters if it is not the first time here */
|
||||
if (pvt->ce_count_available) {
|
||||
if (pvt->ce_count_available[socket]) {
|
||||
/* Updates CE counters */
|
||||
int add0, add1, add2;
|
||||
|
||||
add2 = new2 - pvt->last_ce_count[2];
|
||||
add1 = new1 - pvt->last_ce_count[1];
|
||||
add0 = new0 - pvt->last_ce_count[0];
|
||||
add2 = new2 - pvt->last_ce_count[socket][2];
|
||||
add1 = new1 - pvt->last_ce_count[socket][1];
|
||||
add0 = new0 - pvt->last_ce_count[socket][0];
|
||||
|
||||
if (add2 < 0)
|
||||
add2 += 0x7fff;
|
||||
pvt->ce_count[2] += add2;
|
||||
pvt->ce_count[socket][2] += add2;
|
||||
|
||||
if (add1 < 0)
|
||||
add1 += 0x7fff;
|
||||
pvt->ce_count[1] += add1;
|
||||
pvt->ce_count[socket][1] += add1;
|
||||
|
||||
if (add0 < 0)
|
||||
add0 += 0x7fff;
|
||||
pvt->ce_count[0] += add0;
|
||||
pvt->ce_count[socket][0] += add0;
|
||||
} else
|
||||
pvt->ce_count_available = 1;
|
||||
pvt->ce_count_available[socket] = 1;
|
||||
|
||||
/* Store the new values */
|
||||
pvt->last_ce_count[2] = new2;
|
||||
pvt->last_ce_count[1] = new1;
|
||||
pvt->last_ce_count[0] = new0;
|
||||
pvt->last_ce_count[socket][2] = new2;
|
||||
pvt->last_ce_count[socket][1] = new1;
|
||||
pvt->last_ce_count[socket][0] = new0;
|
||||
}
|
||||
|
||||
static void i7core_mce_output_error(struct mem_ctl_info *mci,
|
||||
|
|
@ -1299,7 +1381,8 @@ static void i7core_check_error(struct mem_ctl_info *mci)
|
|||
kfree(m);
|
||||
|
||||
/* check memory count errors */
|
||||
check_mc_test_err(mci);
|
||||
for (i = 0; i < pvt->sockets; i++)
|
||||
check_mc_test_err(mci, i);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1339,10 +1422,11 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
|
|||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct i7core_pvt *pvt;
|
||||
int num_channels;
|
||||
int num_csrows;
|
||||
int num_channels = 0;
|
||||
int num_csrows = 0;
|
||||
int dev_idx = id->driver_data;
|
||||
int rc;
|
||||
int rc, i;
|
||||
u8 sockets;
|
||||
|
||||
if (unlikely(dev_idx >= ARRAY_SIZE(i7core_devs)))
|
||||
return -EINVAL;
|
||||
|
|
@ -1352,10 +1436,25 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
|
|||
if (unlikely(rc < 0))
|
||||
return rc;
|
||||
|
||||
/* Check the number of active and not disabled channels */
|
||||
rc = i7core_get_active_channels(&num_channels, &num_csrows);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
sockets = 1;
|
||||
for (i = NUM_SOCKETS - 1; i > 0; i--)
|
||||
if (pci_devs[0].pdev[i]) {
|
||||
sockets = i + 1;
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < sockets; i++) {
|
||||
int channels;
|
||||
int csrows;
|
||||
|
||||
/* Check the number of active and not disabled channels */
|
||||
rc = i7core_get_active_channels(i, &channels, &csrows);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
|
||||
num_channels += channels;
|
||||
num_csrows += csrows;
|
||||
}
|
||||
|
||||
/* allocate a new MC control structure */
|
||||
mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
|
||||
|
|
@ -1367,11 +1466,11 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
|
|||
debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
|
||||
|
||||
mci->dev = &pdev->dev; /* record ptr to the generic device */
|
||||
|
||||
pvt = mci->pvt_info;
|
||||
memset(pvt, 0, sizeof(*pvt));
|
||||
|
||||
pvt->sockets = sockets;
|
||||
mci->mc_idx = 0;
|
||||
|
||||
/*
|
||||
* FIXME: how to handle RDDR3 at MCI level? It is possible to have
|
||||
* Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
|
||||
|
|
@ -1395,7 +1494,8 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
|
|||
goto fail1;
|
||||
|
||||
/* Get dimm basic config */
|
||||
get_dimm_config(mci);
|
||||
for (i = 0; i < sockets; i++)
|
||||
get_dimm_config(mci, i);
|
||||
|
||||
/* add this new MC control structure to EDAC's list of MCs */
|
||||
if (unlikely(edac_mc_add_mc(mci))) {
|
||||
|
|
|
|||
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