x86/platform/UV: Update uv_mmrs.h to prepare for UV4A fixes
Regenerate uv_mmrs.h file to accommodate fixes to UV4A MMRs. Signed-off-by: Mike Travis <mike.travis@hpe.com> Acked-by: Andrew Banman <abanman@hpe.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Dimitri Sivanich <sivanich@hpe.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russ Anderson <rja@hpe.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1515440405-20880-2-git-send-email-mike.travis@hpe.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Mike Travis
Ingo Molnar
Родитель
abde587b61
Коммит
673aa20c55
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@ -3031,6 +3031,41 @@ union uvh_node_present_table_u {
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
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unsigned long v;
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@ -3042,6 +3077,46 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s;
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struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s1;
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struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} sx;
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struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s2;
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struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s3;
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struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s4;
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};
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/* ========================================================================= */
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@ -3064,6 +3139,41 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
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unsigned long v;
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@ -3075,6 +3185,46 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s;
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struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s1;
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struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} sx;
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struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s2;
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struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s3;
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struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s4;
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};
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/* ========================================================================= */
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@ -3097,6 +3247,41 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
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unsigned long v;
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@ -3108,6 +3293,46 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s;
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struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s1;
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struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} sx;
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struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s2;
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struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s3;
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struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23:24;
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unsigned long base:8; /* RW */
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unsigned long rsvd_32_47:16;
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unsigned long m_alias:5; /* RW */
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unsigned long rsvd_53_62:10;
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unsigned long enable:1; /* RW */
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} s4;
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};
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/* ========================================================================= */
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@ -3126,6 +3351,21 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
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#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
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#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
|
||||
#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
|
||||
union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
|
||||
unsigned long v;
|
||||
|
|
@ -3134,6 +3374,31 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
|
|||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s;
|
||||
struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s1;
|
||||
struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} sx;
|
||||
struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s2;
|
||||
struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s3;
|
||||
struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
|
|
@ -3152,6 +3417,21 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
|
|||
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
|
||||
union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
|
||||
unsigned long v;
|
||||
|
|
@ -3160,6 +3440,31 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
|
|||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s;
|
||||
struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s1;
|
||||
struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} sx;
|
||||
struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s2;
|
||||
struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s3;
|
||||
struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
|
|
@ -3178,6 +3483,21 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
|
|||
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
||||
#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
||||
|
||||
|
||||
union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
|
||||
unsigned long v;
|
||||
|
|
@ -3186,6 +3506,31 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
|
|||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s;
|
||||
struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s1;
|
||||
struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} sx;
|
||||
struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s2;
|
||||
struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s3;
|
||||
struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s {
|
||||
unsigned long rsvd_0_23:24;
|
||||
unsigned long dest_base:22; /* RW */
|
||||
unsigned long rsvd_46_63:18;
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
|
|
@ -3383,6 +3728,106 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
|
|||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
|
||||
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL
|
||||
#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR)
|
||||
|
||||
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
|
||||
union uvh_rh_gam_mmioh_overlay_config0_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s3;
|
||||
struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
|
||||
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL
|
||||
#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR)
|
||||
|
||||
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
|
||||
union uvh_rh_gam_mmioh_overlay_config1_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s3;
|
||||
struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
|
||||
/* ========================================================================= */
|
||||
|
|
@ -3437,6 +3882,94 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
|
|||
} s2;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
|
||||
#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL
|
||||
#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR)
|
||||
|
||||
#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
|
||||
#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
|
||||
#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH)
|
||||
|
||||
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
|
||||
union uvh_rh_gam_mmioh_redirect_config0_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s3;
|
||||
struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
|
||||
#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL
|
||||
#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR)
|
||||
|
||||
#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
|
||||
#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
|
||||
#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH ( \
|
||||
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \
|
||||
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \
|
||||
is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \
|
||||
/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH)
|
||||
|
||||
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
|
||||
#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
|
||||
union uvh_rh_gam_mmioh_redirect_config1_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s3;
|
||||
struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s4;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
|
||||
/* ========================================================================= */
|
||||
|
|
@ -4137,88 +4670,6 @@ union uv3h_gr0_gam_gr_config_u {
|
|||
} s3;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
union uv3h_rh_gam_mmioh_overlay_config0_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s3;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
|
||||
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
|
||||
|
||||
union uv3h_rh_gam_mmioh_overlay_config1_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
|
||||
unsigned long rsvd_0_25:26;
|
||||
unsigned long base:20; /* RW */
|
||||
unsigned long m_io:6; /* RW */
|
||||
unsigned long n_io:4;
|
||||
unsigned long rsvd_56_62:7;
|
||||
unsigned long enable:1; /* RW */
|
||||
} s3;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
union uv3h_rh_gam_mmioh_redirect_config0_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s3;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */
|
||||
/* ========================================================================= */
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
|
||||
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
|
||||
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
|
||||
|
||||
union uv3h_rh_gam_mmioh_redirect_config1_mmr_u {
|
||||
unsigned long v;
|
||||
struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
|
||||
unsigned long nasid:15; /* RW */
|
||||
unsigned long rsvd_15_63:49;
|
||||
} s3;
|
||||
};
|
||||
|
||||
/* ========================================================================= */
|
||||
/* UV4H_LB_PROC_INTD_QUEUE_FIRST */
|
||||
/* ========================================================================= */
|
||||
|
|
|
|||
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