ARM: mx35: Add mx35_revision function to query the silicon revision
Based on work done earlier by Sascha Hauer Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Eric Bénard <eric@eukrea.com> [ukl: actually squash the two approaches together] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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67520f3a89
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@ -535,6 +535,9 @@ int __init mx35_clocks_init()
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__raw_writel(cgr2, CCM_BASE + CCM_CGR2);
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__raw_writel(cgr3, CCM_BASE + CCM_CGR3);
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clk_enable(&iim_clk);
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mx35_read_cpu_rev();
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#ifdef CONFIG_MXC_USE_EPIT
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epit_timer_init(&epit1_clk,
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MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
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@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
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printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
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}
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unsigned int mx35_cpu_rev;
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EXPORT_SYMBOL(mx35_cpu_rev);
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void __init mx35_read_cpu_rev(void)
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{
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u32 rev;
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char *srev = "unknown";
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rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
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switch (rev) {
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case 0x00:
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mx35_cpu_rev = MX3x_CHIP_REV_1_0;
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srev = "1.0";
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break;
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case 0x10:
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mx35_cpu_rev = MX3x_CHIP_REV_2_0;
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srev = "2.0";
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break;
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case 0x11:
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mx35_cpu_rev = MX3x_CHIP_REV_2_1;
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srev = "2.1";
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break;
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}
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printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
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}
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@ -1,5 +1,6 @@
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#ifndef __MACH_MX35_H__
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#define __MACH_MX35_H__
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/*
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* IRAM
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*/
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@ -66,6 +67,8 @@
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#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
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#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
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#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
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#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
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#define MX35_OTG_BASE_ADDR 0x53ff4000
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#define MX35_ROMP_BASE_ADDR 0x60000000
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@ -187,20 +190,7 @@
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#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
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/* silicon revisions specific to i.MX31 */
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#define MX35_CHIP_REV_1_0 0x10
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#define MX35_CHIP_REV_1_1 0x11
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#define MX35_CHIP_REV_1_2 0x12
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#define MX35_CHIP_REV_1_3 0x13
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#define MX35_CHIP_REV_2_0 0x20
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#define MX35_CHIP_REV_2_1 0x21
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#define MX35_CHIP_REV_2_2 0x22
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#define MX35_CHIP_REV_2_3 0x23
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#define MX35_CHIP_REV_3_0 0x30
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#define MX35_CHIP_REV_3_1 0x31
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#define MX35_CHIP_REV_3_2 0x32
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#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
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#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
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#define MX35_SYSTEM_REV_NUM 3
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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@ -240,7 +240,7 @@
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#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
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/* silicon revisions specific to i.MX31 */
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/* silicon revisions specific to i.MX31 and i.MX35 */
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#define MX3x_CHIP_REV_1_0 0x10
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#define MX3x_CHIP_REV_1_1 0x11
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#define MX3x_CHIP_REV_1_2 0x12
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@ -267,6 +267,14 @@ static inline int mx31_revision(void)
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{
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return mx31_cpu_rev;
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}
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extern unsigned int mx35_cpu_rev;
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extern void mx35_read_cpu_rev(void);
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static inline int mx35_revision(void)
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{
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return mx35_cpu_rev;
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}
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#endif
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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