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cmdq: 

- clean ups of unused code and debuggability
 - add cmdq_instruction to make the function call interface more readable
 - add functions for polling and providing info for the user of cmdq
 
 scpsys:
 - add bindings for MT6765
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl4cPekXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH6YDA/+MRYiMb26fu+Ac3pF1SW6ao0A
 fCI0JH2L8Zj4nklg3Y/hoi2PG7DJL2vaG71Ng3iQxQqKLWJdS1WbF/DBl8JdozQx
 mJXXZ0JM5cc/gIvrG8PLAauWRTDUIPDC2ZZ66mO4CiR6T7Kp/LpnmZF5ZR4qxu/W
 KNAYxSeyPJ36WQ3HCmubBWOn4JaetOeBFID6z3roKhsGyFXLmCo0Djw4c0Lpk79t
 3qVpo7TcC3hintZSC8ufIjQZA/KU3kwy3pS2O+HKMDb4EwORl14Grd6/cN9rAf0p
 twprn4Y9Jx4cBy0jGyZShKMbIn6wT6zF8GqpoV71vvXTgknyr8XoaiepnjMd2Enm
 BXw7R8kUt3w4mHnMwX9aUPAP48S1DVMm0OsbwOOqRcSXyJWnQBFB85LnkKeSfzRW
 iWfeXQBaESCQziYkJSkXz2D4epV/Rzq/L1y5IrddQuwIlpQ3eeqYUWBDYhuV3VlY
 K4r/AawG0NKPWTvH0bgLZAiWybnzXPZUvVJzwkdwRBjpiyhsl0FX1oZb1H8Vf6mK
 yrCUgaTIVp6z0pMd8kaxPTyi2AXryKODOXp+XJ2JFmdLFuBPQMSLCiG+B6sDa2Sw
 eYMcZpFtL5B/p/NpNuSUlGZ2HXTxknS3RnIDTUJ583BZLeItShHnBW3P/8qjx7Wm
 8oGsLh0ZLF0G5iqdeuM=
 =Q9/6
 -----END PGP SIGNATURE-----

Merge tag 'v5.5-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

cmdq:
- clean ups of unused code and debuggability
- add cmdq_instruction to make the function call interface more readable
- add functions for polling and providing info for the user of cmdq

scpsys:
- add bindings for MT6765

* tag 'v5.5-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: mediatek: add MT6765 power dt-bindings
  soc: mediatek: cmdq: delete not used define
  soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
  soc: mediatek: cmdq: add polling function
  soc: mediatek: cmdq: define the instruction struct
  soc: mediatek: cmdq: remove OR opertaion from err return

Link: https://lore.kernel.org/r/9b365e76-e346-f813-d750-d7cfd0d16e4e@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-01-20 11:26:09 -08:00
Родитель 96b34bac41 9c26abeb86
Коммит 684415d0de
5 изменённых файлов: 205 добавлений и 28 удалений
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6
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
Просмотреть файл

@ -11,6 +11,7 @@ The driver implements the Generic PM domain bindings described in
power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt6765-power.h
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
@ -19,6 +20,7 @@ Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt2712-scpsys"
- "mediatek,mt6765-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
@ -33,6 +35,10 @@ Required properties:
enabled before enabling certain power domains.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6765: MUX: "mm", "mfg"
CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0",
"isp-1", "cam-0", "cam-1", "cam-2",
"cam-3","cam-4"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"

149
drivers/soc/mediatek/mtk-cmdq-helper.c
Просмотреть файл

@ -9,11 +9,51 @@
#include <linux/mailbox_controller.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#define CMDQ_ARG_A_WRITE_MASK 0xffff
#define CMDQ_WRITE_ENABLE_MASK BIT(0)
#define CMDQ_POLL_ENABLE_MASK BIT(0)
#define CMDQ_EOC_IRQ_EN BIT(0)
#define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
<< 32 | CMDQ_EOC_IRQ_EN)
struct cmdq_instruction {
union {
u32 value;
u32 mask;
};
union {
u16 offset;
u16 event;
};
u8 subsys;
u8 op;
};
int cmdq_dev_get_client_reg(struct device *dev,
struct cmdq_client_reg *client_reg, int idx)
{
struct of_phandle_args spec;
int err;
if (!client_reg)
return -ENOENT;
err = of_parse_phandle_with_fixed_args(dev->of_node,
"mediatek,gce-client-reg",
3, idx, &spec);
if (err < 0) {
dev_err(dev,
"error %d can't parse gce-client-reg property (%d)",
err, idx);
return err;
}
client_reg->subsys = (u8)spec.args[0];
client_reg->offset = (u16)spec.args[1];
client_reg->size = (u16)spec.args[2];
of_node_put(spec.np);
return 0;
}
EXPORT_SYMBOL(cmdq_dev_get_client_reg);
static void cmdq_client_timeout(struct timer_list *t)
{
@ -110,10 +150,10 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
}
EXPORT_SYMBOL(cmdq_pkt_destroy);
static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
u32 arg_a, u32 arg_b)
static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
struct cmdq_instruction inst)
{
u64 *cmd_ptr;
struct cmdq_instruction *cmd_ptr;
if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
/*
@ -129,8 +169,9 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
__func__, (u32)pkt->buf_size);
return -ENOMEM;
}
cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
(*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
*cmd_ptr = inst;
pkt->cmd_buf_size += CMDQ_INST_SIZE;
return 0;
@ -138,24 +179,34 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
{
u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
(subsys << CMDQ_SUBSYS_SHIFT);
struct cmdq_instruction inst;
return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
inst.op = CMDQ_CODE_WRITE;
inst.value = value;
inst.offset = offset;
inst.subsys = subsys;
return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_write);
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask)
{
u32 offset_mask = offset;
int err = 0;
struct cmdq_instruction inst = { {0} };
u16 offset_mask = offset;
int err;
if (mask != 0xffffffff) {
err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
inst.op = CMDQ_CODE_MASK;
inst.mask = ~mask;
err = cmdq_pkt_append_command(pkt, inst);
if (err < 0)
return err;
offset_mask |= CMDQ_WRITE_ENABLE_MASK;
}
err |= cmdq_pkt_write(pkt, subsys, offset_mask, value);
err = cmdq_pkt_write(pkt, subsys, offset_mask, value);
return err;
}
@ -163,43 +214,85 @@ EXPORT_SYMBOL(cmdq_pkt_write_mask);
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
{
u32 arg_b;
struct cmdq_instruction inst = { {0} };
if (event >= CMDQ_MAX_EVENT)
return -EINVAL;
/*
* WFE arg_b
* bit 0-11: wait value
* bit 15: 1 - wait, 0 - no wait
* bit 16-27: update value
* bit 31: 1 - update, 0 - no update
*/
arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
inst.op = CMDQ_CODE_WFE;
inst.value = CMDQ_WFE_OPTION;
inst.event = event;
return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b);
return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_wfe);
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
{
struct cmdq_instruction inst = { {0} };
if (event >= CMDQ_MAX_EVENT)
return -EINVAL;
return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event,
CMDQ_WFE_UPDATE);
inst.op = CMDQ_CODE_WFE;
inst.value = CMDQ_WFE_UPDATE;
inst.event = event;
return cmdq_pkt_append_command(pkt, inst);
}
EXPORT_SYMBOL(cmdq_pkt_clear_event);
int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value)
{
struct cmdq_instruction inst = { {0} };
int err;
inst.op = CMDQ_CODE_POLL;
inst.value = value;
inst.offset = offset;
inst.subsys = subsys;
err = cmdq_pkt_append_command(pkt, inst);
return err;
}
EXPORT_SYMBOL(cmdq_pkt_poll);
int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask)
{
struct cmdq_instruction inst = { {0} };
int err;
inst.op = CMDQ_CODE_MASK;
inst.mask = ~mask;
err = cmdq_pkt_append_command(pkt, inst);
if (err < 0)
return err;
offset = offset | CMDQ_POLL_ENABLE_MASK;
err = cmdq_pkt_poll(pkt, subsys, offset, value);
return err;
}
EXPORT_SYMBOL(cmdq_pkt_poll_mask);
static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
struct cmdq_instruction inst = { {0} };
int err;
/* insert EOC and generate IRQ for each command iteration */
err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
inst.op = CMDQ_CODE_EOC;
inst.value = CMDQ_EOC_IRQ_EN;
err = cmdq_pkt_append_command(pkt, inst);
if (err < 0)
return err;
/* JUMP to end */
err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
inst.op = CMDQ_CODE_JUMP;
inst.value = CMDQ_JUMP_PASS;
err = cmdq_pkt_append_command(pkt, inst);
return err;
}

14
include/dt-bindings/power/mt6765-power.h Normal file
Просмотреть файл

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H
#define _DT_BINDINGS_POWER_MT6765_POWER_H
#define MT6765_POWER_DOMAIN_CONN 0
#define MT6765_POWER_DOMAIN_MM 1
#define MT6765_POWER_DOMAIN_MFG_ASYNC 2
#define MT6765_POWER_DOMAIN_ISP 3
#define MT6765_POWER_DOMAIN_MFG 4
#define MT6765_POWER_DOMAIN_MFG_CORE0 5
#define MT6765_POWER_DOMAIN_CAM 6
#define MT6765_POWER_DOMAIN_VCODEC 7
#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */

11
include/linux/mailbox/mtk-cmdq-mailbox.h
Просмотреть файл

@ -20,6 +20,16 @@
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1
/*
* WFE arg_b
* bit 0-11: wait value
* bit 15: 1 - wait, 0 - no wait
* bit 16-27: update value
* bit 31: 1 - update, 0 - no update
*/
#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
CMDQ_WFE_WAIT_VALUE)
/** cmdq event maximum */
#define CMDQ_MAX_EVENT 0x3ff
@ -45,6 +55,7 @@
enum cmdq_code {
CMDQ_CODE_MASK = 0x02,
CMDQ_CODE_WRITE = 0x04,
CMDQ_CODE_POLL = 0x08,
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,

53
include/linux/soc/mediatek/mtk-cmdq.h
Просмотреть файл

@ -15,6 +15,12 @@
struct cmdq_pkt;
struct cmdq_client_reg {
u8 subsys;
u16 offset;
u16 size;
};
struct cmdq_client {
spinlock_t lock;
u32 pkt_cnt;
@ -24,6 +30,21 @@ struct cmdq_client {
u32 timeout_ms; /* in unit of microsecond */
};
/**
* cmdq_dev_get_client_reg() - parse cmdq client reg from the device
* node of CMDQ client
* @dev: device of CMDQ mailbox client
* @client_reg: CMDQ client reg pointer
* @idx: the index of desired reg
*
* Return: 0 for success; else the error code is returned
*
* Help CMDQ client parsing the cmdq client reg
* from the device node of CMDQ client.
*/
int cmdq_dev_get_client_reg(struct device *dev,
struct cmdq_client_reg *client_reg, int idx);
/**
* cmdq_mbox_create() - create CMDQ mailbox client and channel
* @dev: device of CMDQ mailbox client
@ -99,6 +120,38 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
*/
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
/**
* cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
* execute an instruction that wait for a specified
* hardware register to check for the value w/o mask.
* All GCE hardware threads will be blocked by this
* instruction.
* @pkt: the CMDQ packet
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
* @value: the specified target register value
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value);
/**
* cmdq_pkt_poll_mask() - Append polling command to the CMDQ packet, ask GCE to
* execute an instruction that wait for a specified
* hardware register to check for the value w/ mask.
* All GCE hardware threads will be blocked by this
* instruction.
* @pkt: the CMDQ packet
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
* @value: the specified target register value
* @mask: the specified target register mask
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask);
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
* packet and call back at the end of done packet