ARM: ux500: select L2X0 cache on ux500
The cache controller needs to be enabled for the cortex-a9 specific errata that are also selected to work. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -8,6 +8,7 @@ config UX500_SOC_COMMON
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select ARM_ERRATA_753970
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369
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select CACHE_L2X0
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config UX500_SOC_DB5500
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bool
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