clk: qcom: smd-rpmcc: Add msm8974 clocks
This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Bjorn Andersson
Stephen Boyd
Родитель
2aab7a2055
Коммит
685dc94b7d
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@ -11,6 +11,7 @@ Required properties :
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compatible "qcom,rpmcc" should be also included.
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"qcom,rpmcc-msm8916", "qcom,rpmcc"
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"qcom,rpmcc-msm8974", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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- #clock-cells : shall contain 1
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@ -462,8 +462,79 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
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.num_clks = ARRAY_SIZE(msm8916_clks),
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};
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/* msm8974 */
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DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
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DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
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DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
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static struct clk_smd_rpm *msm8974_clks[] = {
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[RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk,
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[RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk,
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[RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk,
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[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
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[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
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[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
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[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
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[RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk,
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[RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk,
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[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
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[RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
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[RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk,
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[RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk,
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[RPM_SMD_CXO_D0] = &msm8974_cxo_d0,
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[RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a,
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[RPM_SMD_CXO_D1] = &msm8974_cxo_d1,
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[RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a,
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[RPM_SMD_CXO_A0] = &msm8974_cxo_a0,
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[RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a,
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[RPM_SMD_CXO_A1] = &msm8974_cxo_a1,
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[RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a,
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[RPM_SMD_CXO_A2] = &msm8974_cxo_a2,
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[RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a,
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[RPM_SMD_DIFF_CLK] = &msm8974_diff_clk,
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[RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk,
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[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
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[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
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[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
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[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
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[RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin,
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[RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin,
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[RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin,
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[RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin,
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[RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin,
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[RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin,
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[RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin,
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[RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin,
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[RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin,
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[RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin,
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};
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static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
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.clks = msm8974_clks,
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.num_clks = ARRAY_SIZE(msm8974_clks),
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};
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static const struct of_device_id rpm_smd_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
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{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
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{ }
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};
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MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
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@ -14,7 +14,7 @@
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#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
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#define _DT_BINDINGS_CLK_MSM_RPMCC_H
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/* apq8064 */
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/* RPM clocks */
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#define RPM_PXO_CLK 0
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#define RPM_PXO_A_CLK 1
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#define RPM_CXO_CLK 2
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@ -38,7 +38,7 @@
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#define RPM_SFPB_CLK 20
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#define RPM_SFPB_A_CLK 21
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/* msm8916 */
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/* SMD RPM clocks */
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#define RPM_SMD_XO_CLK_SRC 0
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#define RPM_SMD_XO_A_CLK_SRC 1
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#define RPM_SMD_PCNOC_CLK 2
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@ -65,5 +65,41 @@
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#define RPM_SMD_RF_CLK1_A_PIN 23
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#define RPM_SMD_RF_CLK2_PIN 24
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#define RPM_SMD_RF_CLK2_A_PIN 25
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#define RPM_SMD_PNOC_CLK 26
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#define RPM_SMD_PNOC_A_CLK 27
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#define RPM_SMD_CNOC_CLK 28
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#define RPM_SMD_CNOC_A_CLK 29
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#define RPM_SMD_MMSSNOC_AHB_CLK 30
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#define RPM_SMD_MMSSNOC_AHB_A_CLK 31
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#define RPM_SMD_GFX3D_CLK_SRC 32
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#define RPM_SMD_GFX3D_A_CLK_SRC 33
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#define RPM_SMD_OCMEMGX_CLK 34
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#define RPM_SMD_OCMEMGX_A_CLK 35
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#define RPM_SMD_CXO_D0 36
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#define RPM_SMD_CXO_D0_A 37
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#define RPM_SMD_CXO_D1 38
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#define RPM_SMD_CXO_D1_A 39
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#define RPM_SMD_CXO_A0 40
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#define RPM_SMD_CXO_A0_A 41
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#define RPM_SMD_CXO_A1 42
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#define RPM_SMD_CXO_A1_A 43
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#define RPM_SMD_CXO_A2 44
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#define RPM_SMD_CXO_A2_A 45
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#define RPM_SMD_DIV_CLK1 46
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#define RPM_SMD_DIV_A_CLK1 47
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#define RPM_SMD_DIV_CLK2 48
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#define RPM_SMD_DIV_A_CLK2 49
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#define RPM_SMD_DIFF_CLK 50
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#define RPM_SMD_DIFF_A_CLK 51
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#define RPM_SMD_CXO_D0_PIN 52
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#define RPM_SMD_CXO_D0_A_PIN 53
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#define RPM_SMD_CXO_D1_PIN 54
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#define RPM_SMD_CXO_D1_A_PIN 55
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#define RPM_SMD_CXO_A0_PIN 56
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#define RPM_SMD_CXO_A0_A_PIN 57
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#define RPM_SMD_CXO_A1_PIN 58
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#define RPM_SMD_CXO_A1_A_PIN 59
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#define RPM_SMD_CXO_A2_PIN 60
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#define RPM_SMD_CXO_A2_A_PIN 61
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#endif
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