memory: tegra: Changes for v4.18-rc1
This contains some cleanup of the memory controller driver as well as unification work to share more code between Tegra20 and later SoC generations. Also included are an implementation for the hot resets functionality by the memory controller which is required to properly reset busy hardware. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlr/O5kTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYBuD/0StspIEG9GK8xOdf93unbziinCZ2DG e+xae7l5VfC2VsG5MgyYCr0ugOThdHHzqqsit3uHBXe9cUlNaL6YKyAiTIT7HFNM a0lnE+I++p0bL0GqMa/9l9jWnheR5iKnZYratyKJjtmEd9ljDcgo4Xn0lUonf3NS 9gmI/2qiqkry+pLRafN65H6mbK6JyQ07xZAqd322S8aVkKx10L+GwzMjj6K342zu KPJd5B2mpCkaAc9maFOY5zcljaRBNU5mFGJEzhdzrq6KXcfDnZxyufVX80RhP9vO 9RQJyFVsFiBgH59YPBc72X8Nu0Cc/14jTH1rE55R4239y96cJ/LuniYtHcWqumuL OQgsMfslO8RJ9/XBy/0UEznx1hnDJGfT7s2SRfgCsGnKegvcSw1IASI7xA+49DIR ZpVLEIB3Htq5DGymQrDG99z6tccMV5PJNEOjDhrh74DSXy9S/6Hl9UAoX3455/7Y zP2B5yUfaCnipwWXSowzmkXRKfCrHus1o//YfyarhmRVeDNeMkdbPcxGFZL7Y+MC PPorRu+WdKKzcY+8xmQig+UY2K3thpYSNG1D8vZLC6Dv3r06qGAk2vy9pV2bYG86 4FG9Ory36XK/5fnfLTvTPnbguRNI1y/hbQ7XTTJcnxCvUqNkT7bAgspPfn0gkY+1 Uh8Jm57WooiwHQ== =uVPT -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers memory: tegra: Changes for v4.18-rc1 This contains some cleanup of the memory controller driver as well as unification work to share more code between Tegra20 and later SoC generations. Also included are an implementation for the hot resets functionality by the memory controller which is required to properly reset busy hardware. * tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Register SMMU after MC driver became ready memory: tegra: Add Tegra210 memory controller hot resets memory: tegra: Add Tegra124 memory controller hot resets memory: tegra: Add Tegra114 memory controller hot resets memory: tegra: Add Tegra30 memory controller hot resets memory: tegra: Add Tegra20 memory controller hot resets memory: tegra: Introduce memory client hot reset memory: tegra: Squash tegra20-mc into common tegra-mc driver memory: tegra: Remove unused headers inclusions memory: tegra: Apply interrupts mask per SoC memory: tegra: Setup interrupts mask before requesting IRQ memory: tegra: Do not handle spurious interrupts dt-bindings: memory: tegra: Add hot resets definitions Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
6874f9de65
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@ -104,16 +104,6 @@ config MVEBU_DEVBUS
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Armada 370 and Armada XP. This controller allows to handle flash
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devices such as NOR, NAND, SRAM, and FPGA.
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config TEGRA20_MC
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bool "Tegra20 Memory Controller(MC) driver"
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default y
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depends on ARCH_TEGRA_2x_SOC
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help
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This driver is for the Memory Controller(MC) module available
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in Tegra20 SoCs, mainly for a address translation fault
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analysis, especially for IOMMU/GART(Graphics Address
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Relocation Table) module.
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config FSL_CORENET_CF
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tristate "Freescale CoreNet Error Reporting"
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depends on FSL_SOC_BOOKE
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@ -16,7 +16,6 @@ obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o
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obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
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obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
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obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
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obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
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obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
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obj-$(CONFIG_MTK_SMI) += mtk-smi.o
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obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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tegra-mc-y := mc.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
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@ -7,6 +7,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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@ -20,14 +21,6 @@
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#include "mc.h"
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#define MC_INTSTATUS 0x000
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#define MC_INT_DECERR_MTS (1 << 16)
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#define MC_INT_SECERR_SEC (1 << 13)
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#define MC_INT_DECERR_VPR (1 << 12)
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#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
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#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
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#define MC_INT_ARBITRATION_EMEM (1 << 9)
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#define MC_INT_SECURITY_VIOLATION (1 << 8)
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#define MC_INT_DECERR_EMEM (1 << 6)
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#define MC_INTMASK 0x004
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@ -45,6 +38,9 @@
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#define MC_ERR_ADR 0x0c
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
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#define MC_SECURITY_VIOLATION_STATUS 0x74
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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@ -54,6 +50,9 @@
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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static const struct of_device_id tegra_mc_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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{ .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
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#endif
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@ -73,6 +72,207 @@ static const struct of_device_id tegra_mc_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
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static int terga_mc_block_dma_common(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) | BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static bool terga_mc_dma_idling_common(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
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}
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static int terga_mc_unblock_dma_common(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static int terga_mc_reset_status_common(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
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}
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const struct tegra_mc_reset_ops terga_mc_reset_ops_common = {
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.block_dma = terga_mc_block_dma_common,
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.dma_idling = terga_mc_dma_idling_common,
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.unblock_dma = terga_mc_unblock_dma_common,
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.reset_status = terga_mc_reset_status_common,
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};
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static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct tegra_mc, reset);
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}
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static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
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unsigned long id)
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{
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unsigned int i;
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for (i = 0; i < mc->soc->num_resets; i++)
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if (mc->soc->resets[i].id == id)
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return &mc->soc->resets[i];
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return NULL;
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}
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static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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int retries = 500;
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int err;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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if (rst_ops->block_dma) {
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/* block clients DMA requests */
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err = rst_ops->block_dma(mc, rst);
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if (err) {
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dev_err(mc->dev, "Failed to block %s DMA: %d\n",
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rst->name, err);
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return err;
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}
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}
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if (rst_ops->dma_idling) {
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/* wait for completion of the outstanding DMA requests */
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while (!rst_ops->dma_idling(mc, rst)) {
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if (!retries--) {
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dev_err(mc->dev, "Failed to flush %s DMA\n",
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rst->name);
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return -EBUSY;
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}
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usleep_range(10, 100);
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}
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}
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if (rst_ops->hotreset_assert) {
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/* clear clients DMA requests sitting before arbitration */
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err = rst_ops->hotreset_assert(mc, rst);
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if (err) {
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dev_err(mc->dev, "Failed to hot reset %s: %d\n",
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rst->name, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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int err;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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if (rst_ops->hotreset_deassert) {
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/* take out client from hot reset */
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err = rst_ops->hotreset_deassert(mc, rst);
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if (err) {
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dev_err(mc->dev, "Failed to deassert hot reset %s: %d\n",
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rst->name, err);
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return err;
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}
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}
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if (rst_ops->unblock_dma) {
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/* allow new DMA requests to proceed to arbitration */
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err = rst_ops->unblock_dma(mc, rst);
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if (err) {
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dev_err(mc->dev, "Failed to unblock %s DMA : %d\n",
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rst->name, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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return rst_ops->reset_status(mc, rst);
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}
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static const struct reset_control_ops tegra_mc_reset_ops = {
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.assert = tegra_mc_hotreset_assert,
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.deassert = tegra_mc_hotreset_deassert,
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.status = tegra_mc_hotreset_status,
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};
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static int tegra_mc_reset_setup(struct tegra_mc *mc)
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{
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int err;
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mc->reset.ops = &tegra_mc_reset_ops;
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mc->reset.owner = THIS_MODULE;
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mc->reset.of_node = mc->dev->of_node;
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mc->reset.of_reset_n_cells = 1;
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mc->reset.nr_resets = mc->soc->num_resets;
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err = reset_controller_register(&mc->reset);
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if (err < 0)
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return err;
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return 0;
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}
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static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
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{
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unsigned long long tick;
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@ -229,6 +429,7 @@ static int tegra_mc_setup_timings(struct tegra_mc *mc)
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static const char *const status_names[32] = {
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[ 1] = "External interrupt",
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[ 6] = "EMEM address decode error",
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[ 7] = "GART page fault",
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[ 8] = "Security violation",
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[ 9] = "EMEM arbitration error",
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[10] = "Page fault",
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@ -248,12 +449,13 @@ static const char *const error_names[8] = {
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static irqreturn_t tegra_mc_irq(int irq, void *data)
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{
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struct tegra_mc *mc = data;
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unsigned long status, mask;
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unsigned long status;
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unsigned int bit;
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/* mask all interrupts to avoid flooding */
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status = mc_readl(mc, MC_INTSTATUS);
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mask = mc_readl(mc, MC_INTMASK);
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status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
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if (!status)
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return IRQ_NONE;
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for_each_set_bit(bit, &status, 32) {
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const char *error = status_names[bit] ?: "unknown";
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@ -341,12 +543,78 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
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{
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struct tegra_mc *mc = data;
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unsigned long status;
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unsigned int bit;
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/* mask all interrupts to avoid flooding */
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status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
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if (!status)
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return IRQ_NONE;
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for_each_set_bit(bit, &status, 32) {
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const char *direction = "read", *secure = "";
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const char *error = status_names[bit];
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const char *client, *desc;
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phys_addr_t addr;
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u32 value, reg;
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u8 id, type;
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switch (BIT(bit)) {
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case MC_INT_DECERR_EMEM:
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reg = MC_DECERR_EMEM_OTHERS_STATUS;
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value = mc_readl(mc, reg);
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id = value & mc->soc->client_id_mask;
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desc = error_names[2];
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if (value & BIT(31))
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direction = "write";
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break;
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case MC_INT_INVALID_GART_PAGE:
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dev_err_ratelimited(mc->dev, "%s\n", error);
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continue;
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case MC_INT_SECURITY_VIOLATION:
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reg = MC_SECURITY_VIOLATION_STATUS;
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value = mc_readl(mc, reg);
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id = value & mc->soc->client_id_mask;
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type = (value & BIT(30)) ? 4 : 3;
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desc = error_names[type];
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secure = "secure ";
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if (value & BIT(31))
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direction = "write";
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break;
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default:
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continue;
|
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}
|
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client = mc->soc->clients[id].name;
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addr = mc_readl(mc, reg + sizeof(u32));
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dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
|
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client, secure, direction, &addr, error,
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desc);
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}
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/* clear interrupts */
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mc_writel(mc, status, MC_INTSTATUS);
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return IRQ_HANDLED;
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||||
}
|
||||
|
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static int tegra_mc_probe(struct platform_device *pdev)
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{
|
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const struct of_device_id *match;
|
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struct resource *res;
|
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struct tegra_mc *mc;
|
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u32 value;
|
||||
void *isr;
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int err;
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||||
|
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match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
|
||||
|
|
@ -358,6 +626,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
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return -ENOMEM;
|
||||
|
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platform_set_drvdata(pdev, mc);
|
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spin_lock_init(&mc->lock);
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||||
mc->soc = match->data;
|
||||
mc->dev = &pdev->dev;
|
||||
|
||||
|
|
@ -369,18 +638,32 @@ static int tegra_mc_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(mc->regs))
|
||||
return PTR_ERR(mc->regs);
|
||||
|
||||
mc->clk = devm_clk_get(&pdev->dev, "mc");
|
||||
if (IS_ERR(mc->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
|
||||
PTR_ERR(mc->clk));
|
||||
return PTR_ERR(mc->clk);
|
||||
}
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
if (mc->soc == &tegra20_mc_soc) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mc->regs2))
|
||||
return PTR_ERR(mc->regs2);
|
||||
|
||||
err = tegra_mc_setup_latency_allowance(mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
|
||||
err);
|
||||
return err;
|
||||
isr = tegra20_mc_irq;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
mc->clk = devm_clk_get(&pdev->dev, "mc");
|
||||
if (IS_ERR(mc->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
|
||||
PTR_ERR(mc->clk));
|
||||
return PTR_ERR(mc->clk);
|
||||
}
|
||||
|
||||
err = tegra_mc_setup_latency_allowance(mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
isr = tegra_mc_irq;
|
||||
}
|
||||
|
||||
err = tegra_mc_setup_timings(mc);
|
||||
|
|
@ -389,6 +672,31 @@ static int tegra_mc_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
err = tegra_mc_reset_setup(mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to register reset controller: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
mc->irq = platform_get_irq(pdev, 0);
|
||||
if (mc->irq < 0) {
|
||||
dev_err(&pdev->dev, "interrupt not specified\n");
|
||||
return mc->irq;
|
||||
}
|
||||
|
||||
WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
|
||||
|
||||
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
|
||||
|
||||
err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED,
|
||||
dev_name(&pdev->dev), mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
|
||||
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
|
||||
if (IS_ERR(mc->smmu)) {
|
||||
|
|
@ -398,28 +706,6 @@ static int tegra_mc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
mc->irq = platform_get_irq(pdev, 0);
|
||||
if (mc->irq < 0) {
|
||||
dev_err(&pdev->dev, "interrupt not specified\n");
|
||||
return mc->irq;
|
||||
}
|
||||
|
||||
err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
|
||||
dev_name(&pdev->dev), mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
|
||||
|
||||
value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
|
||||
|
||||
mc_writel(mc, value, MC_INTMASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,17 +14,39 @@
|
|||
|
||||
#include <soc/tegra/mc.h>
|
||||
|
||||
#define MC_INT_DECERR_MTS (1 << 16)
|
||||
#define MC_INT_SECERR_SEC (1 << 13)
|
||||
#define MC_INT_DECERR_VPR (1 << 12)
|
||||
#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
|
||||
#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
|
||||
#define MC_INT_ARBITRATION_EMEM (1 << 9)
|
||||
#define MC_INT_SECURITY_VIOLATION (1 << 8)
|
||||
#define MC_INT_INVALID_GART_PAGE (1 << 7)
|
||||
#define MC_INT_DECERR_EMEM (1 << 6)
|
||||
|
||||
static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
|
||||
{
|
||||
if (mc->regs2 && offset >= 0x24)
|
||||
return readl(mc->regs2 + offset - 0x3c);
|
||||
|
||||
return readl(mc->regs + offset);
|
||||
}
|
||||
|
||||
static inline void mc_writel(struct tegra_mc *mc, u32 value,
|
||||
unsigned long offset)
|
||||
{
|
||||
if (mc->regs2 && offset >= 0x24)
|
||||
return writel(value, mc->regs2 + offset - 0x3c);
|
||||
|
||||
writel(value, mc->regs + offset);
|
||||
}
|
||||
|
||||
extern const struct tegra_mc_reset_ops terga_mc_reset_ops_common;
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
extern const struct tegra_mc_soc tegra20_mc_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
extern const struct tegra_mc_soc tegra30_mc_soc;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -938,6 +938,34 @@ static const struct tegra_smmu_soc tegra114_smmu_soc = {
|
|||
.num_asids = 4,
|
||||
};
|
||||
|
||||
#define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
|
||||
{ \
|
||||
.name = #_name, \
|
||||
.id = TEGRA114_MC_RESET_##_name, \
|
||||
.control = _control, \
|
||||
.status = _status, \
|
||||
.bit = _bit, \
|
||||
}
|
||||
|
||||
static const struct tegra_mc_reset tegra114_mc_resets[] = {
|
||||
TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
|
||||
TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
|
||||
TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
|
||||
TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
|
||||
TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
|
||||
TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
|
||||
TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
|
||||
TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
|
||||
TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
|
||||
TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
|
||||
TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
|
||||
TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
|
||||
TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
|
||||
TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
|
||||
TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
|
||||
TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra114_mc_soc = {
|
||||
.clients = tegra114_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
|
||||
|
|
@ -945,4 +973,9 @@ const struct tegra_mc_soc tegra114_mc_soc = {
|
|||
.atom_size = 32,
|
||||
.client_id_mask = 0x7f,
|
||||
.smmu = &tegra114_smmu_soc,
|
||||
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
|
||||
MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga_mc_reset_ops_common,
|
||||
.resets = tegra114_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1012,6 +1012,42 @@ static const struct tegra_smmu_group_soc tegra124_groups[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
|
||||
{ \
|
||||
.name = #_name, \
|
||||
.id = TEGRA124_MC_RESET_##_name, \
|
||||
.control = _control, \
|
||||
.status = _status, \
|
||||
.bit = _bit, \
|
||||
}
|
||||
|
||||
static const struct tegra_mc_reset tegra124_mc_resets[] = {
|
||||
TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
|
||||
TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
|
||||
TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
|
||||
TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
|
||||
TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
|
||||
TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
|
||||
TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
|
||||
TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
|
||||
TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
|
||||
TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
|
||||
TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
|
||||
TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
|
||||
TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
|
||||
TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
|
||||
TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
|
||||
TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
|
||||
TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
|
||||
TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
|
||||
TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
|
||||
TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
|
||||
TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
|
||||
TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
|
||||
TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
|
||||
TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
static const struct tegra_smmu_soc tegra124_smmu_soc = {
|
||||
.clients = tegra124_mc_clients,
|
||||
|
|
@ -1035,6 +1071,12 @@ const struct tegra_mc_soc tegra124_mc_soc = {
|
|||
.smmu = &tegra124_smmu_soc,
|
||||
.emem_regs = tegra124_mc_emem_regs,
|
||||
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
|
||||
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga_mc_reset_ops_common,
|
||||
.resets = tegra124_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
|
||||
|
||||
|
|
@ -1059,5 +1101,11 @@ const struct tegra_mc_soc tegra132_mc_soc = {
|
|||
.atom_size = 32,
|
||||
.client_id_mask = 0x7f,
|
||||
.smmu = &tegra132_smmu_soc,
|
||||
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga_mc_reset_ops_common,
|
||||
.resets = tegra124_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/memory/tegra20-mc.h>
|
||||
|
||||
#include "mc.h"
|
||||
|
||||
static const struct tegra_mc_client tegra20_mc_clients[] = {
|
||||
{
|
||||
.id = 0x00,
|
||||
.name = "display0a",
|
||||
}, {
|
||||
.id = 0x01,
|
||||
.name = "display0ab",
|
||||
}, {
|
||||
.id = 0x02,
|
||||
.name = "display0b",
|
||||
}, {
|
||||
.id = 0x03,
|
||||
.name = "display0bb",
|
||||
}, {
|
||||
.id = 0x04,
|
||||
.name = "display0c",
|
||||
}, {
|
||||
.id = 0x05,
|
||||
.name = "display0cb",
|
||||
}, {
|
||||
.id = 0x06,
|
||||
.name = "display1b",
|
||||
}, {
|
||||
.id = 0x07,
|
||||
.name = "display1bb",
|
||||
}, {
|
||||
.id = 0x08,
|
||||
.name = "eppup",
|
||||
}, {
|
||||
.id = 0x09,
|
||||
.name = "g2pr",
|
||||
}, {
|
||||
.id = 0x0a,
|
||||
.name = "g2sr",
|
||||
}, {
|
||||
.id = 0x0b,
|
||||
.name = "mpeunifbr",
|
||||
}, {
|
||||
.id = 0x0c,
|
||||
.name = "viruv",
|
||||
}, {
|
||||
.id = 0x0d,
|
||||
.name = "avpcarm7r",
|
||||
}, {
|
||||
.id = 0x0e,
|
||||
.name = "displayhc",
|
||||
}, {
|
||||
.id = 0x0f,
|
||||
.name = "displayhcb",
|
||||
}, {
|
||||
.id = 0x10,
|
||||
.name = "fdcdrd",
|
||||
}, {
|
||||
.id = 0x11,
|
||||
.name = "g2dr",
|
||||
}, {
|
||||
.id = 0x12,
|
||||
.name = "host1xdmar",
|
||||
}, {
|
||||
.id = 0x13,
|
||||
.name = "host1xr",
|
||||
}, {
|
||||
.id = 0x14,
|
||||
.name = "idxsrd",
|
||||
}, {
|
||||
.id = 0x15,
|
||||
.name = "mpcorer",
|
||||
}, {
|
||||
.id = 0x16,
|
||||
.name = "mpe_ipred",
|
||||
}, {
|
||||
.id = 0x17,
|
||||
.name = "mpeamemrd",
|
||||
}, {
|
||||
.id = 0x18,
|
||||
.name = "mpecsrd",
|
||||
}, {
|
||||
.id = 0x19,
|
||||
.name = "ppcsahbdmar",
|
||||
}, {
|
||||
.id = 0x1a,
|
||||
.name = "ppcsahbslvr",
|
||||
}, {
|
||||
.id = 0x1b,
|
||||
.name = "texsrd",
|
||||
}, {
|
||||
.id = 0x1c,
|
||||
.name = "vdebsevr",
|
||||
}, {
|
||||
.id = 0x1d,
|
||||
.name = "vdember",
|
||||
}, {
|
||||
.id = 0x1e,
|
||||
.name = "vdemcer",
|
||||
}, {
|
||||
.id = 0x1f,
|
||||
.name = "vdetper",
|
||||
}, {
|
||||
.id = 0x20,
|
||||
.name = "eppu",
|
||||
}, {
|
||||
.id = 0x21,
|
||||
.name = "eppv",
|
||||
}, {
|
||||
.id = 0x22,
|
||||
.name = "eppy",
|
||||
}, {
|
||||
.id = 0x23,
|
||||
.name = "mpeunifbw",
|
||||
}, {
|
||||
.id = 0x24,
|
||||
.name = "viwsb",
|
||||
}, {
|
||||
.id = 0x25,
|
||||
.name = "viwu",
|
||||
}, {
|
||||
.id = 0x26,
|
||||
.name = "viwv",
|
||||
}, {
|
||||
.id = 0x27,
|
||||
.name = "viwy",
|
||||
}, {
|
||||
.id = 0x28,
|
||||
.name = "g2dw",
|
||||
}, {
|
||||
.id = 0x29,
|
||||
.name = "avpcarm7w",
|
||||
}, {
|
||||
.id = 0x2a,
|
||||
.name = "fdcdwr",
|
||||
}, {
|
||||
.id = 0x2b,
|
||||
.name = "host1xw",
|
||||
}, {
|
||||
.id = 0x2c,
|
||||
.name = "ispw",
|
||||
}, {
|
||||
.id = 0x2d,
|
||||
.name = "mpcorew",
|
||||
}, {
|
||||
.id = 0x2e,
|
||||
.name = "mpecswr",
|
||||
}, {
|
||||
.id = 0x2f,
|
||||
.name = "ppcsahbdmaw",
|
||||
}, {
|
||||
.id = 0x30,
|
||||
.name = "ppcsahbslvw",
|
||||
}, {
|
||||
.id = 0x31,
|
||||
.name = "vdebsevw",
|
||||
}, {
|
||||
.id = 0x32,
|
||||
.name = "vdembew",
|
||||
}, {
|
||||
.id = 0x33,
|
||||
.name = "vdetpmw",
|
||||
},
|
||||
};
|
||||
|
||||
#define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \
|
||||
{ \
|
||||
.name = #_name, \
|
||||
.id = TEGRA20_MC_RESET_##_name, \
|
||||
.control = _control, \
|
||||
.status = _status, \
|
||||
.reset = _reset, \
|
||||
.bit = _bit, \
|
||||
}
|
||||
|
||||
static const struct tegra_mc_reset tegra20_mc_resets[] = {
|
||||
TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
|
||||
TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
|
||||
TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
|
||||
TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
|
||||
TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
|
||||
TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
|
||||
TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
|
||||
TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
|
||||
TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
|
||||
TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
|
||||
TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
|
||||
TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
|
||||
TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
|
||||
TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
|
||||
TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
|
||||
};
|
||||
|
||||
static int terga20_mc_hotreset_assert(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&mc->lock, flags);
|
||||
|
||||
value = mc_readl(mc, rst->reset);
|
||||
mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
|
||||
|
||||
spin_unlock_irqrestore(&mc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int terga20_mc_hotreset_deassert(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&mc->lock, flags);
|
||||
|
||||
value = mc_readl(mc, rst->reset);
|
||||
mc_writel(mc, value | BIT(rst->bit), rst->reset);
|
||||
|
||||
spin_unlock_irqrestore(&mc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int terga20_mc_block_dma(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&mc->lock, flags);
|
||||
|
||||
value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
|
||||
mc_writel(mc, value, rst->control);
|
||||
|
||||
spin_unlock_irqrestore(&mc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool terga20_mc_dma_idling(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
return mc_readl(mc, rst->status) == 0;
|
||||
}
|
||||
|
||||
static int terga20_mc_reset_status(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
|
||||
}
|
||||
|
||||
static int terga20_mc_unblock_dma(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&mc->lock, flags);
|
||||
|
||||
value = mc_readl(mc, rst->control) | BIT(rst->bit);
|
||||
mc_writel(mc, value, rst->control);
|
||||
|
||||
spin_unlock_irqrestore(&mc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct tegra_mc_reset_ops terga20_mc_reset_ops = {
|
||||
.hotreset_assert = terga20_mc_hotreset_assert,
|
||||
.hotreset_deassert = terga20_mc_hotreset_deassert,
|
||||
.block_dma = terga20_mc_block_dma,
|
||||
.dma_idling = terga20_mc_dma_idling,
|
||||
.unblock_dma = terga20_mc_unblock_dma,
|
||||
.reset_status = terga20_mc_reset_status,
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra20_mc_soc = {
|
||||
.clients = tegra20_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
|
||||
.num_address_bits = 32,
|
||||
.client_id_mask = 0x3f,
|
||||
.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
|
||||
MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga20_mc_reset_ops,
|
||||
.resets = tegra20_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
|
||||
};
|
||||
|
|
@ -6,11 +6,6 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <dt-bindings/memory/tegra210-mc.h>
|
||||
|
||||
#include "mc.h"
|
||||
|
|
@ -1085,6 +1080,48 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = {
|
|||
.num_asids = 128,
|
||||
};
|
||||
|
||||
#define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
|
||||
{ \
|
||||
.name = #_name, \
|
||||
.id = TEGRA210_MC_RESET_##_name, \
|
||||
.control = _control, \
|
||||
.status = _status, \
|
||||
.bit = _bit, \
|
||||
}
|
||||
|
||||
static const struct tegra_mc_reset tegra210_mc_resets[] = {
|
||||
TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
|
||||
TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
|
||||
TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
|
||||
TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
|
||||
TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
|
||||
TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
|
||||
TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
|
||||
TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
|
||||
TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
|
||||
TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
|
||||
TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
|
||||
TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
|
||||
TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
|
||||
TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
|
||||
TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
|
||||
TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
|
||||
TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
|
||||
TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
|
||||
TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
|
||||
TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
|
||||
TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
|
||||
TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
|
||||
TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
|
||||
TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
|
||||
TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
|
||||
TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
|
||||
TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
|
||||
TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
|
||||
TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
|
||||
TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra210_mc_soc = {
|
||||
.clients = tegra210_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
|
||||
|
|
@ -1092,4 +1129,10 @@ const struct tegra_mc_soc tegra210_mc_soc = {
|
|||
.atom_size = 64,
|
||||
.client_id_mask = 0xff,
|
||||
.smmu = &tegra210_smmu_soc,
|
||||
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga_mc_reset_ops_common,
|
||||
.resets = tegra210_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -960,6 +960,36 @@ static const struct tegra_smmu_soc tegra30_smmu_soc = {
|
|||
.num_asids = 4,
|
||||
};
|
||||
|
||||
#define TEGRA30_MC_RESET(_name, _control, _status, _bit) \
|
||||
{ \
|
||||
.name = #_name, \
|
||||
.id = TEGRA30_MC_RESET_##_name, \
|
||||
.control = _control, \
|
||||
.status = _status, \
|
||||
.bit = _bit, \
|
||||
}
|
||||
|
||||
static const struct tegra_mc_reset tegra30_mc_resets[] = {
|
||||
TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
|
||||
TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
|
||||
TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
|
||||
TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
|
||||
TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
|
||||
TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
|
||||
TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
|
||||
TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
|
||||
TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
|
||||
TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
|
||||
TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
|
||||
TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
|
||||
TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
|
||||
TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
|
||||
TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
|
||||
TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
|
||||
TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
|
||||
TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra30_mc_soc = {
|
||||
.clients = tegra30_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
|
||||
|
|
@ -967,4 +997,9 @@ const struct tegra_mc_soc tegra30_mc_soc = {
|
|||
.atom_size = 16,
|
||||
.client_id_mask = 0x7f,
|
||||
.smmu = &tegra30_smmu_soc,
|
||||
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
|
||||
MC_INT_DECERR_EMEM,
|
||||
.reset_ops = &terga_mc_reset_ops_common,
|
||||
.resets = tegra30_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,254 +0,0 @@
|
|||
/*
|
||||
* Tegra20 Memory Controller
|
||||
*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/ratelimit.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define DRV_NAME "tegra20-mc"
|
||||
|
||||
#define MC_INTSTATUS 0x0
|
||||
#define MC_INTMASK 0x4
|
||||
|
||||
#define MC_INT_ERR_SHIFT 6
|
||||
#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
|
||||
#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
|
||||
#define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1)
|
||||
#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
|
||||
#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
|
||||
|
||||
#define MC_GART_ERROR_REQ 0x30
|
||||
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
|
||||
#define MC_SECURITY_VIOLATION_STATUS 0x74
|
||||
|
||||
#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
|
||||
|
||||
#define MC_CLIENT_ID_MASK 0x3f
|
||||
|
||||
#define NUM_MC_REG_BANKS 2
|
||||
|
||||
struct tegra20_mc {
|
||||
void __iomem *regs[NUM_MC_REG_BANKS];
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
if (offs < 0x24)
|
||||
val = readl(mc->regs[0] + offs);
|
||||
else if (offs < 0x400)
|
||||
val = readl(mc->regs[1] + offs - 0x3c);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs)
|
||||
{
|
||||
if (offs < 0x24)
|
||||
writel(val, mc->regs[0] + offs);
|
||||
else if (offs < 0x400)
|
||||
writel(val, mc->regs[1] + offs - 0x3c);
|
||||
}
|
||||
|
||||
static const char * const tegra20_mc_client[] = {
|
||||
"cbr_display0a",
|
||||
"cbr_display0ab",
|
||||
"cbr_display0b",
|
||||
"cbr_display0bb",
|
||||
"cbr_display0c",
|
||||
"cbr_display0cb",
|
||||
"cbr_display1b",
|
||||
"cbr_display1bb",
|
||||
"cbr_eppup",
|
||||
"cbr_g2pr",
|
||||
"cbr_g2sr",
|
||||
"cbr_mpeunifbr",
|
||||
"cbr_viruv",
|
||||
"csr_avpcarm7r",
|
||||
"csr_displayhc",
|
||||
"csr_displayhcb",
|
||||
"csr_fdcdrd",
|
||||
"csr_g2dr",
|
||||
"csr_host1xdmar",
|
||||
"csr_host1xr",
|
||||
"csr_idxsrd",
|
||||
"csr_mpcorer",
|
||||
"csr_mpe_ipred",
|
||||
"csr_mpeamemrd",
|
||||
"csr_mpecsrd",
|
||||
"csr_ppcsahbdmar",
|
||||
"csr_ppcsahbslvr",
|
||||
"csr_texsrd",
|
||||
"csr_vdebsevr",
|
||||
"csr_vdember",
|
||||
"csr_vdemcer",
|
||||
"csr_vdetper",
|
||||
"cbw_eppu",
|
||||
"cbw_eppv",
|
||||
"cbw_eppy",
|
||||
"cbw_mpeunifbw",
|
||||
"cbw_viwsb",
|
||||
"cbw_viwu",
|
||||
"cbw_viwv",
|
||||
"cbw_viwy",
|
||||
"ccw_g2dw",
|
||||
"csw_avpcarm7w",
|
||||
"csw_fdcdwr",
|
||||
"csw_host1xw",
|
||||
"csw_ispw",
|
||||
"csw_mpcorew",
|
||||
"csw_mpecswr",
|
||||
"csw_ppcsahbdmaw",
|
||||
"csw_ppcsahbslvw",
|
||||
"csw_vdebsevw",
|
||||
"csw_vdembew",
|
||||
"csw_vdetpmw",
|
||||
};
|
||||
|
||||
static void tegra20_mc_decode(struct tegra20_mc *mc, int n)
|
||||
{
|
||||
u32 addr, req;
|
||||
const char *client = "Unknown";
|
||||
int idx, cid;
|
||||
const struct reg_info {
|
||||
u32 offset;
|
||||
u32 write_bit; /* 0=READ, 1=WRITE */
|
||||
int cid_shift;
|
||||
char *message;
|
||||
} reg[] = {
|
||||
{
|
||||
.offset = MC_DECERR_EMEM_OTHERS_STATUS,
|
||||
.write_bit = 31,
|
||||
.message = "MC_DECERR",
|
||||
},
|
||||
{
|
||||
.offset = MC_GART_ERROR_REQ,
|
||||
.cid_shift = 1,
|
||||
.message = "MC_GART_ERR",
|
||||
|
||||
},
|
||||
{
|
||||
.offset = MC_SECURITY_VIOLATION_STATUS,
|
||||
.write_bit = 31,
|
||||
.message = "MC_SECURITY_ERR",
|
||||
},
|
||||
};
|
||||
|
||||
idx = n - MC_INT_ERR_SHIFT;
|
||||
if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) {
|
||||
dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
|
||||
BIT(n));
|
||||
return;
|
||||
}
|
||||
|
||||
req = mc_readl(mc, reg[idx].offset);
|
||||
cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK;
|
||||
if (cid < ARRAY_SIZE(tegra20_mc_client))
|
||||
client = tegra20_mc_client[cid];
|
||||
|
||||
addr = mc_readl(mc, reg[idx].offset + sizeof(u32));
|
||||
|
||||
dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s)\n",
|
||||
reg[idx].message, req, addr, client,
|
||||
(req & BIT(reg[idx].write_bit)) ? "write" : "read",
|
||||
(reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ?
|
||||
((req & SECURITY_VIOLATION_TYPE) ?
|
||||
"carveout" : "trustzone") : "");
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra20_mc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-mc", },
|
||||
{},
|
||||
};
|
||||
|
||||
static irqreturn_t tegra20_mc_isr(int irq, void *data)
|
||||
{
|
||||
u32 stat, mask, bit;
|
||||
struct tegra20_mc *mc = data;
|
||||
|
||||
stat = mc_readl(mc, MC_INTSTATUS);
|
||||
mask = mc_readl(mc, MC_INTMASK);
|
||||
mask &= stat;
|
||||
if (!mask)
|
||||
return IRQ_NONE;
|
||||
while ((bit = ffs(mask)) != 0) {
|
||||
tegra20_mc_decode(mc, bit - 1);
|
||||
mask &= ~BIT(bit - 1);
|
||||
}
|
||||
|
||||
mc_writel(mc, stat, MC_INTSTATUS);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int tegra20_mc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *irq;
|
||||
struct tegra20_mc *mc;
|
||||
int i, err;
|
||||
u32 intmask;
|
||||
|
||||
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
|
||||
if (!mc)
|
||||
return -ENOMEM;
|
||||
mc->dev = &pdev->dev;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
mc->regs[i] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mc->regs[i]))
|
||||
return PTR_ERR(mc->regs[i]);
|
||||
}
|
||||
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq)
|
||||
return -ENODEV;
|
||||
err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr,
|
||||
IRQF_SHARED, dev_name(&pdev->dev), mc);
|
||||
if (err)
|
||||
return -ENODEV;
|
||||
|
||||
platform_set_drvdata(pdev, mc);
|
||||
|
||||
intmask = MC_INT_INVALID_GART_PAGE |
|
||||
MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
|
||||
mc_writel(mc, intmask, MC_INTMASK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra20_mc_driver = {
|
||||
.probe = tegra20_mc_probe,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = tegra20_mc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(tegra20_mc_driver);
|
||||
|
||||
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra20 MC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
|
|
@ -23,4 +23,21 @@
|
|||
#define TEGRA_SWGROUP_EMUCIF 18
|
||||
#define TEGRA_SWGROUP_TSEC 19
|
||||
|
||||
#define TEGRA114_MC_RESET_AVPC 0
|
||||
#define TEGRA114_MC_RESET_DC 1
|
||||
#define TEGRA114_MC_RESET_DCB 2
|
||||
#define TEGRA114_MC_RESET_EPP 3
|
||||
#define TEGRA114_MC_RESET_2D 4
|
||||
#define TEGRA114_MC_RESET_HC 5
|
||||
#define TEGRA114_MC_RESET_HDA 6
|
||||
#define TEGRA114_MC_RESET_ISP 7
|
||||
#define TEGRA114_MC_RESET_MPCORE 8
|
||||
#define TEGRA114_MC_RESET_MPCORELP 9
|
||||
#define TEGRA114_MC_RESET_MPE 10
|
||||
#define TEGRA114_MC_RESET_3D 11
|
||||
#define TEGRA114_MC_RESET_3D2 12
|
||||
#define TEGRA114_MC_RESET_PPCS 13
|
||||
#define TEGRA114_MC_RESET_VDE 14
|
||||
#define TEGRA114_MC_RESET_VI 15
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,4 +29,29 @@
|
|||
#define TEGRA_SWGROUP_VIC 24
|
||||
#define TEGRA_SWGROUP_VI 25
|
||||
|
||||
#define TEGRA124_MC_RESET_AFI 0
|
||||
#define TEGRA124_MC_RESET_AVPC 1
|
||||
#define TEGRA124_MC_RESET_DC 2
|
||||
#define TEGRA124_MC_RESET_DCB 3
|
||||
#define TEGRA124_MC_RESET_HC 4
|
||||
#define TEGRA124_MC_RESET_HDA 5
|
||||
#define TEGRA124_MC_RESET_ISP2 6
|
||||
#define TEGRA124_MC_RESET_MPCORE 7
|
||||
#define TEGRA124_MC_RESET_MPCORELP 8
|
||||
#define TEGRA124_MC_RESET_MSENC 9
|
||||
#define TEGRA124_MC_RESET_PPCS 10
|
||||
#define TEGRA124_MC_RESET_SATA 11
|
||||
#define TEGRA124_MC_RESET_VDE 12
|
||||
#define TEGRA124_MC_RESET_VI 13
|
||||
#define TEGRA124_MC_RESET_VIC 14
|
||||
#define TEGRA124_MC_RESET_XUSB_HOST 15
|
||||
#define TEGRA124_MC_RESET_XUSB_DEV 16
|
||||
#define TEGRA124_MC_RESET_TSEC 17
|
||||
#define TEGRA124_MC_RESET_SDMMC1 18
|
||||
#define TEGRA124_MC_RESET_SDMMC2 19
|
||||
#define TEGRA124_MC_RESET_SDMMC3 20
|
||||
#define TEGRA124_MC_RESET_SDMMC4 21
|
||||
#define TEGRA124_MC_RESET_ISP2B 22
|
||||
#define TEGRA124_MC_RESET_GPU 23
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
|
||||
#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
|
||||
|
||||
#define TEGRA20_MC_RESET_AVPC 0
|
||||
#define TEGRA20_MC_RESET_DC 1
|
||||
#define TEGRA20_MC_RESET_DCB 2
|
||||
#define TEGRA20_MC_RESET_EPP 3
|
||||
#define TEGRA20_MC_RESET_2D 4
|
||||
#define TEGRA20_MC_RESET_HC 5
|
||||
#define TEGRA20_MC_RESET_ISP 6
|
||||
#define TEGRA20_MC_RESET_MPCORE 7
|
||||
#define TEGRA20_MC_RESET_MPEA 8
|
||||
#define TEGRA20_MC_RESET_MPEB 9
|
||||
#define TEGRA20_MC_RESET_MPEC 10
|
||||
#define TEGRA20_MC_RESET_3D 11
|
||||
#define TEGRA20_MC_RESET_PPCS 12
|
||||
#define TEGRA20_MC_RESET_VDE 13
|
||||
#define TEGRA20_MC_RESET_VI 14
|
||||
|
||||
#endif
|
||||
|
|
@ -34,4 +34,35 @@
|
|||
#define TEGRA_SWGROUP_ETR 29
|
||||
#define TEGRA_SWGROUP_TSECB 30
|
||||
|
||||
#define TEGRA210_MC_RESET_AFI 0
|
||||
#define TEGRA210_MC_RESET_AVPC 1
|
||||
#define TEGRA210_MC_RESET_DC 2
|
||||
#define TEGRA210_MC_RESET_DCB 3
|
||||
#define TEGRA210_MC_RESET_HC 4
|
||||
#define TEGRA210_MC_RESET_HDA 5
|
||||
#define TEGRA210_MC_RESET_ISP2 6
|
||||
#define TEGRA210_MC_RESET_MPCORE 7
|
||||
#define TEGRA210_MC_RESET_NVENC 8
|
||||
#define TEGRA210_MC_RESET_PPCS 9
|
||||
#define TEGRA210_MC_RESET_SATA 10
|
||||
#define TEGRA210_MC_RESET_VI 11
|
||||
#define TEGRA210_MC_RESET_VIC 12
|
||||
#define TEGRA210_MC_RESET_XUSB_HOST 13
|
||||
#define TEGRA210_MC_RESET_XUSB_DEV 14
|
||||
#define TEGRA210_MC_RESET_A9AVP 15
|
||||
#define TEGRA210_MC_RESET_TSEC 16
|
||||
#define TEGRA210_MC_RESET_SDMMC1 17
|
||||
#define TEGRA210_MC_RESET_SDMMC2 18
|
||||
#define TEGRA210_MC_RESET_SDMMC3 19
|
||||
#define TEGRA210_MC_RESET_SDMMC4 20
|
||||
#define TEGRA210_MC_RESET_ISP2B 21
|
||||
#define TEGRA210_MC_RESET_GPU 22
|
||||
#define TEGRA210_MC_RESET_NVDEC 23
|
||||
#define TEGRA210_MC_RESET_APE 24
|
||||
#define TEGRA210_MC_RESET_SE 25
|
||||
#define TEGRA210_MC_RESET_NVJPG 26
|
||||
#define TEGRA210_MC_RESET_AXIAP 27
|
||||
#define TEGRA210_MC_RESET_ETR 28
|
||||
#define TEGRA210_MC_RESET_TSECB 29
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,4 +22,23 @@
|
|||
#define TEGRA_SWGROUP_MPCORE 17
|
||||
#define TEGRA_SWGROUP_ISP 18
|
||||
|
||||
#define TEGRA30_MC_RESET_AFI 0
|
||||
#define TEGRA30_MC_RESET_AVPC 1
|
||||
#define TEGRA30_MC_RESET_DC 2
|
||||
#define TEGRA30_MC_RESET_DCB 3
|
||||
#define TEGRA30_MC_RESET_EPP 4
|
||||
#define TEGRA30_MC_RESET_2D 5
|
||||
#define TEGRA30_MC_RESET_HC 6
|
||||
#define TEGRA30_MC_RESET_HDA 7
|
||||
#define TEGRA30_MC_RESET_ISP 8
|
||||
#define TEGRA30_MC_RESET_MPCORE 9
|
||||
#define TEGRA30_MC_RESET_MPCORELP 10
|
||||
#define TEGRA30_MC_RESET_MPE 11
|
||||
#define TEGRA30_MC_RESET_3D 12
|
||||
#define TEGRA30_MC_RESET_3D2 13
|
||||
#define TEGRA30_MC_RESET_PPCS 14
|
||||
#define TEGRA30_MC_RESET_SATA 15
|
||||
#define TEGRA30_MC_RESET_VDE 16
|
||||
#define TEGRA30_MC_RESET_VI 17
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#ifndef __SOC_TEGRA_MC_H__
|
||||
#define __SOC_TEGRA_MC_H__
|
||||
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct clk;
|
||||
|
|
@ -95,6 +96,30 @@ static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
|
|||
}
|
||||
#endif
|
||||
|
||||
struct tegra_mc_reset {
|
||||
const char *name;
|
||||
unsigned long id;
|
||||
unsigned int control;
|
||||
unsigned int status;
|
||||
unsigned int reset;
|
||||
unsigned int bit;
|
||||
};
|
||||
|
||||
struct tegra_mc_reset_ops {
|
||||
int (*hotreset_assert)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
int (*hotreset_deassert)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
int (*block_dma)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
bool (*dma_idling)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
int (*unblock_dma)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
int (*reset_status)(struct tegra_mc *mc,
|
||||
const struct tegra_mc_reset *rst);
|
||||
};
|
||||
|
||||
struct tegra_mc_soc {
|
||||
const struct tegra_mc_client *clients;
|
||||
unsigned int num_clients;
|
||||
|
|
@ -108,12 +133,18 @@ struct tegra_mc_soc {
|
|||
u8 client_id_mask;
|
||||
|
||||
const struct tegra_smmu_soc *smmu;
|
||||
|
||||
u32 intmask;
|
||||
|
||||
const struct tegra_mc_reset_ops *reset_ops;
|
||||
const struct tegra_mc_reset *resets;
|
||||
unsigned int num_resets;
|
||||
};
|
||||
|
||||
struct tegra_mc {
|
||||
struct device *dev;
|
||||
struct tegra_smmu *smmu;
|
||||
void __iomem *regs;
|
||||
void __iomem *regs, *regs2;
|
||||
struct clk *clk;
|
||||
int irq;
|
||||
|
||||
|
|
@ -122,6 +153,10 @@ struct tegra_mc {
|
|||
|
||||
struct tegra_mc_timing *timings;
|
||||
unsigned int num_timings;
|
||||
|
||||
struct reset_controller_dev reset;
|
||||
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
|
||||
|
|
|
|||
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