ath5k: Minor EEPROM documentation updates
Here are some minor updates for EEPROM, mostly documentation and some small fixes which have no effect at the moment. - fixed_bias is not available for B mode. - AR5K_EEPROM_[RT]X_CHAIN_DIS is 3 bit. this is MIMO and will not be used in ath5k, but just to be correct. - AR5K_EEPROM_JAP_MID_EN added, and shift of following flags adapted. - added some documentation for EEPROM values and some comments. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Bruno Randolf
John W. Linville
Родитель
49a85d211a
Коммит
687c8ff12d
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@ -329,7 +329,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
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ee->ee_x_gain[mode] = (val >> 1) & 0xf;
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ee->ee_xpd[mode] = val & 0x1;
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if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
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if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
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mode != AR5K_EEPROM_MODE_11B)
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ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
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if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
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@ -339,6 +340,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
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if (mode == AR5K_EEPROM_MODE_11A)
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ee->ee_xr_power[mode] = val & 0x3f;
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else {
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/* b_DB_11[bg] and b_OB_11[bg] */
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ee->ee_ob[mode][0] = val & 0x7;
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ee->ee_db[mode][0] = (val >> 3) & 0x7;
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}
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@ -75,9 +75,9 @@
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#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
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#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
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#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
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#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
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#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
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#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
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#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz */
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#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for < 2W power consumption */
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#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
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#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
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#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */
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@ -98,7 +98,7 @@
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#define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
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#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
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#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
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#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) /* has 32KHz crystal for sleep mode */
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#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
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#define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6)
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@ -111,26 +111,27 @@
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#define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8)
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#define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff)
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#define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3)
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#define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3)
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#define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2: A) */
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#define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) /* modes supported by radio 1 (bit 1: G, bit 2: A) */
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#define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9)
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#define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1)
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#define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1)
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#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1)
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#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1)
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#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf)
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#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1)
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#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf)
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#define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) /* disable compression */
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#define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) /* disable AES */
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#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) /* disable fast frames */
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#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) /* disable bursting */
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#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */
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#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) /* enable heayy clipping */
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#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) /* key cache size. defaults to 128 */
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#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
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#define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8)
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#define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8)
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#define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1)
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#define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1)
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#define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1)
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#define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1)
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#define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1)
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#define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x7) /* MIMO chains disabled for TX bitmask */
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#define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x7) /* MIMO chains disabled for RX bitmask */
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#define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) /* 5.47-5.7GHz supported */
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#define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */
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#define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) /* Japan UNII2 band (5.25-5.35GHz) supported */
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#define AR5K_EEPROM_JAP_MID_EN (((_v) >> 9) & 0x1) /* Japan band from 5.47-5.7GHz supported */
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#define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 10) & 0x1) /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */
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#define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 11) & 0x1) /* Japan A mode enabled (using even channels) */
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/* calibration settings */
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#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
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@ -386,7 +387,49 @@ struct ath5k_edge_power {
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bool flag;
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};
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/* EEPROM calibration data */
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/**
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* struct ath5k_eeprom_info - EEPROM calibration data
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*
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* @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING
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* flags
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* @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?]
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* @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for
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* OFDM and CCK packets
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* @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK
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* (11Mbps) rate in G mode. 0.1dB steps
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* @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution
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*
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* @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path
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* @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path
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* @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control
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* @ee_switch_settling: RX/TX Switch settling time
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* @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps
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* @ee_ant_control: Antenna Control Settings
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* @ee_ob: Bias current for Output stage of PA
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* B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
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* A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
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* @ee_db: Bias current for Output stage of PA. see @ee_ob
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* @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame
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* to when the external LNA is activated
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* @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame
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* to when the external PA switch is deactivated
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* @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when
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* external PA switch is activated
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* @ee_thr_62: Clear Channel Assessment (CCA) sensitivity
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* (IEEE802.11a section 17.3.10.5 )
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* @ee_xlna_gain: Total gain of the LNA (information only)
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* @ee_xpd: Use external (1) or internal power detector
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* @ee_x_gain: Gain for external power detector output (differences in EEMAP
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* versions!)
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* @ee_i_gain: Initial gain value after reset
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* @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used
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*
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* @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals
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* @ee_noise_floor_thr: Noise floor threshold in 1dB steps
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* @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps
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* @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps
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* @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)
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*/
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struct ath5k_eeprom_info {
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/* Header information */
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@ -1974,7 +1974,7 @@
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#define AR5K_PHY_SETTLING 0x9844 /* Register Address */
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#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
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#define AR5K_PHY_SETTLING_AGC_S 0
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#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
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#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */
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#define AR5K_PHY_SETTLING_SWITCH_S 7
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/*
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