mfd: arizona: Add support for WM8998 and WM1814
Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Родитель
bc00d68f2f
Коммит
6887b042c5
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@ -1379,6 +1379,12 @@ config MFD_WM8997
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help
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Support for Wolfson Microelectronics WM8997 low power audio SoC
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config MFD_WM8998
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bool "Wolfson Microelectronics WM8998"
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depends on MFD_ARIZONA
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help
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Support for Wolfson Microelectronics WM8998 low power audio SoC
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config MFD_WM8400
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bool "Wolfson Microelectronics WM8400"
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select MFD_CORE
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@ -48,6 +48,9 @@ endif
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ifeq ($(CONFIG_MFD_WM8997),y)
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obj-$(CONFIG_MFD_ARIZONA) += wm8997-tables.o
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endif
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ifeq ($(CONFIG_MFD_WM8998),y)
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obj-$(CONFIG_MFD_ARIZONA) += wm8998-tables.o
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endif
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obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
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wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o
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wm831x-objs += wm831x-auxadc.o
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@ -146,17 +146,31 @@ static irqreturn_t arizona_underclocked(int irq, void *data)
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static irqreturn_t arizona_overclocked(int irq, void *data)
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{
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struct arizona *arizona = data;
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unsigned int val[2];
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unsigned int val[3];
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int ret;
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ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
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&val[0], 2);
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&val[0], 3);
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if (ret != 0) {
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dev_err(arizona->dev, "Failed to read overclock status: %d\n",
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ret);
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return IRQ_NONE;
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}
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switch (arizona->type) {
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case WM8998:
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case WM1814:
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/* Some bits are shifted on WM8998,
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* rearrange to match the standard bit layout
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*/
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val[0] = ((val[0] & 0x60e0) >> 1) |
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((val[0] & 0x1e00) >> 2) |
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(val[0] & 0x000f);
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break;
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default:
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break;
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}
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if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
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dev_err(arizona->dev, "PWM overclocked\n");
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if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
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@ -201,6 +215,9 @@ static irqreturn_t arizona_overclocked(int irq, void *data)
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if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
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dev_err(arizona->dev, "ISRC1 overclocked\n");
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if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS)
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dev_err(arizona->dev, "SPDIF overclocked\n");
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return IRQ_HANDLED;
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}
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@ -806,6 +823,8 @@ const struct of_device_id arizona_of_match[] = {
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{ .compatible = "wlf,wm5110", .data = (void *)WM5110 },
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{ .compatible = "wlf,wm8280", .data = (void *)WM8280 },
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{ .compatible = "wlf,wm8997", .data = (void *)WM8997 },
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{ .compatible = "wlf,wm8998", .data = (void *)WM8998 },
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{ .compatible = "wlf,wm1814", .data = (void *)WM1814 },
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{},
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};
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EXPORT_SYMBOL_GPL(arizona_of_match);
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@ -887,11 +906,28 @@ static const struct mfd_cell wm8997_devs[] = {
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},
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};
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static const struct mfd_cell wm8998_devs[] = {
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{
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.name = "arizona-extcon",
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.parent_supplies = wm5102_supplies,
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.num_parent_supplies = 1, /* We only need MICVDD */
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},
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{ .name = "arizona-gpio" },
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{ .name = "arizona-haptics" },
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{ .name = "arizona-pwm" },
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{
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.name = "wm8998-codec",
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.parent_supplies = wm5102_supplies,
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.num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
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},
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{ .name = "arizona-micsupp" },
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};
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int arizona_dev_init(struct arizona *arizona)
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{
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struct device *dev = arizona->dev;
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const char *type_name;
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unsigned int reg, val;
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unsigned int reg, val, mask;
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int (*apply_patch)(struct arizona *) = NULL;
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int ret, i;
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@ -911,6 +947,8 @@ int arizona_dev_init(struct arizona *arizona)
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case WM5110:
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case WM8280:
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case WM8997:
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case WM8998:
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case WM1814:
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for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
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arizona->core_supplies[i].supply
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= wm5102_core_supplies[i];
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@ -992,6 +1030,7 @@ int arizona_dev_init(struct arizona *arizona)
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switch (reg) {
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case 0x5102:
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case 0x5110:
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case 0x6349:
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case 0x8997:
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break;
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default:
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@ -1092,6 +1131,27 @@ int arizona_dev_init(struct arizona *arizona)
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}
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apply_patch = wm8997_patch;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8998
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case 0x6349:
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switch (arizona->type) {
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case WM8998:
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type_name = "WM8998";
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break;
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case WM1814:
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type_name = "WM1814";
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break;
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default:
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type_name = "WM8998";
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dev_err(arizona->dev, "WM8998 registered as %d\n",
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arizona->type);
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arizona->type = WM8998;
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}
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apply_patch = wm8998_patch;
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break;
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#endif
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default:
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dev_err(arizona->dev, "Unknown device ID %x\n", reg);
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@ -1208,14 +1268,38 @@ int arizona_dev_init(struct arizona *arizona)
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<< ARIZONA_IN1_DMIC_SUP_SHIFT;
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if (arizona->pdata.inmode[i] & ARIZONA_INMODE_DMIC)
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val |= 1 << ARIZONA_IN1_MODE_SHIFT;
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if (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
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val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT;
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switch (arizona->type) {
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case WM8998:
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case WM1814:
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regmap_update_bits(arizona->regmap,
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ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8),
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ARIZONA_IN1L_SRC_SE_MASK,
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(arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
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<< ARIZONA_IN1L_SRC_SE_SHIFT);
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regmap_update_bits(arizona->regmap,
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ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8),
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ARIZONA_IN1R_SRC_SE_MASK,
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(arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
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<< ARIZONA_IN1R_SRC_SE_SHIFT);
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mask = ARIZONA_IN1_DMIC_SUP_MASK |
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ARIZONA_IN1_MODE_MASK;
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break;
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default:
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if (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
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val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT;
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mask = ARIZONA_IN1_DMIC_SUP_MASK |
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ARIZONA_IN1_MODE_MASK |
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ARIZONA_IN1_SINGLE_ENDED_MASK;
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break;
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}
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regmap_update_bits(arizona->regmap,
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ARIZONA_IN1L_CONTROL + (i * 8),
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ARIZONA_IN1_DMIC_SUP_MASK |
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ARIZONA_IN1_MODE_MASK |
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ARIZONA_IN1_SINGLE_ENDED_MASK, val);
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mask, val);
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}
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for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
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@ -1271,6 +1355,11 @@ int arizona_dev_init(struct arizona *arizona)
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ret = mfd_add_devices(arizona->dev, -1, wm8997_devs,
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ARRAY_SIZE(wm8997_devs), NULL, 0, NULL);
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break;
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case WM8998:
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case WM1814:
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ret = mfd_add_devices(arizona->dev, -1, wm8998_devs,
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ARRAY_SIZE(wm8998_devs), NULL, 0, NULL);
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break;
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}
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if (ret != 0) {
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@ -52,6 +52,12 @@ static int arizona_i2c_probe(struct i2c_client *i2c,
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case WM8997:
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regmap_config = &wm8997_i2c_regmap;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8998
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case WM8998:
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case WM1814:
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regmap_config = &wm8998_i2c_regmap;
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break;
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#endif
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default:
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dev_err(&i2c->dev, "Unknown device type %ld\n",
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@ -90,6 +96,8 @@ static const struct i2c_device_id arizona_i2c_id[] = {
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{ "wm5110", WM5110 },
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{ "wm8280", WM8280 },
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{ "wm8997", WM8997 },
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{ "wm8998", WM8998 },
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{ "wm1814", WM1814 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, arizona_i2c_id);
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@ -234,6 +234,15 @@ int arizona_irq_init(struct arizona *arizona)
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arizona->ctrlif_error = false;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8998
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case WM8998:
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case WM1814:
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aod = &wm8998_aod;
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irq = &wm8998_irq;
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arizona->ctrlif_error = false;
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break;
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#endif
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default:
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BUG_ON("Unknown Arizona class device" == NULL);
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return -EINVAL;
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@ -27,6 +27,8 @@ extern const struct regmap_config wm5110_spi_regmap;
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extern const struct regmap_config wm8997_i2c_regmap;
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extern const struct regmap_config wm8998_i2c_regmap;
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extern const struct dev_pm_ops arizona_pm_ops;
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extern const struct of_device_id arizona_of_match[];
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@ -41,6 +43,9 @@ extern const struct regmap_irq_chip wm5110_revd_irq;
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extern const struct regmap_irq_chip wm8997_aod;
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extern const struct regmap_irq_chip wm8997_irq;
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extern struct regmap_irq_chip wm8998_aod;
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extern struct regmap_irq_chip wm8998_irq;
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int arizona_dev_init(struct arizona *arizona);
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int arizona_dev_exit(struct arizona *arizona);
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int arizona_irq_init(struct arizona *arizona);
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -25,6 +25,8 @@ enum arizona_type {
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WM5110 = 2,
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WM8997 = 3,
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WM8280 = 4,
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WM8998 = 5,
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WM1814 = 6,
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};
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#define ARIZONA_IRQ_GP1 0
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@ -165,6 +167,7 @@ static inline int wm5102_patch(struct arizona *arizona)
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int wm5110_patch(struct arizona *arizona);
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int wm8997_patch(struct arizona *arizona);
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int wm8998_patch(struct arizona *arizona);
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extern int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
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bool mandatory);
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@ -162,6 +162,8 @@ struct arizona_pdata {
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/**
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* Mode of input structures
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* One of the ARIZONA_INMODE_xxx values
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* wm5102/wm5110/wm8280/wm8997: [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4
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* wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B
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*/
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int inmode[ARIZONA_MAX_INPUT];
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@ -139,6 +139,7 @@
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#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7
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#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8
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#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9
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#define ARIZONA_MIC_DETECT_4 0x2AB
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#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
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#define ARIZONA_ISOLATION_CONTROL 0x2CB
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#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
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@ -225,14 +226,18 @@
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#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
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#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
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#define ARIZONA_DRE_ENABLE 0x440
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#define ARIZONA_DRE_CONTROL_1 0x441
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#define ARIZONA_DRE_CONTROL_2 0x442
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#define ARIZONA_DRE_CONTROL_3 0x443
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#define ARIZONA_EDRE_ENABLE 0x448
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#define ARIZONA_DAC_AEC_CONTROL_1 0x450
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#define ARIZONA_DAC_AEC_CONTROL_2 0x451
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#define ARIZONA_NOISE_GATE_CONTROL 0x458
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#define ARIZONA_PDM_SPK1_CTRL_1 0x490
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#define ARIZONA_PDM_SPK1_CTRL_2 0x491
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#define ARIZONA_PDM_SPK2_CTRL_1 0x492
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#define ARIZONA_PDM_SPK2_CTRL_2 0x493
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#define ARIZONA_HP_TEST_CTRL_13 0x49A
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#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0
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#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1
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#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2
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@ -310,6 +315,10 @@
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#define ARIZONA_AIF3_TX_ENABLES 0x599
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#define ARIZONA_AIF3_RX_ENABLES 0x59A
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#define ARIZONA_AIF3_FORCE_WRITE 0x59B
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#define ARIZONA_SPD1_TX_CONTROL 0x5C2
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#define ARIZONA_SPD1_TX_CHANNEL_STATUS_1 0x5C3
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#define ARIZONA_SPD1_TX_CHANNEL_STATUS_2 0x5C4
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#define ARIZONA_SPD1_TX_CHANNEL_STATUS_3 0x5C5
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#define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
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#define ARIZONA_SLIMBUS_RATES_1 0x5E5
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#define ARIZONA_SLIMBUS_RATES_2 0x5E6
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@ -643,6 +652,10 @@
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#define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
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#define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
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#define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
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#define ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE 0x800
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#define ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME 0x801
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#define ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE 0x808
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#define ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME 0x809
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#define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
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#define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
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#define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
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@ -868,6 +881,7 @@
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#define ARIZONA_GPIO5_CTRL 0xC04
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#define ARIZONA_IRQ_CTRL_1 0xC0F
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#define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
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#define ARIZONA_GP_SWITCH_1 0xC18
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#define ARIZONA_MISC_PAD_CTRL_1 0xC20
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#define ARIZONA_MISC_PAD_CTRL_2 0xC21
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#define ARIZONA_MISC_PAD_CTRL_3 0xC22
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@ -1169,6 +1183,13 @@
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#define ARIZONA_DSP4_SCRATCH_1 0x1441
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#define ARIZONA_DSP4_SCRATCH_2 0x1442
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#define ARIZONA_DSP4_SCRATCH_3 0x1443
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#define ARIZONA_FRF_COEFF_1 0x1700
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#define ARIZONA_FRF_COEFF_2 0x1701
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#define ARIZONA_FRF_COEFF_3 0x1702
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#define ARIZONA_FRF_COEFF_4 0x1703
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#define ARIZONA_V2_DAC_COMP_1 0x1704
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#define ARIZONA_V2_DAC_COMP_2 0x1705
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/*
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* Field Definitions.
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@ -2325,6 +2346,9 @@
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#define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
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#define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
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#define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
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#define WM8998_HP_RATE_MASK 0x0006 /* HP_RATE - [2:1] */
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#define WM8998_HP_RATE_SHIFT 1 /* HP_RATE - [2:1] */
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#define WM8998_HP_RATE_WIDTH 2 /* HP_RATE - [2:1] */
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#define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
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#define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
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#define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
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@ -2412,6 +2436,16 @@
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#define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
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#define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
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/*
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* R683 (0x2AB) - Mic Detect 4
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*/
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#define ARIZONA_MICDET_ADCVAL_DIFF_MASK 0xFF00 /* MICDET_ADCVAL_DIFF - [15:8] */
|
||||
#define ARIZONA_MICDET_ADCVAL_DIFF_SHIFT 8 /* MICDET_ADCVAL_DIFF - [15:8] */
|
||||
#define ARIZONA_MICDET_ADCVAL_DIFF_WIDTH 8 /* MICDET_ADCVAL_DIFF - [15:8] */
|
||||
#define ARIZONA_MICDET_ADCVAL_MASK 0x007F /* MICDET_ADCVAL - [15:8] */
|
||||
#define ARIZONA_MICDET_ADCVAL_SHIFT 0 /* MICDET_ADCVAL - [15:8] */
|
||||
#define ARIZONA_MICDET_ADCVAL_WIDTH 7 /* MICDET_ADCVAL - [15:8] */
|
||||
|
||||
/*
|
||||
* R707 (0x2C3) - Mic noise mix control 1
|
||||
*/
|
||||
|
@ -2528,6 +2562,12 @@
|
|||
/*
|
||||
* R785 (0x311) - ADC Digital Volume 1L
|
||||
*/
|
||||
#define ARIZONA_IN1L_SRC_MASK 0x4000 /* IN1L_SRC - [14] */
|
||||
#define ARIZONA_IN1L_SRC_SHIFT 14 /* IN1L_SRC - [14] */
|
||||
#define ARIZONA_IN1L_SRC_WIDTH 1 /* IN1L_SRC - [14] */
|
||||
#define ARIZONA_IN1L_SRC_SE_MASK 0x2000 /* IN1L_SRC - [13] */
|
||||
#define ARIZONA_IN1L_SRC_SE_SHIFT 13 /* IN1L_SRC - [13] */
|
||||
#define ARIZONA_IN1L_SRC_SE_WIDTH 1 /* IN1L_SRC - [13] */
|
||||
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
|
||||
|
@ -2560,6 +2600,12 @@
|
|||
/*
|
||||
* R789 (0x315) - ADC Digital Volume 1R
|
||||
*/
|
||||
#define ARIZONA_IN1R_SRC_MASK 0x4000 /* IN1R_SRC - [14] */
|
||||
#define ARIZONA_IN1R_SRC_SHIFT 14 /* IN1R_SRC - [14] */
|
||||
#define ARIZONA_IN1R_SRC_WIDTH 1 /* IN1R_SRC - [14] */
|
||||
#define ARIZONA_IN1R_SRC_SE_MASK 0x2000 /* IN1R_SRC - [13] */
|
||||
#define ARIZONA_IN1R_SRC_SE_SHIFT 13 /* IN1R_SRC - [13] */
|
||||
#define ARIZONA_IN1R_SRC_SE_WIDTH 1 /* IN1R_SRC - [13] */
|
||||
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
|
||||
|
@ -2604,6 +2650,12 @@
|
|||
/*
|
||||
* R793 (0x319) - ADC Digital Volume 2L
|
||||
*/
|
||||
#define ARIZONA_IN2L_SRC_MASK 0x4000 /* IN2L_SRC - [14] */
|
||||
#define ARIZONA_IN2L_SRC_SHIFT 14 /* IN2L_SRC - [14] */
|
||||
#define ARIZONA_IN2L_SRC_WIDTH 1 /* IN2L_SRC - [14] */
|
||||
#define ARIZONA_IN2L_SRC_SE_MASK 0x2000 /* IN2L_SRC - [13] */
|
||||
#define ARIZONA_IN2L_SRC_SE_SHIFT 13 /* IN2L_SRC - [13] */
|
||||
#define ARIZONA_IN2L_SRC_SE_WIDTH 1 /* IN2L_SRC - [13] */
|
||||
#define ARIZONA_IN_VU 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
|
||||
#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
|
||||
|
@ -3411,12 +3463,46 @@
|
|||
#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */
|
||||
#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
|
||||
|
||||
/*
|
||||
* R1088 (0x440) - DRE Enable (WM8998)
|
||||
*/
|
||||
#define WM8998_DRE3L_ENA 0x0020 /* DRE3L_ENA */
|
||||
#define WM8998_DRE3L_ENA_MASK 0x0020 /* DRE3L_ENA */
|
||||
#define WM8998_DRE3L_ENA_SHIFT 5 /* DRE3L_ENA */
|
||||
#define WM8998_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */
|
||||
#define WM8998_DRE2L_ENA 0x0008 /* DRE2L_ENA */
|
||||
#define WM8998_DRE2L_ENA_MASK 0x0008 /* DRE2L_ENA */
|
||||
#define WM8998_DRE2L_ENA_SHIFT 3 /* DRE2L_ENA */
|
||||
#define WM8998_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */
|
||||
#define WM8998_DRE2R_ENA 0x0004 /* DRE2R_ENA */
|
||||
#define WM8998_DRE2R_ENA_MASK 0x0004 /* DRE2R_ENA */
|
||||
#define WM8998_DRE2R_ENA_SHIFT 2 /* DRE2R_ENA */
|
||||
#define WM8998_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */
|
||||
#define WM8998_DRE1L_ENA 0x0002 /* DRE1L_ENA */
|
||||
#define WM8998_DRE1L_ENA_MASK 0x0002 /* DRE1L_ENA */
|
||||
#define WM8998_DRE1L_ENA_SHIFT 1 /* DRE1L_ENA */
|
||||
#define WM8998_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
|
||||
#define WM8998_DRE1R_ENA 0x0001 /* DRE1R_ENA */
|
||||
#define WM8998_DRE1R_ENA_MASK 0x0001 /* DRE1R_ENA */
|
||||
#define WM8998_DRE1R_ENA_SHIFT 0 /* DRE1R_ENA */
|
||||
#define WM8998_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */
|
||||
|
||||
/*
|
||||
* R1089 (0x441) - DRE Control 1
|
||||
*/
|
||||
#define ARIZONA_DRE_ENV_TC_FAST_MASK 0x0F00 /* DRE_ENV_TC_FAST - [11:8] */
|
||||
#define ARIZONA_DRE_ENV_TC_FAST_SHIFT 8 /* DRE_ENV_TC_FAST - [11:8] */
|
||||
#define ARIZONA_DRE_ENV_TC_FAST_WIDTH 4 /* DRE_ENV_TC_FAST - [11:8] */
|
||||
|
||||
/*
|
||||
* R1090 (0x442) - DRE Control 2
|
||||
*/
|
||||
#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */
|
||||
#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */
|
||||
#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */
|
||||
#define ARIZONA_DRE_ALOG_VOL_DELAY_MASK 0x000F /* DRE_ALOG_VOL_DELAY - [3:0] */
|
||||
#define ARIZONA_DRE_ALOG_VOL_DELAY_SHIFT 0 /* DRE_ALOG_VOL_DELAY - [3:0] */
|
||||
#define ARIZONA_DRE_ALOG_VOL_DELAY_WIDTH 4 /* DRE_ALOG_VOL_DELAY - [3:0] */
|
||||
|
||||
/*
|
||||
* R1091 (0x443) - DRE Control 3
|
||||
|
@ -3428,6 +3514,49 @@
|
|||
#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */
|
||||
#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */
|
||||
|
||||
/* R486 (0x448) - EDRE_Enable
|
||||
*/
|
||||
#define ARIZONA_EDRE_OUT4L_THR2_ENA 0x0200 /* EDRE_OUT4L_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR2_ENA_MASK 0x0200 /* EDRE_OUT4L_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR2_ENA_SHIFT 9 /* EDRE_OUT4L_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR2_ENA_WIDTH 1 /* EDRE_OUT4L_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR2_ENA 0x0100 /* EDRE_OUT4R_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR2_ENA_MASK 0x0100 /* EDRE_OUT4R_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR2_ENA_SHIFT 8 /* EDRE_OUT4R_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR2_ENA_WIDTH 1 /* EDRE_OUT4R_THR2_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR1_ENA 0x0080 /* EDRE_OUT4L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR1_ENA_MASK 0x0080 /* EDRE_OUT4L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR1_ENA_SHIFT 7 /* EDRE_OUT4L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4L_THR1_ENA_WIDTH 1 /* EDRE_OUT4L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR1_ENA 0x0040 /* EDRE_OUT4R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR1_ENA_MASK 0x0040 /* EDRE_OUT4R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR1_ENA_SHIFT 6 /* EDRE_OUT4R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT4R_THR1_ENA_WIDTH 1 /* EDRE_OUT4R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3L_THR1_ENA 0x0020 /* EDRE_OUT3L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3L_THR1_ENA_MASK 0x0020 /* EDRE_OUT3L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3L_THR1_ENA_SHIFT 5 /* EDRE_OUT3L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3L_THR1_ENA_WIDTH 1 /* EDRE_OUT3L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3R_THR1_ENA 0x0010 /* EDRE_OUT3R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3R_THR1_ENA_MASK 0x0010 /* EDRE_OUT3R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3R_THR1_ENA_SHIFT 4 /* EDRE_OUT3R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT3R_THR1_ENA_WIDTH 1 /* EDRE_OUT3R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2L_THR1_ENA 0x0008 /* EDRE_OUT2L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2L_THR1_ENA_MASK 0x0008 /* EDRE_OUT2L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2L_THR1_ENA_SHIFT 3 /* EDRE_OUT2L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2L_THR1_ENA_WIDTH 1 /* EDRE_OUT2L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2R_THR1_ENA 0x0004 /* EDRE_OUT2R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2R_THR1_ENA_MASK 0x0004 /* EDRE_OUT2R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2R_THR1_ENA_SHIFT 2 /* EDRE_OUT2R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT2R_THR1_ENA_WIDTH 1 /* EDRE_OUT2R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1L_THR1_ENA 0x0002 /* EDRE_OUT1L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1L_THR1_ENA_MASK 0x0002 /* EDRE_OUT1L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1L_THR1_ENA_SHIFT 1 /* EDRE_OUT1L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1L_THR1_ENA_WIDTH 1 /* EDRE_OUT1L_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1R_THR1_ENA 0x0001 /* EDRE_OUT1R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1R_THR1_ENA_MASK 0x0001 /* EDRE_OUT1R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1R_THR1_ENA_SHIFT 0 /* EDRE_OUT1R_THR1_ENA */
|
||||
#define ARIZONA_EDRE_OUT1R_THR1_ENA_WIDTH 1 /* EDRE_OUT1R_THR1_ENA */
|
||||
|
||||
/*
|
||||
* R1104 (0x450) - DAC AEC Control 1
|
||||
*/
|
||||
|
@ -4307,6 +4436,86 @@
|
|||
#define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
|
||||
#define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
|
||||
|
||||
/*
|
||||
* R1474 (0x5C2) - SPD1 TX Control
|
||||
*/
|
||||
#define ARIZONA_SPD1_VAL2 0x2000 /* SPD1_VAL2 */
|
||||
#define ARIZONA_SPD1_VAL2_MASK 0x2000 /* SPD1_VAL2 */
|
||||
#define ARIZONA_SPD1_VAL2_SHIFT 13 /* SPD1_VAL2 */
|
||||
#define ARIZONA_SPD1_VAL2_WIDTH 1 /* SPD1_VAL2 */
|
||||
#define ARIZONA_SPD1_VAL1 0x1000 /* SPD1_VAL1 */
|
||||
#define ARIZONA_SPD1_VAL1_MASK 0x1000 /* SPD1_VAL1 */
|
||||
#define ARIZONA_SPD1_VAL1_SHIFT 12 /* SPD1_VAL1 */
|
||||
#define ARIZONA_SPD1_VAL1_WIDTH 1 /* SPD1_VAL1 */
|
||||
#define ARIZONA_SPD1_RATE_MASK 0x00F0 /* SPD1_RATE */
|
||||
#define ARIZONA_SPD1_RATE_SHIFT 4 /* SPD1_RATE */
|
||||
#define ARIZONA_SPD1_RATE_WIDTH 4 /* SPD1_RATE */
|
||||
#define ARIZONA_SPD1_ENA 0x0001 /* SPD1_ENA */
|
||||
#define ARIZONA_SPD1_ENA_MASK 0x0001 /* SPD1_ENA */
|
||||
#define ARIZONA_SPD1_ENA_SHIFT 0 /* SPD1_ENA */
|
||||
#define ARIZONA_SPD1_ENA_WIDTH 1 /* SPD1_ENA */
|
||||
|
||||
/*
|
||||
* R1475 (0x5C3) - SPD1 TX Channel Status 1
|
||||
*/
|
||||
#define ARIZONA_SPD1_CATCODE_MASK 0xFF00 /* SPD1_CATCODE */
|
||||
#define ARIZONA_SPD1_CATCODE_SHIFT 8 /* SPD1_CATCODE */
|
||||
#define ARIZONA_SPD1_CATCODE_WIDTH 8 /* SPD1_CATCODE */
|
||||
#define ARIZONA_SPD1_CHSTMODE_MASK 0x00C0 /* SPD1_CHSTMODE */
|
||||
#define ARIZONA_SPD1_CHSTMODE_SHIFT 6 /* SPD1_CHSTMODE */
|
||||
#define ARIZONA_SPD1_CHSTMODE_WIDTH 2 /* SPD1_CHSTMODE */
|
||||
#define ARIZONA_SPD1_PREEMPH_MASK 0x0038 /* SPD1_PREEMPH */
|
||||
#define ARIZONA_SPD1_PREEMPH_SHIFT 3 /* SPD1_PREEMPH */
|
||||
#define ARIZONA_SPD1_PREEMPH_WIDTH 3 /* SPD1_PREEMPH */
|
||||
#define ARIZONA_SPD1_NOCOPY 0x0004 /* SPD1_NOCOPY */
|
||||
#define ARIZONA_SPD1_NOCOPY_MASK 0x0004 /* SPD1_NOCOPY */
|
||||
#define ARIZONA_SPD1_NOCOPY_SHIFT 2 /* SPD1_NOCOPY */
|
||||
#define ARIZONA_SPD1_NOCOPY_WIDTH 1 /* SPD1_NOCOPY */
|
||||
#define ARIZONA_SPD1_NOAUDIO 0x0002 /* SPD1_NOAUDIO */
|
||||
#define ARIZONA_SPD1_NOAUDIO_MASK 0x0002 /* SPD1_NOAUDIO */
|
||||
#define ARIZONA_SPD1_NOAUDIO_SHIFT 1 /* SPD1_NOAUDIO */
|
||||
#define ARIZONA_SPD1_NOAUDIO_WIDTH 1 /* SPD1_NOAUDIO */
|
||||
#define ARIZONA_SPD1_PRO 0x0001 /* SPD1_PRO */
|
||||
#define ARIZONA_SPD1_PRO_MASK 0x0001 /* SPD1_PRO */
|
||||
#define ARIZONA_SPD1_PRO_SHIFT 0 /* SPD1_PRO */
|
||||
#define ARIZONA_SPD1_PRO_WIDTH 1 /* SPD1_PRO */
|
||||
|
||||
/*
|
||||
* R1475 (0x5C4) - SPD1 TX Channel Status 2
|
||||
*/
|
||||
#define ARIZONA_SPD1_FREQ_MASK 0xF000 /* SPD1_FREQ */
|
||||
#define ARIZONA_SPD1_FREQ_SHIFT 12 /* SPD1_FREQ */
|
||||
#define ARIZONA_SPD1_FREQ_WIDTH 4 /* SPD1_FREQ */
|
||||
#define ARIZONA_SPD1_CHNUM2_MASK 0x0F00 /* SPD1_CHNUM2 */
|
||||
#define ARIZONA_SPD1_CHNUM2_SHIFT 8 /* SPD1_CHNUM2 */
|
||||
#define ARIZONA_SPD1_CHNUM2_WIDTH 4 /* SPD1_CHNUM2 */
|
||||
#define ARIZONA_SPD1_CHNUM1_MASK 0x00F0 /* SPD1_CHNUM1 */
|
||||
#define ARIZONA_SPD1_CHNUM1_SHIFT 4 /* SPD1_CHNUM1 */
|
||||
#define ARIZONA_SPD1_CHNUM1_WIDTH 4 /* SPD1_CHNUM1 */
|
||||
#define ARIZONA_SPD1_SRCNUM_MASK 0x000F /* SPD1_SRCNUM */
|
||||
#define ARIZONA_SPD1_SRCNUM_SHIFT 0 /* SPD1_SRCNUM */
|
||||
#define ARIZONA_SPD1_SRCNUM_WIDTH 4 /* SPD1_SRCNUM */
|
||||
|
||||
/*
|
||||
* R1475 (0x5C5) - SPD1 TX Channel Status 3
|
||||
*/
|
||||
#define ARIZONA_SPD1_ORGSAMP_MASK 0x0F00 /* SPD1_ORGSAMP */
|
||||
#define ARIZONA_SPD1_ORGSAMP_SHIFT 8 /* SPD1_ORGSAMP */
|
||||
#define ARIZONA_SPD1_ORGSAMP_WIDTH 4 /* SPD1_ORGSAMP */
|
||||
#define ARIZONA_SPD1_TXWL_MASK 0x00E0 /* SPD1_TXWL */
|
||||
#define ARIZONA_SPD1_TXWL_SHIFT 5 /* SPD1_TXWL */
|
||||
#define ARIZONA_SPD1_TXWL_WIDTH 3 /* SPD1_TXWL */
|
||||
#define ARIZONA_SPD1_MAXWL 0x0010 /* SPD1_MAXWL */
|
||||
#define ARIZONA_SPD1_MAXWL_MASK 0x0010 /* SPD1_MAXWL */
|
||||
#define ARIZONA_SPD1_MAXWL_SHIFT 4 /* SPD1_MAXWL */
|
||||
#define ARIZONA_SPD1_MAXWL_WIDTH 1 /* SPD1_MAXWL */
|
||||
#define ARIZONA_SPD1_CS31_30_MASK 0x000C /* SPD1_CS31_30 */
|
||||
#define ARIZONA_SPD1_CS31_30_SHIFT 2 /* SPD1_CS31_30 */
|
||||
#define ARIZONA_SPD1_CS31_30_WIDTH 2 /* SPD1_CS31_30 */
|
||||
#define ARIZONA_SPD1_CLKACU_MASK 0x0003 /* SPD1_CLKACU */
|
||||
#define ARIZONA_SPD1_CLKACU_SHIFT 2 /* SPD1_CLKACU */
|
||||
#define ARIZONA_SPD1_CLKACU_WIDTH 0 /* SPD1_CLKACU */
|
||||
|
||||
/*
|
||||
* R1507 (0x5E3) - SLIMbus Framer Ref Gear
|
||||
*/
|
||||
|
@ -4561,6 +4770,13 @@
|
|||
#define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
|
||||
#define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
|
||||
|
||||
/*
|
||||
* R3096 (0xC18) - GP Switch 1
|
||||
*/
|
||||
#define ARIZONA_SW1_MODE_MASK 0x0003 /* SW1_MODE - [1:0] */
|
||||
#define ARIZONA_SW1_MODE_SHIFT 0 /* SW1_MODE - [1:0] */
|
||||
#define ARIZONA_SW1_MODE_WIDTH 2 /* SW1_MODE - [1:0] */
|
||||
|
||||
/*
|
||||
* R3104 (0xC20) - Misc Pad Ctrl 1
|
||||
*/
|
||||
|
@ -6301,6 +6517,10 @@
|
|||
/*
|
||||
* R3366 (0xD26) - Interrupt Raw Status 8
|
||||
*/
|
||||
#define ARIZONA_SPDIF_OVERCLOCKED_STS 0x8000 /* SPDIF_OVERCLOCKED_STS */
|
||||
#define ARIZONA_SPDIF_OVERCLOCKED_STS_MASK 0x8000 /* SPDIF_OVERCLOCKED_STS */
|
||||
#define ARIZONA_SPDIF_OVERCLOCKED_STS_SHIFT 15 /* SPDIF_OVERCLOCKED_STS */
|
||||
#define ARIZONA_SPDIF_OVERCLOCKED_STS_WIDTH 1 /* SPDIF_OVERCLOCKED_STS */
|
||||
#define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */
|
||||
|
|
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