cxgb4: Add code to dump SGE registers when hitting idma hangs
Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kumar Sanghvi
David S. Miller
Родитель
92ddcc7b8f
Коммит
68bce1922f
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@ -1032,4 +1032,5 @@ void t4_db_dropped(struct adapter *adapter);
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int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
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int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
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u32 addr, u32 val);
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void t4_sge_decode_idma_state(struct adapter *adapter, int state);
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#endif /* __CXGB4_H__ */
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@ -2596,6 +2596,112 @@ int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
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return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
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}
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/**
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* t4_sge_decode_idma_state - decode the idma state
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* @adap: the adapter
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* @state: the state idma is stuck in
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*/
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void t4_sge_decode_idma_state(struct adapter *adapter, int state)
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{
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static const char * const t4_decode[] = {
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"IDMA_IDLE",
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"IDMA_PUSH_MORE_CPL_FIFO",
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"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
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"Not used",
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"IDMA_PHYSADDR_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
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"IDMA_PHYSADDR_SEND_PAYLOAD",
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"IDMA_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATA_FL_PREP",
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"IDMA_FL_REQ_DATA_FL",
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"IDMA_FL_DROP",
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"IDMA_FL_H_REQ_HEADER_FL",
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"IDMA_FL_H_SEND_PCIEHDR",
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"IDMA_FL_H_PUSH_CPL_FIFO",
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"IDMA_FL_H_SEND_CPL",
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"IDMA_FL_H_SEND_IP_HDR_FIRST",
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"IDMA_FL_H_SEND_IP_HDR",
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"IDMA_FL_H_REQ_NEXT_HEADER_FL",
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"IDMA_FL_H_SEND_NEXT_PCIEHDR",
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"IDMA_FL_H_SEND_IP_HDR_PADDING",
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"IDMA_FL_D_SEND_PCIEHDR",
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"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
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"IDMA_FL_D_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_PCIEHDR",
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"IDMA_FL_PUSH_CPL_FIFO",
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"IDMA_FL_SEND_CPL",
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"IDMA_FL_SEND_PAYLOAD_FIRST",
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"IDMA_FL_SEND_PAYLOAD",
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"IDMA_FL_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_NEXT_PCIEHDR",
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"IDMA_FL_SEND_PADDING",
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"IDMA_FL_SEND_COMPLETION_TO_IMSG",
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"IDMA_FL_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATAFL_DONE",
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"IDMA_FL_REQ_HEADERFL_DONE",
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};
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static const char * const t5_decode[] = {
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"IDMA_IDLE",
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"IDMA_ALMOST_IDLE",
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"IDMA_PUSH_MORE_CPL_FIFO",
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"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
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"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PCIEHDR",
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"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
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"IDMA_PHYSADDR_SEND_PAYLOAD",
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"IDMA_SEND_FIFO_TO_IMSG",
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"IDMA_FL_REQ_DATA_FL",
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"IDMA_FL_DROP",
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"IDMA_FL_DROP_SEND_INC",
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"IDMA_FL_H_REQ_HEADER_FL",
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"IDMA_FL_H_SEND_PCIEHDR",
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"IDMA_FL_H_PUSH_CPL_FIFO",
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"IDMA_FL_H_SEND_CPL",
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"IDMA_FL_H_SEND_IP_HDR_FIRST",
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"IDMA_FL_H_SEND_IP_HDR",
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"IDMA_FL_H_REQ_NEXT_HEADER_FL",
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"IDMA_FL_H_SEND_NEXT_PCIEHDR",
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"IDMA_FL_H_SEND_IP_HDR_PADDING",
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"IDMA_FL_D_SEND_PCIEHDR",
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"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
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"IDMA_FL_D_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_PCIEHDR",
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"IDMA_FL_PUSH_CPL_FIFO",
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"IDMA_FL_SEND_CPL",
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"IDMA_FL_SEND_PAYLOAD_FIRST",
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"IDMA_FL_SEND_PAYLOAD",
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"IDMA_FL_REQ_NEXT_DATA_FL",
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"IDMA_FL_SEND_NEXT_PCIEHDR",
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"IDMA_FL_SEND_PADDING",
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"IDMA_FL_SEND_COMPLETION_TO_IMSG",
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};
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static const u32 sge_regs[] = {
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SGE_DEBUG_DATA_LOW_INDEX_2,
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SGE_DEBUG_DATA_LOW_INDEX_3,
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SGE_DEBUG_DATA_HIGH_INDEX_10,
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};
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const char **sge_idma_decode;
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int sge_idma_decode_nstates;
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int i;
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if (is_t4(adapter->params.chip)) {
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sge_idma_decode = (const char **)t4_decode;
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sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
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} else {
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sge_idma_decode = (const char **)t5_decode;
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sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
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}
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if (state < sge_idma_decode_nstates)
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CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
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else
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CH_WARN(adapter, "idma state %d unknown\n", state);
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for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
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CH_WARN(adapter, "SGE register %#x value %#x\n",
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sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
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}
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/**
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* t4_fw_hello - establish communication with FW
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* @adap: the adapter
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@ -278,6 +278,9 @@
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#define SGE_DEBUG_INDEX 0x10cc
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#define SGE_DEBUG_DATA_HIGH 0x10d0
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#define SGE_DEBUG_DATA_LOW 0x10d4
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#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
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#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
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#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
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#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
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#define S_HP_INT_THRESH 28
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